Optimizing dominant time constant in RC
Lieven Vandenberghe, Stephen Boyd, and Abbas El Gamal
Information Systems Laboratory
Electrical Engineering Department
Stanford CA 94305
firstname.lastname@example.org u, email@example.com, firstname.lastname@example.org
Submitted to IEEE Transactions on Computer-Aided Design.
Updated versions, and source code for the examples, will be avail-able via anonymous ftp to isl.stanford.edu, or via WWW at URL http://www-isl.stanford.e du/p eop le/b oyd.
We propose to use the dominant time constant of a resistor-capacitor (RC) circuit as a mea-sure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this prop-erty to cast several interesting design problems as convex optimization problems, specically, semidenite programs (SDPs). For example, assuming that the conductances and capaci-tances are ane functions of the design parameters (which is a common model in transistor or interconnect wire sizing), one can minimize the power consumption or the area subject to an upper bound on the dominant time constant, or compute the optimal tradeo surface between power, dominant time constant, and area. We will also note that, to a certain extent, convex optimization can be used to design the topology of the interconnect wires.
This approach has two advantages over methods based on Elmore delay optimization. First, it handles a far wider class of circuits, e.g., those with non-grounded capacitors. Second, it always results in convex optimization problems for which very ecient interior-point methods have recently been developed.
We illustrate the method, and extensions, with several examples involving optimal wire and transistor sizing.
Research supported in part by AFOSR (under F49620-95-1-0318), NSF (under ECS-9222391 and EEC-9420565), MURI (under F49620-95-1-0525), and a gift from Synopsys.
Determining the optimal dimensions of the transistors and interconnect wires in a digital cir-cuit involves a tradeo between signal delay, area, and power dissipation. The conventional approach to optimal sizing is based on linear RC models and on the Elmore delay as a measure of signal propagation delay. This approach nds its origins in the work of Elmore[Elm48], Rubinstein, Peneld and Horowitz[RPH83], and Fishburn and Dunlop[FD85]. In particular, Fishburn and Dunlop were rst to observe that under certain conditions (the resistors form a tree with the input voltage source at its root and all capacitors are grounded) the Elmore delay of an RC circuit is a posynomial function of the conductances and capacitances. This observation has the important consequence that convex programming, specically geometric programming, can be used to optimize Elmore delay, area, and power consumption. Geo-metric programming forms the basis of the TILOS program and of several extensions and related programs developed since then [FD85, HSFK89, SSVFD88, ME87, SRVK93, Sap96]. In this paper we propose to use the dominant time constant as an alternative to the Elmore delay. The resulting method has two important advantages over methods based on Elmore delay optimization. First, a far wider class of circuits can be handled, including for example circuits with capacitive coupling between the nodes. We will give an example that illustrates the practical signicance of this extension. Second, the dominant time constant of a general RC circuit is a quasiconvex function of the design parameters, and it can be op-timized using convex optimization techniques (specically, semidenite programming). The Elmore delay, on the other hand, leads to convex optimization problems only for a very spe-cial class of circuits (which excludes, for example, circuits with loops of resistors). Moreover practical experience suggests that the numerical values of Elmore delay and dominant time constant are usually close.
The method will be illustrated with ve examples (Section 5). The rst two of these examples (x5.1 and x5.2) are applications that can also be handled with classical Elmore
delay optimization. They are included to show that, where they both apply, dominant time constant and Elmore delay minimization give very similar results. The next two examples (x5.3 and x5.4) are applications that cannot be handled using Elmore delay minimization
because of the presence of resistor loops in the circuit. These two examples will illustrate that, to a certain extent, convex optimization can be used to design the topology of the interconnect wires. The fth example (x5.5) is the best illustration of how much more general the new
technique is. Here we simultaneously determine the optimal sizes of interconnect wires and the optimal distances between them, taking into account capacitive coupling between neighboring wires. We will see that optimizing dominant time constant allows us to control not only the signal propagation delay, but also indirectly the crosstalk between the wires. This is not possible with Elmore delay minimization, since the Elmore delay is only dened for circuits with grounded capacitors. This example is of practical importance in deep submicron technologies where the coupling capacitance can be signicantly higher than the plate capacitance.
The outline of the rest of the paper is as follows. In x2 we describe the circuit model
considered in the paper and the special cases that we will encounter. We also explain how these dierent RC circuit models arise in MOS transistor and interconnect wire sizing. Inx3
node 1 node 2 noden node 0 u1 u2 un
ResistiveNetwork Capacitive Network i1 i2 v1 v2 vn in i=G(v?U) ?i=Cdv=dt
Figure 1: General RC circuit with n+ 1 nodes shown as a resistive network, a
capacitive network, and voltages sources.
we discuss three denitions of signal propagation delay. In x4 we show that optimizing
the dominant time constant leads to semidenite programming problems, a special class of convex optimzation problems for which very ecient methods have recently been developed. Section 5 contains the ve examples. In Section 6 we relate the three denitions of signal propagation delay. Section 7 gives a short discussion of the computational complexity.
2 Circuit models
2.1 General RC circuit
We consider linear resistor-capacitor (RC) circuits that can be described by the dierential equation
Cdvdt =?G(v(t)?u(t)); (1)
where v(t) 2
n is the vector of node voltages, u(t)
n is the vector of independent
voltage sources, C 2
is the capacitance matrix, and G 2
is the conductance matrix (see Figure 1). Throughout this paper we assume that C and G are symmetric and positive denite (i.e., that the capacitive and resistive subcircuits are reciprocal and strictly passive). In a few examples and the appendix we will also consider the case in whichC and
G are only positive semidenite, i.e., possibly singular.
We are interested in design problems in whichCandGdepend on some design parameters
m. Specically we assume that the matricesC and G are ane functions ofx, i.e.,
C(x) =C0+x1C1++xmCm; G(x) =G0+x1G1++xmGm; (2)
where Ci and Gi are symmetric matrices.
We will refer to a circuit described by (1) and (2) as a general RC circuit. We will also consider several important special cases, for example circuits composed of two-terminal elements, circuits in which the resistive network forms a tree, or all capacitors are grounded. We describe these special cases now.
mck Uk gk Ik
Figure2: Orientation of thekth branch voltageVkand branch currentIk in an RC
circuit. Each branch consists of a capacitorck0, and a resistor with conductance gk0 in series with an independent voltage source Uk.
2.2 RC circuit
When the general RC circuit is composed of two terminal resistors and capacitors (and the independent voltage sources) we will refer to it as an RC circuit. More precisely, consider a circuit with N branches and n+ 1 nodes, numbered 0 to n, where node 0 is the ground or reference node. Each branch k consists of a capacitor ck 0, and a conductance gk 0 in
series with a voltage source Uk (see Figure 2). Some branches can have a zero capacitance
or a zero conductance, but we will assume that both the capacitive subnetwork (i.e., the network obtained by removing all resistors and voltage sources), and the resistive subnetwork (i.e., the network obtained by removing all capacitors) are connected.
We denote the vector of node voltages by v 2
n, the vector of branch voltages by
N and the vector of branch currents by I
N. The relation between branch
voltages and currents is
Ik =ckdVdtk +gk(Vk?Uk); k = 1;:::;N: (3)
To obtain a description of the form (1), we introduce the reduced node-incidence matrix
nN and deneC and G as
Obviously, C and G are positive semidenite. Both matrices are also nonsingular if the capacitive and resistive subnetworks are connected. To see this, suppose that ck > 0 for
k = 1;:::;N+ and ck = 0 for k > N+. Then C = A+
diag(c+)AT+, where c+ is the vector
with the rst N+ components ofc, andA+ is the matrix formed by the rst N+ columns of
A (i.e., the reduced node-incidence matrix of the capacitive subnetwork). Since a reduced node-incidence matrix of a network is of full row rank if and only if the network is connected,
A+ must have rank n, and hence C must be positive denite. In a similar way one can show
that G is positive denite if the resistive subnetwork is connected.
Using Kirchho's laws AI = 0 and V = ATv, it is now straightforward to write the
branch equations (3) as (1) with u=G?1A
vin g1 g2 g3 g4 g5 g6 c7 c8 c9 c10 c11 1
Figure 3: Example of a grounded capacitor RC tree.
For future use we note that for this class of circuitsCandGhave the following well-known form: for i= 1;:::;n, Gii= X k2N(i) gk; Cii = X k2N(i) ck;
where the summations extend over all branches connected to node i, and, for i;j = 1;:::;n,
i6=j, Gij=? X k2N(i;j) gk; Cij=? X k2N(i;j) ck
where the summations are over all branches between nodes i and j. In particular, the diagonal elements ofC andGare positive and the o-diagonal elements are negative. It can also be shown that the matrices R=G?1 and C?1 are elementwise nonnegative.
From the expressions for the matrices Gand C (4), we see that they are ane functions of the design parameters x, if each of the conductances gk and capacitancesck is.
2.3 Grounded capacitor RC circuit
It is quite common that all capacitors in the RC circuit are connected to the ground node. In this case the matrix C is diagonal and nonsingular if there is a capacitor between every node and the ground. We will refer to circuits of this form as grounded capacitor RC circuits.
2.4 Grounded capacitor RC tree
The most restricted class of circuits considered in this paper consists of grounded capacitor RC circuits in which the resistive branches form a tree with the ground node as its root. Moreover only one resistive branch is connected to the ground node, and it contains the only voltage source in the circuit. An example is shown in Figure 3.
Note that the resistance matrix R =G?1 for a circuit of this class can be written down
resistances upstream from node i and node j; (5) 4
i.e., to nd Rij we add all resistances in the intersection of the unique path from nodei to
the root of the tree and the unique path from nodej to the root of the tree. For the example in Figure 3, we obtain R = 2 6 6 6 6 6 6 6 6 4 r1 r1 r1 r1 r1 r1 r1 r1+r2 r1 +r2 r1 r1 r1 r1 r1+r2 r1+r2+r3 r1 r1 r1 r1 r1 r1 r1+r4 r1+r4 r1 +r4 r1 r1 r1 r1+r4 r1+r4+r6 r1 +r4 r1 r1 r1 r1+r4 r1+r4 r1+r4+r5 3 7 7 7 7 7 7 7 7 5 where ri = 1=gi.
One can also verify that in a grounded capacitor RC tree with input voltage vin(t), the
vector u(t) in (1) is equal to u(t) =vin(t)e where e is the vector with all components equal
Linear RC circuits are often used as approximate models for transistors and interconnect wires. When the design parameters are the physical widths of conductors or transistors, the conductance and capacitance matrices are ane in these parameters, i.e., they have the form (2).
An important example is wire sizing, where xi denotes the width of a segment of some
conductor or interconnect line. A simple lumped model of the segment consists of asection: a series conductance, with a capacitance to ground on each end. Here the conductance is linear in the width xi, and the capacitances are linear or ane. We can also model each
segment by many such sections, and still have the general form (1), (2).
Another important example is an MOS transistor circuit where xi denotes the width of
a transistor. When the transistor is `on' it is modeled as a conductance that is proportional to xi, and a source-to-ground capacitance and drain-to-ground capacitance that are linear
or ane in xi.
We are interested in how fast a change in the input u propagates to the dierent nodes of the circuit, and in how this propagation delay varies as a function of the resistances and capacitances. In this section we introduce three possible measures for this propagation delay: the threshold delay, which is the most natural measure but dicult to handle mathematically; the Elmore delay, which is widely used in transistor and wire sizing; and the dominant time constant. We will compare the three delay measures in the examples of x5 where we will
observe that their numerical values are usually quite close. More theoretical details on the relation between these three measures will be presented in x6, including some bounds that
they must satisfy.
We assume that for t <0, the circuit is in static steady-state with u(t) =v(t) =v?. For
t0, the source switches to the constant value u(t) =v+. As a result we have, for t 0,
which converges, as t ! 1, to v+ (since our assumption C > 0, G > 0 implies stability).
The dierence between the node voltage and its ultimate value is given by ~
and we are interested in how large t must be before this is small.
To simplify notation, we will relabel ~v asv, and from here on study the rate at which
v(t) = e?C
becomes small. Note that this v satises the autonomous equation Cdv=dt=?Gv.
It can be shown that for a grounded capacitor RC circuit the matrixe?C ?1Gt
is element-wise nonnegative for allt0 (see Berman and Plemmons[BP94, Theorem 3.12]). Therefore,
if v(0) 0 (meaning, vk(0) 0 for k = 1;:::;n) in (7), the voltages remain nonnegative,
i.e., for t0 we have
Also note that in a grounded capacitor RC tree, the steady-state node voltages are all equal. When discussing RC trees, we will therefore assume without loss of generality that the input switches from zero to one at t= 0, i.e., v? = 0, v+ =e in (6), or, for the autonomous
model, that v(0) =e in (7).
3.1 Threshold delay
In many applications the natural measure of the delay at nodek is the rst time after which
vk stays below some given threshold level >0, i.e.,
Tkthres = inf
fT j jvk(t)j for tT g:
We will call the maximum threshold delay to any node the critical threshold delay of the circuit: Tthres = max fT thres 1 ;:::;Tnthresg= inff T j kv(t)k 1 for tT g; where kk
1 denotes the innity norm, dened by kzk
1 = maxi
jzij. The critical threshold
delay is the rst time after which all node voltages are less than.
The critical threshold delay Tthres depends on the design parameters xthrough (7), i.e.,
in a very complicated way. Methods for direct optimization of Tthres are inecient and also
local, i.e., not guaranteed to nd a globally optimal design.
t vk(t) Tkthres Tkelm Tkthres vk(0)
Figure 4: Graphical interpretation of the Elmore delay at node k. Tkthres is the
threshold delay at nodek. The area below vk, which is shaded lightly, isTkelm. The
darker shaded box, which lies below vk, has area Tkthres. From this it is clear that
when the voltage is nonnegative and monotonically decaying,TkthresTkelm.
3.2 Elmore delay
In[Elm48], Elmore introduced a measure of the delay to a node that depends on C and
G (hence, x) in a simpler way than the threshold delay, and often gives an acceptable approximation to it. The Elmore delay to node k is dened as
WhileTkelmis always dened, it can be interpreted as a measure of delay only whenvk(t)
for allt0, i.e., when the node voltage is nonnegative. (Which is the case, as we mentioned,
in grounded capacitor RC circuits with v(0)0.)
In the common case that the voltages decay monotonically, i.e., dvk(t)=dt 0 for all
t0, we have the simple bound
which can be derived as follows. Assuming vk is positive and nonincreasing, we must have
vk(t) > for t < Tkthres. Hence the integral of vk must exceed Tkthres (see Figure 4). The
monotonic decay property holds, for example, for grounded capacitor RC trees (see [RPH83, Appendix C]).
We can express the Elmore delay in terms of G, C, andv(0) as
where ek is the kth unit vector. Thus the vector of Elmore delays is given by the simple
expression RCv(0), where R = G?1 is the resistance matrix. We dene the critical Elmore
delay as the largest Elmore delay at any node, i.e., Telm = maxkTkelm.
For a grounded capacitor RC circuit with v(0) 0 we can express the critical Elmore
delay as Telm = kG ?1Cv(0) k 1;
by noting that the matrix G?1C = RC is elementwise nonnegative. If v(0) = e (as in a
grounded-capacitor RC tree) we can also write
Telm= max k eTkG?1Ce =kG ?1C k 1: (8) 7
(For a matrixA2
1is the maximum row sum ofA, i.e., kAk
1= maxi=1;:::;n P
3.3 Dominant time constant
In this paper we propose using the dominant time constant of the RC circuit as a measure of the delay. We start with the denition. Let 1;:::;n denote the eigenvalues of the circuit,
i.e., the eigenvalues of ?C
?1G, or equivalently, the roots of the characteristic polynomial
det(sC+G). They are real and negative since they are also the eigenvalues of the symmetric, negative denite matrix
C1=2 ?C ?1G C?1=2= ?C ?1=2GC?1=2 (which is similar to ?C
?1G). We assume they are sorted in decreasing order, i.e.,
0> 1 n:
The largest eigenvalue, 1, is called the dominant eigenvalue or dominant pole of the RC
Each node voltage can be expressed in the form
which is a sum of decaying exponentials with rates given by the eigenvalues. We dene the dominant time constant at the kth node as follows. Let p denote the index of the rst nonzero term in the sum (9), i.e.,ik= 0 for i < pand ip6= 0. (Thus, the slowest decaying
term invk isipept.) We call p the dominant eigenvalue at nodek, and the dominant time
constant at node k is dened as
In most cases,vk contains a term associated with the largest eigenvalue1, in which case we
simply have Tkdom =?1=1.
The dominant time constant Tkdom measures the asymptotic rate of decay of vk(t), and
there are several ways to interpret it. For example,Tkdom is the smallest numberT such that
holds for some and allt0.
The (critical) dominant time constant is dened as Tdom = maxkTkdom. Except in the
pathological case when v(0) is decient in the eigenvector associated with 1, we have
In the sequel we will assume this is the case.
Note that the dominant time constant Tdom is a very complicated function of G and C,
i.e., the negative inverse of the largest zero of the polynomial det(sC+G). The dominant time constant can also be expressed in another form that will be more useful to us:
Tdom = min
f T j TG?C0 g:
This form has another advantage: it makes sense and provides a reasonable measure of delay in the case whenC and Gare only positive semidenite (i.e., possibly singular). We will see this in several of the examples; the details are given in Appendix A.
4 Dominant time constant optimization
In this section we show how several important design problems involving dominant time constant, area, and power, can be cast as convex or quasiconvex optimization problems that can be solved very eciently.
4.1 Dominant time constant specication as linear matrix
The dominant pole1 can be expressed as
1 = inffj C(x) +G(x)0g; (11)
and hence, in particular,1C(x) +G(x)0. Another consequence of (11) is
Tmax ()TmaxG(x)?C(x)0: (12)
This type of constraint is called a linear matrix inequality (LMI): the left hand side is a symmetric matrix, the entries of which are ane functions of x. It can be shown that the set of vectors x that satisfy (12) is convex.
We conclude that Tdom is a quasiconvex function ofx, i.e., its sublevel sets
n x T dom(x) Tmax o
are convex sets for allTmax. Quasiconvexity can also be expressed as: for 2[0;1],
i.e., as the design parameters vary on a segment between two values, the dominant time constant is never any more than the largest of the two dominant time constants at the endpoints.
Linear matrix inequalities have recently been recognized as an ecient and unied rep-resentation of a wide variety of nonlinear convex constraints. They arise in many dierent elds such as control theory and combinatorial optimization (for surveys, see [BEFB94, NN94, VB96, LO96, Ali95]). Most importantly for us, many convex and quasiconvex op-timization problems that involve LMIs can be solved with great eciency using recently developed interior-point methods.
4.2 Optimization over LMIs
Here we briey describe several common convex and quasiconvex optimization problems over LMIs.
The most common problem is semidenite programming (SDP), in which we minimize a linear function subject to a linear matrix inequality:
subject to A(x)0;
where A(x) = A0 +x1A1 + + xmAm, Ai = ATi. Semidenite programs are convex
optimization problems, and can be solved very eciently (see, e.g., [NN94, VB96]). Some public domain general-purpose SDP software packages are sp[VB94], sdpsol[WB96], and
We can handle multiple LMI constraints in SDP (13) by representing them as one big block diagonal matrix. We can also incorporate a wide variety of convex constraints onxby representing them as LMIs. For example, we can represent an SDP with additional linear inequalities on x, minimize cTx subject to A(x)0 fTixgi; i= 1;:::;p (14) as the SDP minimize cTx subject to " A(x) 0 0
diag(g1?fT1x;:::;gp?fTpx) # 0: (15) In the sequel we will simply refer to a problem such as (14), which is easily transformed to an SDP in the standard form (13), as an SDP.
Another common problem has the form minimize
subject to B(x)?A(x)0
(16) where A, B, and C are symmetric matrices that are ane functions of x, and the variables are x and 2
R. This problem is called the generalized eigenvalue minimization problem
(GEVP). GEVPs are quasiconvex and can be solved very eciently using recently developed interior-point methods. See Boyd and El Ghaoui [BE93], Haeberly and Overton [HO94], and Nesterov and Nemirovsky [NN94, NN95, Nem94] for details on specialized algorithms.
4.3 Minimum area subject to bound on delay
We now return to circuit optimization problems. We suppose the area of the circuit is a linear (or ane) function of the variables xi. This occurs when the variables represent the
widths of transistors or conductors (with lengths xed as li), in which case the circuit area
has the form
where a0 is the area of the xed part of the circuit.
We can minimize the area subject to a bound on the dominant time constantTdom
and subject to upper and lower bounds on the widths by solving the SDP minimize Xm i=1lixi subject to TmaxG(x)?C(x)0 xmin xi xmax; i= 1;:::;m: (17) 10
By solving this SDP for a sequence of values of Tmax, we can compute the exact optimal
tradeo between area and dominant time constant. The optimal solutions of (17) are on the tradeo curve, i.e., they are Pareto optimal for area and dominant time constant.
4.4 Minimum power dissipation subject to bound on delay
The total energy dissipated in the resistors during a transition from initial voltagev to nal voltage 0 (or between 0 andv) is the energy stored in the capacitors, i.e., (1=2)vTCv.
There-fore for a xed clock rate and xed probability of transition, the average power dissipated in proportional to vTC(x)v =Xm i=1xk vTCiv ;
which is a linear function of the design parameters x.
Therefore we can minimize power dissipation subject to a constraint on the dominant time constant by solving the SDP
subject to TmaxG(x)?C(x)0
xmin xi xmax; i= 1;:::;m:
We can also add an upper bound on area, which is a linear inequality. By solving this SDP for a sequence of values of Tmax, we can compute the optimal tradeo between power
dissipation and dominant time constant. By adding a constraint that the area cannot exceed
Amax, and solving the SDP for a sequence of values of Tmax and Amax, we can compute the
exact optimal tradeo surface between power dissipation, area, and dominant time constant.
4.5 Minimum delay subject to area and power constraints
We can also directly minimize the delay subject to limits on area and power dissipation, by solving the GEVP
subject to TG(x)?C(x)0
xmin xi xmax; i= 1;:::;m
fTixgi; i= 1;2
with variables x and T, where the linear inequalities limit area and power dissipation.
4.6 Comparison with Elmore delay optimization
We briey describe how Elmore delay can be optimized, in order to compare it with the methods for dominant time constant optimization we have described above.
Elmore delay is optimized only in a very special case: grounded capacitor RC trees where each conductance is proportional to exactly one variable. From (5) and (8) we see that the Elmore delay to nodek can be written in the form
ij ijci=gj (18)
where the coecients ij are either zero or one. For example the Elmore delay to the third
node of the circuit in Figure 3 is
T3elm=c9(r1+r2+r3) +c8(r1+r2) +c7r1+c10r1+c12r1+c11r1:
Suppose eachci is ane in the variablex, and eachgiis proportional to exactly one variable.
Then (18) simplies to a function of the form
f(x1;:::;xn) = N X j=1j m Y i=1x ij i : (19)
where the coecients j are nonnegative and the exponents ij can be ?1, 0, or +1. A
function of the form (19) (with ij arbitrary real numbers) is called a posynomial function,
and an optimization problem of the form minimze f0(x)
subject to fi(x)1; i= 1;:::;n
x >0; (20)
where all functionsfiare posynomial, is called a geometric programming problem. Geometric
programming problems can be cast as convex optimization problems by the following simple change of variables. Dening yi = logxi, and expressing the function (19) in terms of y, we
obtain f(ey1;:::;eym) =X j jexp m X i=1ijyi ! ;
which is convex in y. Applying this transformation to each of the functions in (20) yields a convex optimization problem in the variables y.
This fact was exploited in the TILOS program of Fishburn and Dunlop[FD85] for Elmore delay minimization, and in several more recent approaches to Elmore delay minimization in transistor and wire sizing (for examples, see [SSVFD88, HNSLS90, SRVK93, Sap96]).
We conclude this section by listing some limitations of the Elmore delay, and contrasting them with the dominant time constant. The main dierence is that the dominant time constant always leads to tractable convex or quasiconvex optimization problems, with no restrictions on circuit topology. In particular:
The circuits may contain loops of resistors. Although for grounded capacitor RC
circuits with loops of resistors, the Elmore delay is still a meaningful approximation of signal delay (see Lin and Mead[LM84] and Wyatt[Wya85, Wya87]), it does not have a simple posynomial form as it does for RC trees, and convex optimization cannot be used to minimize it.
The circuits may contain non grounded capacitors (i.e., the matrix C in (1) may be
nondiagonal). As we have seen, the voltagesvk(t) can be negative in this case, and the
Elmore delay is not a good measure for signal delay.
Elmore delay gives the delay from one input node to one output node. The dominant
time constant applies also to circuits with multiple input voltages. 12
The Elmore delay in an RC tree is a posynomial function if the conductances depend
on one variable only. For dominant time constant optimization the conductance and capacitances can be general ane functions of the variables.
The examples in the next section will illustrate these dierences. The rst two are applica-tions to which Elmore delay would also apply, with very similar results. The third and fourth example illustrate the application to circuits with loops of resistors. The fth example has non-grounded capacitors.
ixi ixi ixi
Figure 5: Optimal wire sizing. A voltage source and conductance drive a capacitor
through a wire modeled as 20 -segments with (xed) lengthsli and widths (to be
5.1 Wire sizing
In the rst example we consider the problem of sizing an interconnect wire that connects a voltage source and conductance G to a capacitive load C. We divide the wire into 20 segments of length li, and width xi, i = 1;:::;20, which is constrained as 0 xi Wmax.
(We include this constraint just to show that it is readily handled.) The total area of the interconnect wire is thereforeP
ilixi. We use amodel of each wire segment, with capacitors
ixi and conductanceixi. This is shown in Figure 5.
We used the following parameter values in our numerical simulation:
G= 1:0; C = 10; li = 1; i = 1:0; i = 0:5; Wmax = 1:
To minimize the total area subject to the width bound and a bound Tmax on dominant
time constant, we solve the SDP
subject to TmaxG(x)?C(x)0
0xi Wmax; i= 1;:::;20:
By solving this SDP for a sequence of values of Tmax that range between 300 and 2000, we
can compute the optimal area-delay tradeo for this example, which is shown in Figure 6. We emphasize that the tradeo curve shown is the absolute tradeo curve between the competing objectives, i.e., area and dominant time constant. This is a consequence of the guaranteed global optimality of the solutions computed using semidenite programming.
The general shape of the tradeo curve is not a surprise: by increasing total area, we can reduce the dominant time constant. In this case the optimal tradeo curve happens to be approximately hyperbolic, i.e., it is approximately described by
2 4 6 8 10 12 14 16 18 200 400 600 800 1000 1200 1400 1600 1800 2000 area dominan ttime constan t A A A U (a) A A A U (b) A A A U (c) H H H Y (d)
Figure 6: Area-delay tradeo curve. The curve shows the (globally) optimal
trade-o curve between twtrade-o ctrade-ompeting trade-objectives: the ttrade-otal area trade-of the wire and the dominant time constant of the circuit. The solution for the four points marked on the curve is shown in Figure 7.
(the minimum value of the area-delay product is 4700 and the maximum value is 6180). Figure 7 shows the solution x at the four points marked on the tradeo curve. The general shape of these plots match what we would expect. The interconnect wire decreases in size as we move from the drive end towards the other end, since less current is needed to charge or discharge the capacitances farther down the line. As expected, this eect is more pronounced in the large, fast design (a), and much less evident in the small, slow design (d). We can see that the wire width limit becomes active only when the dominant time constant specication is smaller than 400 (or equivalently, the total area exceeds 14.5).
Figure 8 shows the step responses at the 21 nodes along the wire, for the two solutions marked (a) and (d) on the tradeo curve. Note that in design (d) the voltage at the rst nodes along the wire increases faster than in design (a), while the response at the end of the wire is much slower. This is easily explained. Since the capacitors in design (d) are much smaller than in (a), the voltage at the rst nodes increases faster than in (a). However, since the resistances along the wire are larger in (d), the voltages at the last stages increase much more slowly. The dashed lines indicate the dominant time constant and the Elmore and 50%-threshold delays at the end node. We see that in both cases the dominant time constant is a reasonable approximation of the 0.5-threshold delay, and that Telm and Tdom
are very close.
Finally, note that the circuit is a grounded capacitor RC tree, and therefore the same designs could be done using Elmore delay instead of dominant time constant. In this example, simple wire sizing via dominant time constant optimization seems to produce results very close to wire sizing via Elmore delay optimization.
0 0.5 1 0 0.5 1 0 0.3 0.6 0 2 4 6 8 10 12 14 16 18 20 0 0.2
Figure 7: Solution at four points on the tradeo curve. The top gure is the
solution (a). The bottom gure is solution (d). The plots show wire width as a function of position. Each segment has unit length.
0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 time voltage Tdom ? ? Telm Tthres 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 time voltage @ @ R Tdom ? ? Telm @ @ R Tthres
Figure 8: Step responses at the 21 nodes. Left. Step responses for the solution
marked (a). Right. Step responses for the solution marked (d). The vertical lines show Tthres, the 50% threshold delay (i.e., = 0:5) at the output node,Tdom, the
dominant time constant, andTelm, the Elmore delay.
d2 d1 C xi xi xi t vout vin x1 x20 x21 x40 d C0+cd gd xi vin vout
Figure 9: Optimization of wire and repeater sizes. The lefthand driver drives an
interconnect wire, modeled as 20 RC segments connected to a repeater, which
drives a capacitive load through another 20 segment wire. The problem is to deter-mine the sizes of the wire segments (x1, ..., x40) as well as the sizes of the driver
and repeaterd1 and d2.
5.2 Combined sizing of drivers, repeaters, and wire
Figure (9) depicts two repeaters inserted in an interconnect wire. The wires are divided in 20 segments each. The segments are modeled as-segments with capacitance and conductance proportional to the segment widths. The dimensions of a repeater are characterized by one number d. The input capacitance of the repeater is ane in d: C0 +cd; the output
conductance is linear in d: gd. For the dynamics of the repeater we use a simplied model and assume that the output of the repeater is a perfect step input triggered when the input crosses a certain threshold. In this example we assume that the output of the rst repeater is a perfect unit step at timet = 0 and that the output of the second repeater is a unit step at t =T1dom, where T1dom is the dominant time constant of the rst stage. We assume that
the total area is equal to L(d1+d2) +P40
i=1lixi, where li is the length of the ith segment,
and L(d1+d2) is the area of the drivers.
The numerical values used in the calculations are
g = 1; C0 = 1; c= 3; = 5; = 0:1; C = 50; li = 1; L= 10:
We also impose a maximum wire width of 2.
We want to minimize area subject to bound on the combined delay T1dom+T2dom of the
two stages. However, the sum of two quasiconvex functions is not quasiconvex, and therefore, minimizing the total area subject to a bound on T1dom+T2dom is not a convex optimization
problem. A reasonable sub-optimal solution consists in dividing the total allowed delay equally over the two stages. In other words we will replace the nonconvex constraintT1dom+
Tmax by two convex constraints
20 40 60 80 100 120 140 160 150 200 250 300 350 400 450 500 area total dela y ? ? (a)
Figure 10: Area-delay tradeo. The area is 10(d1 +d2) + P
ixi. The delay is
equally distributed over the two stages, i.e., total delay less than Tmax means that T1dom Tmax=2 and T2domTmax=2, where T1dom and T2dom are the dominant time
constants of the rst and second stage, resp. The solution marked (a) is shown in Figure 11.
This leads to the optimization problem
minimize L(d1+d2) + 40 X i=1lixi subject to 0 xi 2; i= 1;:::;40 d1;d2 0 (Tmax=2)(G1(x;d1;d2)?C1(x;d2)0 (Tmax=2)(G2(x;d2)?C2(x)0; (21) where G1 2
is the conductance matrix of stage 1, C1 2
is a diagonal matrix with the total capacitance at the nodes of stage 1 as its elements, G2 2
2121 is the
con-ductance matrix of stage 2 and C2 2
2121 is a diagonal matrix with the total capacitance
at the nodes of stage 2 as its elements.
Note that the two stages are almost uncoupled; only the size of the second repeater (d2)
couples the two stages, since it varies the capacitive load on the end of the rst wire, and also determines the drive conductance for the second wire.
The tradeo curve computed by solving the SDP (21) for a sequence of values Tmax is
shown in Figure 10. The solution marked (a) is shown in Figures 11 and 12.
0 10 20 0 10 20 −5 −4 −3 −2 −1 0 1 2 3 4 5
Figure 11: Solution for the point on the tradeo curve. Figure show the widths
of the 20 segments of both wires. The rectangular blocks on the left and in the middle have area 10d1 and 10d2, i.e., the scale is such that the total shaded area is
proportional to theL(d1+d2) + P lixi. 0 50 100 150 200 250 300 350 400 450 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 time voltage A A A U T1dom ? ? T1elm ? ? T1thres ? ? ? T1dom+T2dom T1dom+T2elm T1dom+T2thres
Figure 12: Step responses for solution (a). The gure shows the step response at
the last node of the rst wire, assuming that the output of the rst driver goes up at t= 0, and the step response at the last node of the second wire assuming that
the output of the second driver goes up at t=T1dom.
xi ixi ixi ixi G x1 x2 x3 x4 x6 x5 C 1
Figure 13: Interconnect network with 4 nodes, connected by 6 wire segments,
shown as rectangles. The wire segments are modeled as-segments of lengthli and
width xi, shown at right. Note that only 3 wire segments are required to connect
the 4 nodes; the 6 wire segments include 3 loops.
5.3 Wire sizing and topology design
In the third example we size the wires for an interconnect circuit with four nodes, as shown in Figure 13. This example illustrates two important extensions. First, the topology of the circuit is more complex; the wires do not even form a tree. As a result, conventional Elmore delay minimization, based on geometric programming, cannot be applied. (Elmore delay minimization for circuits with meshes yields hard non-convex optimization problems.) Secondly, we will use this example to illustrate that, to a certain extent, convex optimization can be used to design the topology of interconnections. Note that this is an example of a grounded capacitor RC circuit.
The numerical values of the parameters are:
G= 0:1; C = 10; 1 =2 = 10; 3 = 100; 4 =5 = 1; i = 1:0; li = 1:
Since we take li = 1, the area of the circuit is simplyP
Figure 14 shows the optimal tradeo curve between area and dominant time constant. In this example the tradeo curve has interesting structure, with three `regions' that correspond to dierent interconnect topologies (see below).
Figure 15 shows the solution for the three points marked on the tradeo curve. The left gures show the circuit, with the optimal width mentioned above each segment (and segments with zero width not shown). The interpretation of the third solution requires some explanation. The optimal values of the widths are x3 = 0:027 and xi = 0 for i 6= 3,
which means that all conductances and capacitances connected to node 4 are zero. The interpretation of this solution poses no problem: we can simply delete node 4 from the
0 0.1 0.2 0.3 0.4 0.5 0.6 100 200 300 400 500 600 700 800 ? ? (a) ? ? (b) ? ? (c) area dominan ttime constan t
Figure 14: Tradeo curve. Optimal tradeo between area and dominant time
constant for the circuit in Figure 13. The solutions at the three points marked (a), (b), (c) are given in Figure 15.
circuit. Note however that the conductance and capacitance matrices are both singular:
G= 2 6 6 6 4 0:127 0:000 ?0:027 0:000 0:000 0:000 0:000 0:000 ?0:027 0:000 0:027 0:000 0:000 0:000 0:000 0:000 3 7 7 7 5 ; C =
diagh 2:727 0:000 12:727 0:000 i ;
and therefore the assumptions we made in x2 do not hold. In particular, the equation
det(C +G) = 0 has an innite number of solutions, so the number of eigenvalues of the pencil (G;?C) is innite. However, the dominant time constant
is still well dened, and yields Tdom = 600. We will discuss the case of singular G or C in
more detail in Appendix A.
The right half of Figure 15 shows the step responses at the dierent nodes, and the values of the dominant time constant and the critical Elmore delay (the Elmore delay at node 3). We can observe that the critical Elmore delay and the dominant time constant are quite close, and that the dominant time constant is a reasonable approximation for the 50%-threshold delay at the output node.
Note also the interesting fact that for design (b), the interconnect circuit has loops, which is certainly not a conventional design. Nevertheless this circuit has smaller area than any loop-free design with the same dominant time constant.
x4 = 0:23 x6 = 0:22 1
m0 100 200 300 400 500 600 700 800 900 1000 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ? ? v1(t) @ @ I v3(t) v4(t) Tdom ? ? Telm @ @ R Tthres time voltage x6 = 0:037 x4 = 0:038 x3 = 0:036 1
m0 100 200 300 400 500 600 700 800 900 1000 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ? ? v1(t) @ @ I v3(t) v4(t) Tdom ? ? Telm @ @ R Tthres time voltage 1
mx3 = 0:027 4
j0 100 200 300 400 500 600 700 800 900 1000 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ? ? v1(t) @ @ I v3(t) Tdom ? ? Telm @ @ R Tthres time voltage
Figure 15: Solutions. The solutions at the three points marked on the tradeo
curve (top: solution (a), middle: solution (b), bottom: solution (c)). The left gures show the circuit with the optimal segment widths xi. The segments that are not
shown have width zero. The right gure shows the step responses at the dierent nodes. The vertical lines give the values of the dominant time constant Tdom, the
Elmore delay Telm at the output node, and the 0:5-threshold delay Tthres, at the
output node 3.
C C C G G G G G G 1
mC C C i
mxij=lij xijlij xijlij
Figure 16: Tri-state bus sizing and topology design. The circuit on the left
repre-sents a tri-state bus connecting six nodes. Each pair of nodes is connected through a wire, shown as a dashed line, modeled as a segment shown at right. Note that
we have fteen wires connecting the nodes, whereas only ve are needed to connect them. In this example, as in the previous example, we will use dominant time con-stant optimization to determine the topology of the bus as well as the optimal wire sizes xij: optimalxij's which are zero correspond to unused wires. The bus can be
driven from any node. When nodeidrives the bus, theith switch is closed and the
others are all open.
5.4 Tri-state bus sizing and topology design
In this example we optimize a tri-state bus connecting six nodes. The example will again illustrate that dominant time constant minimization can be used to (indirectly) design the optimal topology of a circuit.
The model for the bus is shown in Figure 16. Each pair of nodes is connected by a wire (shown as a dashed line), which is modeled as a -segment, as shown at right in the gure. (Since in the optimal designs many of the wire segments will have width zero, it is perhaps better to think of the fteen segments as possible wire segments.) The capacitance and the conductance of the wire segment between nodei and node j depend on its physical dimensions, i.e., on its length lij and width xij: the conductance is proportional to xij=lij;
the capacitance is proportional to xijlij. The lengths of the wires are given; the widths will
be our design variables. The total wire area is P
The bus can be driven from any node. When nodeidrives the bus, theith switch is closed and the others are all open. Thus we really have six dierent circuits, each corresponding to a given node driving the bus. To characterize the threshold or Elmore delay of the bus we need to consider 36 dierent delays: the delay to node iwhen node j acts as driver. We are interested in the largest of these 36 delays, i.e., the delay for the worst drive/receive pair. To constrain the dominant time constant, we require that the dominant time constant of each of the six drive conguration circuits has dominant time constant less than Tmax. In
Figure 17: Position of the six nodes. The length lij of the wire between each
two nodesiand jin Figure 16 is the`1-distance (Manhattan-distance) between the
pointsiand j in this gure. The squares in the grid have unit size.
0 10 20 30 40 50 60 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 area dominan ttime constan t A A A U (a) H H H Y (b)
Figure 18: Area-delay tradeo.
other words, if Tidom is the dominant time constant of the RC-circuit obtained by closing
the switch at node i and opening the other switches, then Tdom= maxiTi is the measure of
dominant time constant for the tri-state bus.
The numerical values used in the calculation are:
G= 1; C = 10; = 0:5; = 1:
The wire sizes are limited to a maximum value of 1:0. We assume that the geometry of the bus is as in Figure 17, and that the length lij of the wire between nodes iand j is given by
the `1-distance (Manhattan distance) between points i and j in Figure 17.
Figure 18 shows the tradeo curve between maximum dominant time constant Tdom and
the bus area. This tradeo curve was computed by solving the following SDP for a sequence 24
1 4 5 6 2 3 1 2 3 4 5 6
Figure 19: Solutions marked on the tradeo curve. The left gure shows the line
widths for solution (a). The thickness of the lines is proportional to xij. The
size of the wires between (1,5), (2,4), (3,4) and (3,6) is equal to the maximum allowed value of one. There is no connection between node pairs (2,6), (3,5), (4,5) and (4,6). The right gure is the solution marked (b) on the tradeo curve. The thickest connection is between nodes (3,4) and has width 0.14. Again all connections are drawn with a thickness proportional to their width xij. In this solution the
connections between (1,4), (2,3), (2,5), (2,5), (2,6), (3,5), (4,5) and (4,6) are absent. (Note when comparing both gures, that a dierent scale was used for the widths in both gures. The sizes in the right gure are roughly seven times smaller than in the left gure.)
of values ofTmax:
subject to 0 xij 1
Tmax( ~G(x) +GEkk)?C(x)0; k= 1;:::;6:
Here x denotes the vector with components xij (in any indexing order), ~G(x) denotes the
conductance matrix of the circuit when all switches are open, andC(x) is the diagonal matrix with as its ith element the total capacitance at node i. The matrix Ekk is zero except for
the kth diagonal element, which is equal to one. The six dierent LMI constraints in the above SDP correspond to the six dierent RC-circuits we have to consider. The conductance matrix for the circuit with switch k closed is ~G with G added to its kth diagonal element, so thekth LMI constraint states that the dominant time constant of the circuit with switch
k closed is less thanTmax.
Figure 19 shows the optimal widths for the two solutions marked (a) and (b) on the tradeo curve. The connections in the gure are drawn with a thickness proportional to
xij. (Note however that the scales are not the same in the left and right gure.) Note
again that the topology of both designs are dierent: Solution (a), which is faster, uses more connections than solution (b). Also note that in both cases the optimal topologies have loops.
Figure 20 shows all step responses for both solutions. The results conrm what we expect. The smallest delay arises when the input node is 1 or 2 (the two top rows in the gure), since they lie in the middle. The delay is larger when the input node is one of the four other nodes. Note that, in both solutions, Tdom is equal in four of the six cases.
0 0.5 1 v1 ? ? v2 B B B B M v3 A A A K v4 v5 @ @ I v6 ? ? ? Tdom Telm Tthres voltage v1 ? ? v2 B B B B M v3 @ @ I v4 v5 A A A K v6 ? ? ? Tdom Telm Tthres 0 0.5 1 ? ? v1 v2 A A A K v3 v4 @ @ I v5 B B B B M v6 ? ? ? Tdom Telm Tthres voltage ? ? v1 v2 A A A K v3 v4 @ @ I v5 B B B B M v6 ? ? ? Tdom Telm Tthres 0 0.5 1 @ @ I v1 A A A K v2 v3 v4 B B B B M v5 ? ? v6 ? ? ? Tdom Telm Tthres voltage B B B B M v1 A A A K v2 v3 v4 @ @ I v5 ? ? v6 ? ? ? Tdom Telm Tthres 0 0.5 1 @ @ I v1 ? ? v2 v3 v4 A A A K v5 B B B B M v6 ? ? ? Tdom Telm Tthres voltage @ @ I v1 v2 ? ? v3 v4 B B B B M v5 A A A K v6 ? ? ? Tdom Telm Tthres 0 0.5 1 v1 @ @ I v2 A A A K v3 B B B B M v4 v5 ? ? v6 ? ? ? Tdom Telm Tthres voltage v1 @ @ I v2 A A A K v3 B B B B M v4 v5 ? ? v6 ? ? ? Tdom Telm Tthres 0 100 200 300 400 500 600 700 800 900 1000 0 0.5 1 @ @ I v1 A A A K v2 v3 B B B B M v4 ? ? v5 v6 ? ? ? Tdom Telm Tthres voltage time 0 500 1000 1500 2000 2500 3000 @ @ I v1 B B B B M v2 ? ? v3 A A A K v4 v5 v6 ? ? ? Tdom Telm Tthres time
Figure 20: Step responses. Step responses for solution (a) (left) and solution (b)
(right). The gures in the top row are the step responses when switch 1 is closed, the second row shows step responses when switch 2 is closed, etc. Each plot gives the step responses at the six dierent nodes of the circuit. We also indicate the values of the dominant time constant, the critical Elmore delay, and the critical 50%-threshold delay.
Again the Elmore delay is slightly higher than dominant time constant and the dominant time constant is roughly equal to the 50%-threshold delay.
w21 w22 w23 w24 w25 w31 w32 w35 w34 w33 w11 w12 w13 w15 w14 s11 s12 s13 s14 s15 s21 s22 s23 s24 s25 s1 s2
Figure21: Wire sizing and spacing. Three parallel wires consisting of ve segments
each. The conductance and capacitance of thejth segment of wireiis proportional
towij. There is a capacitive coupling between theith segments of wires 1 and 2, and
between theith segments of wires 2 and 3, and the value of this parasitic capacitance
is inversely proportional tos1i, ands2i, respectively. The optimization variables are
the 15 segment widthswij and the distancess1 ands2.
5.5 Combined wire sizing and spacing
The examples so far involved grounded capacitor RC circuits. This section will illustrate an important advantage of dominant time constant minimization over techniques based on Elmore delay: the ability to take into account non-grounded capacitors.
The problem is to determine the optimal sizes of interconnect wires and the optimal distances between them. We will consider an example with three wires, each consisting of ve segments, as shown in Figure 21. The optimization variables are the widthswij, and the
distances s1 and s2 between the wires.
The RC model of the three wires is shown in Figure 22. The wires are connected to a voltage source with output conductance G at one end, and to capacitive loads at the other end. As in the previous examples, each segment is modeled as a -segment, with conductance and capacitance proportional to the segment width wij. The dierence with
the models used above is that we include a parasitic capacitance between the wires. We assume that there is a capacitance between the jth segments of wires 1 and 2, and between the jth segments of wires 2 and 3, with total values inversely proportional to the distances
s1j and s2j, respectively. To obtain a lumped model, we split this distributed capacitance
over two capacitors: the capacitance between segments j of wires 1 and 2 is lumped in two capacitors with value =s1j, placed between nodes j and j + 6, and between nodes j + 1
and j+ 7, resp; the total capacitance between segments j of wires 2 and 3 is lumped in two capacitors with value =s2j, placed between nodes j+6 and j+12, and between nodes j+7
U1 U2 U3 G G g11 g21 g25 g15 g35 g31 C1 C2 C3 c26 c32 c36 G c11 c21 c12 c22 c13 c23 g12 g22 g32 b c11 b c21 b c12 b c22 b c13 b c23 b c25 b c15 b c16 b c26 c16 c15 c25 c35 c31 c33 1
Figure 22: RC model of the three wires shown in Figure 21. The wires are
con-nected to voltage sources with output conductance G at one end, and to load
ca-pacitors Ci at the other end. The conductances gij and capacitances cij are part
of the -models of the wire segments. The capacitances b
cij model the capacitive
coupling. The conductances and capacitances depend on the geometry of Figure 21 in the following way: gij = wij, ci1 = wi1, cij = (wij +wi(j
?1)) (1 < j < 6), ci6=wi5,bci1==si1,bcij==sij+=si(j ?1) (1 <j<6), bci6==si5. 29
0 5 10 15 20 25 30 80 100 120 140 160 180 200 total widths1+s2 dominan ttime constan t (a) (b)
Figure 23: Tradeo curve. The two objectives are the dominant time constant
of the circuit and the total width s1+s2. subject to a lower bound of 1.0 on the
distancessij, and an upper bound of 2.0 on the segment widthswij.
and j+ 13, respectively. This leads to the RC circuit in Figure 22 with, for i= 1;2;3,
gij =wij; ci1 =wi1; cij =(wij+wi(j?1)) (1< j <6); ci6=wi5; and, for i= 1;2, b ci1 = si1; cbij= sij + si(j?1) (1< j <6); cbi6= si5:
In the calculations we will use the numerical values
G= 100; C1 = 10; C2 = 20; C3 = 30; = 1; = 0:5; = 2:
We also impose the constraints that the distances sij between the wires must exceed 1.0,
and that wire widths are less than 2.0.
Figure 10 shows the tradeo between the total width s1+s2 of the three wires, and the
dominant time constant of the circuit. Each point on the tradeo curve is the solution of an optimization problem mimimize s1+s2 subject to TmaxG(w11;:::;w35)?C(w11;:::;w35;s11;:::;s25)0 s1j =s1?w1j ?0:5w2j; j = 1;:::;5 s2j =s2?w3j ?0:5w2j; j = 1;:::;5 sij 1; i= 1;2; j = 1;:::;5; wij2; i= 1;2;3; j = 1;:::;5; (22) in the variables s1, s2, wij, sij. Note that the capacitance matrix contains terms that
are inversely proportional to the variables sij, and therefore problem (22) is not an SDP.
However, it can be reformulated as an SDP in the following way. First we introduce new variables tij = 1=sij, and write the problem as
mimimize s1+s2 subject to TmaxG(w11;:::;w35)?C(w11;:::;w35;t11;:::;t25)0 1=t1j s1?w1j?0:5w2j; j = 1;:::;5 1=t2j s2?w3j?0:5w2j; j = 1;:::;5 0tij 1; i= 1;2; j = 1;:::;5: (23) Note that we replace the equalities in the second and third constraints by inequalities. We rst argue that this can be done without loss of generality. Suppose (si;wij;tij) are feasible
in (23) with a certain objective value, and that one of the of the nonlinear inequalities intij,
e.g., the inequality
1=t1j s1?w1j ?0:5w2j
is not tight. Decreasing t1j increases the smallest eigenvalue of the matrix G ? TmaxC.
(This is readily shown from the Courant-Fischer minimax theorem. It is also quite intuitive: reducing coupling decreases the dominant time constant.) Therefore we can replace t1j by
t1j = 1=(s1?w1j?0:5w2j);
while still retaining feasibility in (23), and without changing the objective value. Without loss of generality we can therefore assume that at the optimum the second and third constraints in (23) are tight. Hence problem (23) is equivalent to (22).
Problem (23) is convex in the variables s1, s2,tij,wij: the rst constraint is an LMI; the
fourth constraint is a set of linear inequalities; the second and third constraints are nonlinear convex constraints that can be cast as 33-LMIs by the following equivalence:
x0; xy 1 () x0; " 2 x?y # x+y () x0; 2 6 4 x+y 0 2 0 x+y x?y 2 x?y x+y 3 7 5 0:
Figures 24 through 26 illustrate the solution marked (a) on the tradeo curve, i.e., a solution with large dominant time constant and small area. The thickest wire is number three, since it drives the largest load, the thinnest wire is number one, which drives the smallest load. Note that although the wires clearly taper o toward the end, there is a very slight increase in the width of wires 1 and 3 at segments 2 and 3. We also see that the smallest distance between the wires is equal to its minimum allowed value of 1.0, which means that the cross-coupling did not aect the optimal spacing between the wires. Figure 25 shows the output voltages for steps applied to one of the wires, while the two other input voltages remains zero. In Figure 26 we show the eect of applying a step simultaneously at two inputs, while the third input voltage remains zero.
Figures 27 through 29 illustrate the solution (b), i.e., a circuit with small dominant time constant and large area.. Note that here the distance between the second and third wires is
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 1 2 3 4 5 6
Figure 24: Solution marked (a) on the tradeo curve. Note that the distance
between the wires is equal to its minimal allowed value of 1.0
0 50 100 150 200 250 0 0.2 0.4 0.6 0.8 1 v6(t) v12(t) ? ? v18(t) time voltage 0 50 100 150 200 250 0 0.2 0.4 0.6 0.8 1 v6(t) v12(t) ? ? v18(t) time 0 50 100 150 200 250 0 0.2 0.4 0.6 0.8 1 ? ? v6(t) v12(t) v18(t) time voltage
Figure 25: Responses for solution (a). The voltages at the output nodes due to a
step applied to the rst wire (left gure), second wire (center), or third wire (right). The dashed line marks the dominant time constant.
0 50 100 150 200 250 0 0.2 0.4 0.6 0.8 1 ? ? v6(t) @ @ I v12(t) ? ? v18(t) time voltage 0 50 100 150 200 250 0 0.2 0.4 0.6 0.8 1 ? ? v6(t) ? ? v12(t) @ @ I v18(t) time 0 50 100 150 200 250 0 0.2 0.4 0.6 0.8 1 ? ? v6(t) ? ? v12(t) @ @ I v18(t) time
Figure 26: Responses for solution (a). Voltages at output nodes when a step is
applied simultaneously at wires 1 and 2 (left gure), wires 1 and 3 (center), and wires 2 and 3 (right). The dashed line marks the dominant time constant.
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 2 4 6 8 10 12 14
Figure 27: Solution marked (b) on the tradeo curve.
0 20 40 60 80 100 120 140 160 0 0.2 0.4 0.6 0.8 1 v6(t) v12(t) ? ? v18(t) time voltage 0 20 40 60 80 100 120 140 160 0 0.2 0.4 0.6 0.8 1 v6(t) v12(t) ? ? v18(t) time 0 20 40 60 80 100 120 140 160 0 0.2 0.4 0.6 0.8 1 ? ? v6(t) v12(t) v18(t) time voltage
Figure 28: Responses for solution (b). The voltages at the output nodes, due to
to a step applied to the rst wire (left gure), second wire (center), or third wire (right). The dashed line marks the dominant time constant.
0 20 40 60 80 100 120 140 160 0 0.2 0.4 0.6 0.8 1 ? ? v6(t) @ @ I v12(t) ? ? v18(t) time voltage 0 20 40 60 80 100 120 140 160 0 0.2 0.4 0.6 0.8 1 ? ? v6(t) ? ? v12(t) @ @ I v18(t) time 0 20 40 60 80 100 120 140 160 0 0.2 0.4 0.6 0.8 1 ? ? v6(t) ? ? v12(t) @ @ I v18(t) time
Figure 29: Responses for solution (b). Voltages at output nodes when a step is
applied simultaneously at wires 1 and 2 (left gure), wires 1 and 3 (center), and wires 2 and 3 (right). The dashed line marks the dominant time constant.
larger than the minimum allowed value of 1.0. The other gures show the output voltages for the same situations as above.
Note that we can not guarantee that the peak due to crosstalk stays under a certain level. This would be a specication in practice, but it is dicult to incorporate into the optimization problem. However we inuence the level indirectly: minimizing the dominant time constant makes the cross-talk peak shorter in time (since the dominant time constant determines how fast all voltages settle around their steady-state value). Indirectly, this also tends to make the magnitude of the peak smaller (as can be seen by comparing the crosstalk levels for the two solutions in the examples).
A practical heuristic based on the dominant time constant minimization that would guarantee a given peak level is as follows. We rst solve a problem as above, i.e., minimize area subject to a constraint on the dominant time constant. Then we simulate to see if crosstalk level is acceptable. If not, we increase the spacing of the wires until it is. Then we determine the optimal wire sizes again, keeping the wires at least at this minimum distance. This iteration is continued until it converges. The dominant time constant of the nal result will be at least as good as the rst solution and the cross talk level will not exceed the maximum level.
6 Some relations between the delay measures
In this section we derive several bounds between the three delay measures. The results allow us to translate upper bounds on Tdom into upper bounds on Elmore delay and threshold
delays. Some of the bounds will turn out to be quite conservative. As the examples of previous section show, the 50% threshold delay, the Elmore delay, and the dominant time constant are much closer in practice than the bounds derived here would suggest.
Bounds on node voltages
We start by rewriting (7) as v(t) =e?C ?1Gt v(0) =C?1=2e?C ?1=2GC?1=2t C1=2v(0);
and use the second form to derive an upper bound on kv(t)k 1: kv(t)k 1 = C 1=2e?C ?1=2GC?1=2t C?1=2v(0) 1 C 1=2 1 e ?C ?1=2GC?1=2t 1 C ?1=2 1 kv(0)k 1 p n1(C 1=2) e ?C ?1=2GC?1=2t kv(0)k 1 = p n1(C 1=2) kv(0)k 1e ?t=Tdom; (24)
where the condition number 1 is dened as 1(A) = kAk 1 kA ?1 k 1, and kAk denotes the
spectral norm of A, i.e., its largest singular value. The rst inequality follows from the submultiplicative property of the matrix norm (kABk
1) and the denition of
the innity-induced matrix norm (kAxk 1
1). The second inequality follows from
the relation between the innity-induced and the spectral norm of a matrix (kAk 1 p nkAk for A 2
mn). In the last line we used the fact the largest eigenvalue of the symmetric
ise?t=Tdom, and that the largest eigenvalue and the spectral norm of a
positive denite symmetric matrix coincide.
Note that for diagonalC =
diag(C1;:::;Cn) we have1(C
1=2) = (maxiCi)1=2=(minjCj)1=2.
For grounded capacitor RC circuits with v(0) >0 we can also derive a lower bound on
1. Recall that for a grounded capacitor RC circuit the matrix e ?C
is elementwise nonnegative. We therefore have
maxk vk(t) = maxk eTke?C ?1Gt v(0) vmin(0)max k eTke?C ?1Gt e vmin(0)e ?t=Tdom; (25)
where vmin(0) is the smallest component of v(0). The last inequality follows from the
Ger-shgorin disk theorem [GL89, p. 341], which, together with the elementwise nonnegativity, implies that the eigenvalues of the matrix e?C
are bounded above by largest row sum maxkeTke?C
e. In a grounded-capacitor RC tree we can assume v(0) =e and therefore maxk vk(t)e
Threshold delay and dominant time constant
From (24) we see that for t Tdomlog p n1(C 1=2)kv(0)k1 , we have kv(t)k 1 , so we conclude Tthres T domlog p n1(C 1=2)kv(0)k 1 ! :
In a similar way, we can derive from (25) the lower bound
(27) on the critical threshold delay of a grounded capacitor RC circuit. If v(0) =e, one obtains
Dominant time constant and Elmore delay
From (24) we have for each k
Tkelm =Z 1 0 vk(t)dt p n1(C 1=2) kv(0)k 1 Z 1 0 e ?t=Tdom dt = Tdomp n1(C 1=2) kv(0)k 1: (28)
Thus we have a bound between critical Elmore delay and dominant time constant. For grounded capacitor circuits we obtain the lower bound from (26):
and for a grounded capacitor RC tree
Tthres Telm Tdom Tthres T elm= T domlog(p n=) Telm Tthres p n=log(1=) Tdom p n
Tdom Tthres=log(1=) Telm
Table 1: Bounds for grounded capacitor RC trees. stands forC
Threshold delay and Elmore delay
We have already seen that TthresTelm= when the voltage decays monotonically.
For a grounded capacitor circuit we can also put together bounds (28) and (27), which yields Telm T thresp n1(C 1=2) kv(0)k 1 log(vmin(0)=);
and, for a grounded capacitor RC tree,
Telm T thresp n1(C 1=2) 1 log(1=):
Table 1 summarizes the bounds for grounded-capacitor RC trees, for which we have a com-plete set of upper and lower bounds. As an illustration, we evaluate the upper and lower bounds for the RC tree of the example in x5.1. We obtain
Tdom T elm 4:58 1(C 1=2)Tdom:
The lower bound turns out to be quite close (Telm
dom+ 67 over the entire range of
computed values of Tdom). The upper bound however turns out to be very conservative (it
ranges from 7842 forTdom= 370 to 8289 forTdom = 2000). The other examples conrm this
observation that the bounds of this section are sometimes quite conservative in practice.