ABSTRACT
VAN BRUNT, EDWARD R. Development of Optimal 4H-SiC Bipolar Power Diodes for High-Voltage High-Frequency Applications. (Under the direction of Alex Q. Huang and B. Jayant Baliga.)
Development of Optimal 4H-SiC Bipolar Power Diodes for High-Voltage High-Frequency Applications
by
Edward R. Van Brunt
A dissertation submitted to the Graduate Faculty of North Carolina State University
in partial fulfillment of the requirements for the Degree of
Doctor of Philosophy
Electrical Engineering
Raleigh, North Carolina
2013
APPROVED BY:
Subhashish Bhattacharya Anant Agarwal
Alex Q. Huang
Co-chair of Advisory Committee
B. Jayant Baliga
DEDICATION
ACKNOWLEDGEMENTS
First and foremost, I would like to thank my advisors and committee members in guiding me to a level of physical understanding that has shaped my view of the universe of power devices, and semiconductors in general.
My special thanks goes to the technical staff of the three cleanrooms in which my devices were fabricated. At NCSU, I thank Marcio Cerullo, Nicole Hedges, and Henry Taylor, for keeping the equipment running and assisting me with process development. Especially, I’d like to thank David Vellenga for answering the phone on a Sunday morning while watching a football game to help me get the stepper working, and the 1001 other times that he answered my bizarre photo questions in stride. At Cree, Inc., my thanks go out to Charlotte Jonas, Craig Capell, and Kheim Lam for doing my second run, as well as for their advice and support.
TABLE OF CONTENTS
List of Tables . . . vii
List of Figures . . . .viii
Chapter 1 Introduction . . . 1
Chapter 2 A Review of 4H-SiC Diodes . . . 4
2.1 Unipolar Power Diodes . . . 5
2.1.1 Breakdown Voltage . . . 5
2.1.2 Leakage . . . 6
2.1.3 Conduction characteristics . . . 8
2.1.4 Switching characteristics . . . 11
2.2 PiN Bipolar Power Diodes . . . 11
2.2.1 Ideal On-State Carrier Distribution . . . 11
2.2.2 Non-ideal On-State Carrier Distribution . . . 13
2.2.3 Switching characteristics . . . 15
2.2.4 Maximumdi/dtduring diode turnoff . . . 18
2.3 Low Injection Efficiency Bipolar Diodes . . . 24
2.3.1 On-state carrier concentration: MPS diode . . . 25
2.3.2 On-state carrier concentration: SSD . . . 25
2.3.3 On state forward voltage drop . . . 25
2.3.4 Stored Charge . . . 30
2.3.5 Maximumdi/dtfor low-injection efficiency diodes . . . 30
2.4 Conclusions . . . 31
Chapter 3 4H-SiC MPS Diodes . . . 34
3.1 Design of the Schottky Barrier . . . 34
3.2 Design of 4H-SiC MPS diodes for SST applications . . . 40
3.2.1 MPS diodes with a thick (150µm) drift region . . . 40
3.2.2 MPS diodes with a thin (100µm) drift region . . . 44
3.2.3 SiC diode frequency capability: current density analysis . . . 45
3.3 Conclusions . . . 47
Chapter 4 Fabrication and Characterization of 4H-SiC Power Diodes. . . 50
4.1 Fabrication Procedure for 4H-SiC 15kV Diodes . . . 50
4.1.1 Zero Patterning . . . 50
4.1.2 Ion Implantation . . . 52
4.1.3 Lithography . . . 55
4.1.4 Contacts . . . 61
4.2 Characterization of 4H-SiC 15kV Diodes . . . 62
4.2.1 Contact Resistance . . . 62
4.2.3 CV doping profiling . . . 65
4.2.4 Lifetime . . . 65
4.2.5 Forward I-V . . . 68
4.2.6 Reverse I-V . . . 73
4.2.7 Reverse Recovery . . . 77
4.3 Analysis . . . 81
4.4 Conclusions . . . 85
Chapter 5 Second MPS Diode Fabrication . . . 87
5.1 Device Design & Mask Layout . . . 88
5.1.1 Active region design and mask sequence . . . 88
5.1.2 Edge Termination Design . . . 90
5.2 Process Flow and Development . . . 92
5.2.1 Starting material . . . 92
5.2.2 Passivation . . . 93
5.2.3 Process Flow . . . 93
5.3 Characterization Results . . . 95
5.3.1 CV Doping Concentration . . . 96
5.3.2 Schottky Barrier . . . 96
5.3.3 Ohmic Contacts . . . 96
5.3.4 Forward IV . . . 99
5.3.5 Reverse IV . . . 102
5.3.6 OCVD Lifetime . . . 117
5.3.7 Forward Recovery . . . 117
5.3.8 Reverse Recovery . . . 121
5.4 Discussion . . . 127
5.4.1 Static forward characteristics . . . 127
5.4.2 Reverse characteristics . . . 128
5.4.3 Reverse Recovery . . . 129
5.4.4 Performance tradeoff . . . 134
5.5 Conclusions . . . 139
Chapter 6 4H-SiC SPEED Diode . . . .140
6.1 Concept and Physical Design . . . 141
6.1.1 Drift Region Design . . . 142
6.1.2 Anode Design . . . 142
6.2 SPEED Diode Process . . . 143
6.2.1 Deep RIE of SiC to form anode pattern . . . 143
6.2.2 Mask sequence and bevel edge termination formation . . . 149
6.3 Conclusion . . . 153
Chapter 7 Conclusions. . . .154
7.1 Major Contributions . . . 154
LIST OF TABLES
Table 3.1 Device device parameters . . . 34
Table 3.2 Metal work functions and barrier heights . . . 35
Table 4.1 Fabrication Procedure . . . 51
Table 4.2 Zero Pattern Etch Parameters . . . 52
Table 4.3 Anode Implantation Series . . . 53
Table 4.4 JTE Implantation Series . . . 54
Table 4.5 AZ LOF-5510 Spin Speed vs. Thickness . . . 58
Table 4.6 Room temperature reverse recovery . . . 81
Table 4.7 125°C reverse recovery . . . 81
Table 4.8 Measured device parameters . . . 82
Table 5.1 Mask levels for second MPS design iteration . . . 90
Table 5.2 Process flow for second MPS design iteration . . . 94
Table 5.3 Summary of median on-state voltage for devices in second MPS fabrication run at 30 A/cm2 . . . 102
Table 5.4 K-S normality test results for leakage current . . . 114
Table 5.5 K-W test comparing PiN, Lin. MPS, and Hex. MPS . . . 114
Table 5.6 K-S tests on wafer KA-0368-25 between device types . . . 114
Table 5.7 Reverse recovery test results @ 25°C . . . 124
Table 5.8 Reverse recovery test results @ 125°C for wafer HD-0487-03 . . . 127
LIST OF FIGURES
Figure 1.1 Block diagram of a Solid State Transformer . . . 1
Figure 2.1 Schematic diagram of different types of power diodes implementations . . 5 Figure 2.2 Allowable WD and ND values for a parallel plane breakdown voltage of
18.75 kV . . . 7 Figure 2.3 Contour plots of maximum electric field (from Eq. 2.6) and associated
barrier lowering . . . 9 Figure 2.4 Contour plots of maximum electric field (from TCAD simulation) and
associated barrier lowering . . . 10 Figure 2.5 Plot of Eq. 2.18, τHL= 1.5µs, JT = 30 A/cm2,T = 400 K . . . 13 Figure 2.6 Plot of carrier density for a PiN diode with WA=1µm, NA=1e18 cm-3,
JT=30 A/cm2. Plots assuming unity injection efficiency, non-unity injec-tion efficiency, and a simulated result are included . . . 16 Figure 2.7 Analytically modeled reverse recovery process for 4H-SiC PiN diode (a)
and simulation (b) . . . 17 Figure 2.8 Illustration of dynamic avalanche process in a power diode . . . 19 Figure 2.9 Plot of di/dtmax vs. JF for 15 kV silicon and 4H-SiC power diodes . . . . 21 Figure 2.10 Contour plots ofdi/dtmax vs. JF and VR for silicon and SiC . . . 22 Figure 2.11 Drift region length design rule used when computing maximum di/dt
capability of 4H-SiC and silicon power diodes . . . 23 Figure 2.12 Drift region doping design rule used when computing maximum di/dt
capability of 4H-SiC and silicon power diodes . . . 23 Figure 2.13 Drift region lifetime design rule used when computing maximum di/dt
capability of 4H-SiC and silicon power diodes . . . 24 Figure 2.14 Plot of Eq. 2.21,τHL= 1.5µs, JT = 30 A/cm2,T = 400 K for various
P-emitter dopings as indicated on plot . . . 26 Figure 2.15 Voltage drop across the middle region of 15 kV MPS and SSD rectifiers . 28 Figure 2.16 Total voltage drop for 15 kV MPS and SSD rectifiers . . . 29 Figure 2.17 Stored Charge vs. Forward Drop atJt=30 A/cm2for various 15 kV rectifiers 30 Figure 2.18 Plot ofdi/dtmax vs. JF for 15 kV silicon and 4H-SiC MPS power diodes . 31 Figure 2.19 Contour plots ofdi/dtmax vs. JF and VR for silicon and SiC MPS diodes 32
Figure 3.1 J-V relationship for 15 kV 4H-SiC MPS diodes with various Schottky barrier heights . . . 36 Figure 3.2 Zero-bias solution for MPS anode conduction band energy with WO = 1
µm and WS = 0.35 µm . . . 37 Figure 3.3 Cut-line at point furthest from P+N junction in Figure 3.2 . . . 38 Figure 3.4 Conduction band energy for 1.45 eV, 1.00 eV, and 0.55 eV Schottky
bar-rier height . . . 39 Figure 3.5 Reverse J-V characteristic for MPS diodes with 1.45 eV, 1.00 eV, and
Figure 3.6 J-V relationship for designed 15 kV 4H-SiC diodes with different anode
designs . . . 40
Figure 3.7 On-state excess hole profiles for designed 15 kV 4H-SiC diodes with dif-ferent anode designs at 30 A/cm2 . . . 41
Figure 3.8 Remote ohmic contact structure . . . 42
Figure 3.9 Switching waveforms from two-device mixed mode simulations with RG = 30 for the active switch . . . 43
Figure 3.10 VF vs. ERR tradeoff for designed 15kV 4H-SiC diodes . . . 43
Figure 3.11 Frequency capability of 15kV 4H-SiC diodes in SST ABR with P=300W/cm2 44 Figure 3.12 Frequency capability of 15kV 4H-SiC diodes in SST DAB with P=300W/cm2 45 Figure 3.13 Frequency capability of 4H-SiC diodes with WD=100 µm in SST ABR with P=300W/cm2 . . . 46
Figure 3.14 Frequency capability of 4H-SiC FET with WD=100µm in SST ABR with P=300W/cm2 for various diode types . . . 46
Figure 3.15 Total required device area vs. frequency for 15kV SiC devices with WD=100µm in SST ABR with P=300W/cm2 for various diode types . . 47
Figure 3.16 Maximum diode current density vs. frequency for 15kV SiC devices in SST ABR with P=300W/cm2 for various diode types . . . 48
Figure 3.17 Maximum MOSFET current density vs. frequency for 15kV SiC devices in SST ABR with P=300W/cm2 for various diode types . . . 48
Figure 4.1 Comparison between different implant simulation techniques and mea-sured data . . . 54
Figure 4.2 SIMS profile of implanted anode concentration (thin purple line) and simulated implant (thick line) . . . 55
Figure 4.3 Wafer map . . . 56
Figure 4.4 Secondary Electron Image of 0.5 µm Au evaporated on top of 1.5 µm thick diluted NFR-16 film. 1 µm features are completely merged. . . 57
Figure 4.5 AZ-nLOF-5510 with different exposure times . . . 58
Figure 4.6 AZ-nLOF-5510 with Au film showing ideal breaks in pattern for liftoff . . 59
Figure 4.7 AZ-nLOF-5510 3/4ths view Secondary Electron Images of Au film on same device with both good and bad pattern . . . 60
Figure 4.8 Darkfield microscope images showing examples of both good patterning for liftoff and uneven pattern that will yield poor results . . . 60
Figure 4.9 Picture of wafer prior with final anode mask applied . . . 61
Figure 4.10 Example of obtained I-V characteristics for a TLM pattern (a), and ob-tained RT vs. d relationship from I-V characteristics (b) . . . 64
Figure 4.11 Example I-V relationship used for Schottky barrier extraction, whereIs is given by the intersection of the fit line with the y axis . . . 65
Figure 4.12 ND vs. WD extracted from CV measurement . . . 66
Figure 4.13 Circuit used for OCVD test . . . 68
Figure 4.14 Detail of captured OCVD voltage waveform . . . 68
Figure 4.15 Room Temperature J-V relationship for small devices. Legend: Schottky contact half-cell pitch . . . 69
Figure 4.17 Room Temperature J-V relationship for large devices. Legend: Schottky
contact half-cell pitch . . . 71
Figure 4.18 High Temperature J-V relationship for large devices, taken at 125°C . . . 72
Figure 4.19 Circuit used for measuring reverse I-V characteristics . . . 74
Figure 4.20 Highest BV device’s Reverse J-V characteristic from 15 kV wafer before removal of metal . . . 75
Figure 4.21 Highest BV device’s Reverse J-V characteristic from 15 kV wafer after removal of metal . . . 76
Figure 4.22 Double pulse test circuit schematic . . . 78
Figure 4.23 Detail of implementation of reverse recovery test device and in-progress reverse recovery test . . . 79
Figure 4.24 Reverse recovery parasitic capacitance extraction waveforms . . . 80
Figure 4.25 125°C reverse recovery waveform with on-state current density of 22 A/cm2 82 Figure 4.26 Measured results compared to 2D-simulated results with parameters from Table 4.8. Dotted lines are simulated results . . . 83
Figure 4.27 Simulated reverse recovery compared to measured reverse recovery for MPS diode for different Schottky contact half-cell pitchs . . . 84
Figure 4.28 3-D model of MPS diode including remote ohmic contact with 2-D cut lines (a), and carrier concentration taken at 30 A/cm2 at cut linesα and β 84 Figure 4.29 Measured results compared to 3D-simulated results with parameters from Table 4.8. Dotted lines are simulated results . . . 85
Figure 5.1 Mask layout for second ion-implanted MPS design iteration . . . 88
Figure 5.2 Anode pattern detail for second ion-implanted MPS design iteration. Light areas in these images were implanted with aluminum . . . 89
Figure 5.3 Breakdown voltage vs. incremental spacing Si for various values ofS1 . . 91
Figure 5.4 µPCD histogram for wafer HD0487-03, used for second MPS fabrication run . . . 93
Figure 5.5 Finished wafer with die numbering scheme overlaid . . . 95
Figure 5.6 Doping concentrations for wafers in second ion implanted MPS process . . 97
Figure 5.7 Log-scale JV characteristic for 600 µm diameter Schottky test structures on finished wafers . . . 98
Figure 5.8 Statistics for JV schottky barrier measurements on finished wafers. 8 measurements were made for each wafer . . . 98
Figure 5.9 Forward IV characteristic for wafers in second ion implanted MPS process at 25 °C . . . 100
Figure 5.10 Forward IV characteristic for wafers in second ion implanted MPS process at 125°C . . . 101
Figure 5.11 Forward IV statistics for wafers in second ion implanted MPS process at 25 °C. 60 devices were measured for each device type . . . 103
Figure 5.12 Forward IV statistics for wafers in second ion implanted MPS process at 125°C. 8 devices were measured for each device type . . . 104
Figure 5.13 VON @ 30 A/cm2 vs. temperature for different device types . . . 105
Figure 5.14 BV map for wafer HD-0487-03 at 25°C . . . 106
Figure 5.16 BV histogram for wafer HD-0487-03 at 25°C . . . 108
Figure 5.17 BV histogram for wafer KA-0368-25 at 25°C . . . 109
Figure 5.18 Reverse leakage for wafer HD-0487-03 at 25°C . . . 110
Figure 5.19 Reverse leakage for wafer KA-0368-25 at 25°C . . . 111
Figure 5.20 Highest breakdown obtained on wafer HD-0487-03 (hexagonal MPS device type) . . . 112
Figure 5.21 Reverse leakage statistics for wafers in second ion implanted MPS process at 25°C with mean 95% confidence diamonds computed from Z distribution113 Figure 5.22 Reverse leakage for wafer HD-0487-03 at 125°C . . . 115
Figure 5.23 Reverse leakage for wafer KA-0368-25 at 125°C . . . 116
Figure 5.24 OCVD waveforms for 2nd MPS process . . . 118
Figure 5.25 Forward recovery for packaged devices from wafer HD-0487-03 at 25°C . 119 Figure 5.26 Forward recovery for packaged devices from wafer KA-0368-25 at 25°C . 120 Figure 5.27 Reverse recovery for packaged devices from wafer HD-0487-03 at 25°C . . 122
Figure 5.28 Reverse recovery for packaged devices from wafer KA-0368-25 at 25°C . . 123
Figure 5.29 Reverse recovery for packaged PiN diode from wafer HD-0487-03 at 25°C and 125 °C . . . 125
Figure 5.30 Reverse recovery for packaged linear MPS diode from wafer HD-0487-03 at 25 °C and 125°C . . . 125
Figure 5.31 Reverse recovery for packaged hexagonal MPS diode from wafer HD-0487-03 at 25 °C and 125°C . . . 126
Figure 5.32 Reverse recovery waveform of MPS diode from wafer KA-0368-25 at 125 °C showing snappy behavior . . . 126
Figure 5.33 Measured PiN JV from wafer KA-0368-25 vs. simulated JV with and without degraded lifetime near junction . . . 129
Figure 5.34 Illustration of reverse recovery process for 4H-SiC diodes: Storage phase . 132 Figure 5.35 Illustration of reverse recovery process for 4H-SiC diodes: Charge removal phase . . . 132
Figure 5.36 Illustration of reverse recovery process for 4H-SiC diodes: Voltage ap-proaches Vbus . . . 133
Figure 5.37 Illustration of reverse recovery process for 4H-SiC diodes: Voltage reaches Vbus . . . 133
Figure 5.38 MPS reverse recovery simulation current/voltage waveform and carrier profile . . . 135
Figure 5.39 PiN reverse recovery simulation current/voltage waveform and carrier profile136 Figure 5.40 Plots of carrier concentration vs. time and distance from anode junction during reverse recovery process . . . 137
Figure 5.41 QRR - VON @ 30 A/cm2 tradeoff (25°C) . . . 138
Figure 5.42 QRR - VON @ 30 A/cm2 tradeoff (125 °C) . . . 138
Figure 6.1 Unit cell for Si and SiC SPEED diodes . . . 141
Figure 6.2 Forward J-V curve and carrier profile at 30 A/cm2 for high γ PiN diode and low γ PiN diode with epitaxial emitters . . . 144
Figure 6.4 Micromasking of SiC during CF4 ICP etch with Ni hardmask . . . 146
Figure 6.5 RIE of SiC using S1813 positive photoresist . . . 147
Figure 6.6 RIE of SiC using NFR-16-D2 negative photoresist . . . 148
Figure 6.7 RIE of SiC using KMPR-1010 negative photoresist . . . 150
Figure 6.8 Silicon chip cut with 45° bevel . . . 151
Figure 6.9 Mask layout for 15 kV SPEED diodes . . . 152
Chapter 1
Introduction
Growing industrial and research investment in ”smart grid” technologies has fueled an interest in the development of switched-mode power electronics based transformers operating as a converter between distribution level voltages (7.2 kV AC) and consumer level voltages (120 V AC). These so-called Solid-State Transformers (SST) use one or more semiconductor switches to accomplish the control and regulation of voltage and current. The semiconductor switches used in a SST have a number of requirements that are unique to the application: Specifically, for connecting a consumer load to the grid, the required current levels are relatively low (on the order of 2 A RMS), and voltage levels are quite high (10.2 kV or higher, depending on the converter topology). In addition, the semiconductor switches should operate at high frequency to maximize the overall power density of the SST, and have low loss, as the efficiency of the 60 Hz magnetic transformers that the SST will replace can be as high as 98%. A diagram of a proposed SST incorporating active bridge rectifier and dual-half bridge type converters is shown in Figure 1.1.
Figure 1.1: Block diagram of a Solid State Transformer
of an externally applied signal, and diodes, which cannot be controlled, but disallow the flow of current in one direction. Both types of switches can be used in the construction of a switched mode power supply. This work focuses on the development of optimal power diodes for use in SST applications.
In Chapter 2 of this report, the fundamental physics of different types of power diodes are analyzed using a first-principles approach. Both unipolar and different types of power diodes are analyzed; it is found that in the regime of high voltage devices appropriate for use in a SST, bipolar diodes with a low anode injection efficiency can provide an advantageous trade-off between stored charge and on-state voltage.
Chapter 3 focuses on the design issues of 4H-SiC MPS diodes, and discusses a method based on using a submicron anode pattern spacing to achieve sufficient barrier heights to allow MPS diodes to be fabricated using a planar process. Using the developed anode pattern, 2D numerical simulations are used to design 4H-SiC MPS diodes with optimal parameters for use in a SST.
Chapter 4 discusses the fabrication procedure used to implement the MPS diodes designed in Chapter 3. The challenges that were encountered during the fabrication process as well as the methods used to solve them are detailed. Measurement results and techniques are presented in the second half of this chapter: it was found that in the high temperature operation regime, some control over the anode injection efficiency by variation in the anode pattern was achieved. 3D simulations with parameters matching the measured device characteristics are discussed to explain the observed device behavior.
Chapter 5 describes a second design iteration and fabrication run of 4H-SiC MPS diodes, as well as detailing extensive characterization work that went into determining the devices’s behavior. Sufficient breakdown voltage yield was obtained to allow for packaging of several devices for full power tests: the obtained devices showed good forward and reverse recovery characteristics, and validated the MPS diode design strategy by showing a superior performance trade-off when compared to PiN diodes fabricated in the same run. Some literature review and 2D numerical simulation was performed and described to relate obtained device characteristics to physical concepts.
Chapter 6 details an alternative reduced-anode-injection-efficiency diode design, based en-tirely on epitaxially grown emitter structures. The 4H-SiC SPEED diode is shown through simulation to have significantly less stored charge than an equivalent PiN diode, but with only marginally higher forward voltage drop. Due to the nature of the anode design, the lithographic requirements of the SPEED diode are vastly reduced compared to the MPS diode, allowing for the use of contact lithography. In addition, the SPEED diode is expected to give better on-state performance than the ion-implanted MPS diode due to better emitter characteristics.
Chapter 2
A Review of 4H-SiC Diodes
This chapter presents a review and brief analysis of important physical concepts for the design of power rectifiers. As the physical concepts of rectifier design are developed in this chapter, several important parameters such as drift region thickness and doping concentration are designed for a 15 kV diode.
Broadly, power diodes can be subcategorized into two different types, based on the funda-mental physics that govern their operation:
Unipolarpower diodes, the simplest example of which is the Schottky Rectifier, are char-acterized by a majority carrier current conduction mechanism, and capacitive switching characteristics.
Bipolardiodes are characterized by a high injection efficiency anode that injects minority carriers into the device’s high resistance drift region, reducing the on-state forward voltage drop of the device (an effect termed conductivity modulation). The switching character-istics of these devices are governed by the removal of the injected charge. Bipolar device physics are quite complex, and, in 4H-SiC, must take into account a number of 2nd-order physical processes considered to be unimportant in equivalent Si structures. These effects can reduce the injected charge, which may be a desired condition.
Figure 2.1: Schematic diagram of different types of power diodes implementations
2.1
Unipolar Power Diodes
Any passive device that prevents current flow in the second quadrant and allows it in the first without the injection of minority carriers falls under the Unipolar power diode designation, and includes Schottky diodes, JBS diodes, as well as Superjunction or other charge-coupled struc-tures. The physics of this structure are analyzed below; the information relating to breakdown voltage is relevant to both bipolar and unipolar type devices.
2.1.1 Breakdown Voltage
The breakdown voltage of a power device is typically defined by the avalanche breakdown cri-terion: the acceleration of thermal carriers under the high fields present in a reversed-biased junction results in the production of more carriers; a condition known as avalanche multiplica-tion. When there are infinite carriers produced for a single carrier that enters the multiplication process, the leakage current becomes infinite, and the device ceases to serve as a rectifier.
It is convenient to define the initiation point of avalanche breakdown by a critical electric field. For silicon carbide, this critical field is typically given by Eq. 2.1 [1].
EC =
2.49e6
1−0.25 logND
1016
(2.1)
There are three approaches to making a vertical unipolar power diode drift region
devices have a triangular electric field distribution, and have the highest on-state voltage.
2. Punch-through devices have a drift region that is shorter than that of a symmetric device. In the breakdown condition, the electric field is nonzero at the cathode, causing the field profile to have a trapezoidal shape. These devices have a lower on-state voltage drop than symmetric devices.
3. Charge-coupled devices utilize either a deep p-doped column (“Superjunction”) or trenched anode (such as the TMBS structure) to cause the region near the cathode to support more voltage than would be possible without the charge-coupled structure. Properly im-plemented, the electric field takes on a rectangular profile, and the device breakdown voltage becomes independent of the doping concentration. While this approach has been employed to great success in silicon for power MOSFETs [2] and diodes [3], it has received little attention in SiC, likely due to the limited diffusivity of acceptor species.
Of these methods, due to the impracticability of the Superjunction approach, and the high
RON of the symmetric approach, the punch-through design was adopted to design a 15 kV BV capable drift region. The criterion for breakdown of a punch-through structure is given by [4]
BV =ECWD −
qNDWD2
2s
(2.2)
whereEC is from Eq. 2.1,ND is the doping concentration, andWD is the drift region width. For a given value of BV, this equation produces a curve that describes allowable combinations of doping concentration and drift region width. The resulting combination of Eq. 2.2 and Eq. 2.1 is plotted below in Figure 2.2 for a BV value of 18.75 kV, which was selected based on an application target of 15 kV and assuming an edge termination that can effectively support 80% of the parallel-plane breakdown voltage.
As can be seen from the curve, the required WD increases rapidly beyond about ND = 4.5e14 cm-3 concentration. Because it is more difficult to reliably fabricate a epilayer with low doping concentration, the parametersND = 4.5e14 cm-3and WD = 150µm were selected.
2.1.2 Leakage
1´1014 2´1014 3´1014 4´1014 5´1014 120
140 160 180 200
N
DH
cm
-3L
Drift
Region
Width
H
Μ
m
L
Figure 2.2: Allowable WD and ND values for a parallel plane breakdown voltage of 18.75 kV
that tunnel through the Schottky barrier, and electrons with a potential energy equal to that of the metal’s Fermi potential that tunnel directly from the metal through the Schottky barrier.
With increasing reverse bias, the electric field at the Schottky contact increases, causing a corresponding drop in the barrier height due to image force barrier lowering. The origin effect is explained in detail in [5]. The decrease in the barrier is given by
∆φBN =
r
qEM
4πs
(2.3)
where EM is given by
EM =
r
2qND
s
(VR+Vbi) (2.4)
In addition, with increasing reverse bias, the barrier becomes spatially thinner closer to the Schottky contact, resulting in an increase in field emission. This is modeled by the inclusion of a “tunneling coefficient,” which has a value of CT = 8e-13 cm2 V-2 [6]. Finally, the leakage current for a 4H-SiC diode can be expressed as
JS=AT2exp
−qφBN
kT
q∆φBN
kT
CTEM2
In a SiC power rectifier, the material’s high critical electric field can lead to high reverse leakage currents (due to the greater value of EM at breakdown) when compared to silicon. To counteract this effect, the JBS and TMBS rectifier structures have been successfully employed to reduce the field strength at the Schottky contact and therefore reduce the leakage current [7] [3]. Such structures rely on the use of a higher-barrier P-N junction (in the JBS structure) or Schottky junction (in the TSBS structure) to shield the main junction from the high fields present under reverse-biased conditions [8]. Because some contact area is lost due to the in-clusion of this shielding junction, for low-voltage devices with thin drift regions, the spreading resistance caused by this lost contact area can have an effect on the device on-state voltage. However, for 15 kV class SiC devices, simulations conducted for the drift region described in this chapter have shown that this spreading resistance is insignificant compared to the resistance of the drift region and can effectively be ignored.
Semi-analytical models exist that model the reduction of the maximum field at the Schottky contact [6] [9], but these models rely on empirical parameters to model the 2-D effects of the P-N junctions. Reference [9] gives an empirical form for the electric field at the Schottky contact as a function of voltage (VR), the junction depthXJ, and the Schottky contact half-cell pitch
W
EM =
αW
β(µm)
XJ(µm)
VR1/2 (2.6)
where the empirical parameters α and β have values α = 7e3 and β = 0.7. The resulting barrier lowering given the maximum field model in Eq. 2.6 is shown in Figure 2.3 given a junction depth of 1.3 µm. These results can be compared to the maximum electric field and barrier lowering for a JBS/MPS structure constructed on a 150 µm thick, 4.5e14 cm-3 doped drift region computed using Synopsys TCAD, shown in Figure 2.4. The difference between the computed barrier lowering from the formula and the simulation is at most 0.02 eV, indicating that Eq. 2.6 is a good approximation of the maximum field in a high-voltage JBS/MPS structure.
2.1.3 Conduction characteristics
200
400
600
800
1000 1200
1400
0.5 0.75 1.0 1.5 2.0 2.5 3.0 3.5 4.0
2 4 6 8 10 12
Schottky Half
-
Cell Pitch
H
Μ
m
L
Reverse
Voltage
H
kV
L
¬EmaxHkVcmL
(a): Emax
0.06 0.07
0.08
0.09
0.1 0.11
0.12 0.13
0.14
0.5 0.75 1.0 1.5 2.0 2.5 3.0 3.5 4.0
2 4 6 8 10 12
Schottky Half
-
Cell Pitch
H
Μ
m
L
Reverse
Voltage
H
kV
L
¬DFBNHeVL
(b): ∆ΦBN
200
400
600
800 1000 1200
0.5 0.75 1.0 1.5 2.0 2.5 3.0 3.5 4.0
2 4 6 8 10 12
Schottky Half
-
Cell Pitch
H
Μ
m
L
Reverse
Voltage
H
kV
L
¬EmaxHkVcmL
(a): Emax
0.05 0.06
0.07
0.08 0.09
0.1
0.11 0.12
0.13
0.5 0.75 1.0 1.5 2.0 2.5 3.0 3.5 4.0
2 4 6 8 10 12
Schottky Half
-
Cell Pitch
H
Μ
m
L
Reverse
Voltage
H
kV
L
¬DFBNHeVL
(b): ∆ΦBN
VF =
kT
q ln
JF
JS
+RSJF (2.7)
JS = AT2exp (−qφBN/kT) (2.8)
It is important to note that drift region resistance RS scales approximately as the square of the breakdown voltage [4]. Thus, with increasing breakdown voltage, it becomes increasingly prohibitive from a conduction loss standpoint to use a unipolar power device.
2.1.4 Switching characteristics
During a switching transient, power will be dissipated in a JBS diode due to capacitive dis-placement current. The disdis-placement current through the diode can be computed with
J =CJ,sp
∂V
∂t (2.9)
Where CJ,sp is the voltage-dependent specific junction capacitance, and is given by
CJ,sp ≈
s
2s
qNDVR
−1/2
:VR< VP T
sWD−1 :VR≥VP T
(2.10)
As the voltage across the device rises, the capacitance decreases, leading to a fall in the displacement current. Eventually, the device will reach the dc-link voltage, and∂V /∂tbecomes zero, completing the switching process. In 15 kV devices, switching losses in a unipolar diode can become significant due to the high voltages involved.
2.2
PiN Bipolar Power Diodes
Unipolar power diodes offer excellent switching performance, and are appropriate for many applications, especially those for low blocking voltages. For 10 kV+ class devices, the PiN power diode is also an attractive candidate [6]; However, in an SST application where high power density and high efficiency are both design criteria, the increased switching losses in the PiN diode do not make it universally a better choice.
2.2.1 Ideal On-State Carrier Distribution
greater than the drift region doping, and are equal to one another. Assuming a N-type drift region, this can be expressed as
p(x) =n(x)ND (2.11)
The above relationship greatly simplifies the analysis of the on-state characteristics. Gen-erally, carrier concentrations in a 1-D semiconductor device under steady state conditions can be described with
0 = n
τHL
+Dn
∂2n
∂x2 +µn
∂
∂x(nE) (2.12)
0 = p
τHL
+Dp
∂2p
∂x2 −µn
∂
∂x(pE) (2.13)
Combining these two equations, neglecting carrier transport due to the effects of the electric field, and by assuming Eq. 2.11, an equation for the ambipolar carrier concentration can be derived
0 = −n
τHL
+Da
∂2n
∂x2 (2.14)
where Da is the ambipolar diffusion coefficient, and is given by
Da =
2DnDp
Dn+Dp
(2.15)
It is important to note that this equation will no longer hold in the event that high level injection conditions (e.g. Eq. 2.11) are not satisfied. Boundary conditions for Eq. 2.14 can be derived by manipulating the current density equations [10]. At the anode and cathode, the current flow is either entirely hole current or electron current, respectively. Given this fact, the boundary conditions for the high level injection condition can be derived:
JT = 2qDn
∂n ∂x
x=+d
(2.16)
JT = −2qDp
∂n ∂x
x=−d
(2.17)
n(x) = τHLJT 2qLa
cosh(x/La) sinh(d/La) −B
sinh(x/La) cosh(d/La)
(2.18)
where the second term inside the parenthesis arises due to differing electron and hole mo-bilities. The mobility scaling coefficientB is given by
B= µn−µp
µn+µp
(2.19)
For the drift region defined in Section 2.1.1, a room temperature high level lifetime τHL of 1.5µs, and a forward currentJT of 30 A/cm2, and at 400 K, the solution to Eq. 2.18 is plotted in Figure 2.5. The simulated result assumes a thick, heavily doped anode.
0 25 50 75 100 125 150
5e15 1e16 2e16 3e16 4e16 5e16 7e16 1e17 2e17
Distance from AnodeHΜmL
Excess
carriers
H
cm
-3 L
analytical
sim
Figure 2.5: Plot of Eq. 2.18,τHL= 1.5 µs,JT = 30 A/cm2,T = 400 K
2.2.2 Non-ideal On-State Carrier Distribution
activation, simulations show that incomplete ionization of Al-type acceptors at 400 K results in approximately a 5% to 10% ionization rate. Thus, a junction doped with 1e19 cm-3Al ions will only have an effective doping concentration of 1e18 cm-3. Due to the effects of incomplete ionization and material quality, modern SiC junctions begin to suffer from the effects of injection efficency reduction starting at current densities of less than 1 A/cm2 [11]. To quantify the influence this has on the on-state carrier concentration, the effects of low-level injection into the P+ anode region can be modeled to find an alternate boundary condition at x=−d.
When the electron current is nonzero at the anode contact, it is appropriate to replace Eq. 2.17 with
p(−d) =n(−d) =pn (2.20)
The variable pn represents the minority carrier concentration in the drift region near the anode. The boundary condition at the cathode remains the same as Eq. 2.16: in 4H-SiC, the diffusivity for holes is much lower than that of electrons, especially in the heavily doped cathode region. Thus, the injection efficiency of the cathode should remain close to unity, especially if it is formed from a thick, heavily doped N+ substrate. Solving Eq. 2.14 with these alternate boundary conditions, an equation for the carrier concentration in the drift region that depends on pn can be derived
-n(x) = 1
2qDn sech
2d
La
2qDnpncosh
d−x
La
+JtLasinh
d+x
La
(2.21)
Now, an expression forpnmust be found. Using the Boltzmann quasiequilibrium assumption at the junction, we have
pn
pp = np
nn
= e−(q∆Va/kT) (2.22)
Where pn and np represent the excess hole and electron concentrations on the N- and P+ sides of the junction, respectively, and pp and nn represent the carrier concentrations on the alternate side of the junction. ∆Va is the voltage that is applied across the junction. Due to high level injection, nn =pn, and due to the relative high doping concentration and low-level injection condition in the P+ anode, pp=NA. Rearranging Eq. 2.22,
np =
p2 n
NA
(2.23)
Jn=qµnAnE+qDnA
∂n ∂x
=qDnA
np
WA
= qDnAp 2 n
WANA
(2.24)
WhereWAis the depth of the anode junction, andDnA is the diffusivity of electrons in the anode. The hole current at the junction can be solved using the hole current density equation neglecting transport due to the electric field:
Jp =qµpnE−qDp
∂n ∂x (2.25) ∂n
∂x is given by the derivative of Eq. 2.21. Then, by using the fact that at the junction
Jp+Jn=JT, an expression forpn in terms of physical parameters and JT can be derived.
pn=
√
WANA
2DnA
√
qDnLa
sech
2d
La
4DnADnJTL2acosh2
2d
La
+
2DnADpJTL2acosh
2d
La
+DnD2pNAqWAsinh2
2d
La
1/2
−
DpNAWAtanh
2d La
2DnALa
(2.26)
This expression for pn can be then substituted into Eq. 2.21 to obtain an on-state carrier distribution for a 4H-SiC PiN diode with a non-unity injection effeciency due to incomplete ionization and a shallow P+ junction. The resulting carrier distribution for a diode with a P+ junction depth of 1µm and an effective doping concentration of 1e18 cm-3 at 30 A/cm2 is plotted in Figure 2.6.
2.2.3 Switching characteristics
Before the PiN diode can begin to support voltage, the large amount of charge stored in the drift region during the forward conduction must be removed. This process necessarily takes more time than than the recovery of a unipolar diode. In addition, the extracted charge carriers lead to additional current during the turn-off process, which can lead to large energy losses in each switching cycle.
0 25 50 75 100 125 150 5e15
1e16 2e16 3e16 4e16 5e16 7e16 1e17 2e17
Distance from AnodeHΜmL
Excess
carriers
H
cm
-3 L Γ=
1
Γ<1
sim
Figure 2.6: Plot of carrier density for a PiN diode with WA=1µm, NA=1e18 cm-3, JT=30 A/cm2. Plots assuming unity injection efficiency, non-unity injection efficiency, and a simulated result are included
In the model in [4], an assumption is made that when the supply voltage is reached, holes transiting the space charge region cause the space charge region to occupy less width than the total width of the drift region. This “dynamic” hole density is calculated using
p = Jrev/(qvsat,p). This is a reasonable assumption for silicon rectifiers: the value of
Jrev can be quite high, due to the long drift regions and high minority carrier lifetimes that are often used in high voltage Si rectifiers. The value of vsat,p is also less than 1e7 cm/s in Si [4], but is as high as 2e7 in SiC [12]. In addition, doping concentrations in Si power rectifiers can be below 1014 cm-3, increasing the relative contribution of the dynamic hole charge during reverse recovery. For a 15 kV SiC rectifier however, the doping concentration used in the drift region is far higher than an equivalent Si structure (4.5e14 cm-3for the diode described in this chapter): a calculation shows that for the case of Jrev =200 A/cm2, the dynamic doping of the space charge region during the reverse recovery process is only 0.6e14 cm-3. As a consequence, attempting to use the model in [4] for a 15 kV class SiC rectifier may result in negative values for the undepleted drift region length once the supply voltage is reached.
will have the effect of the model in [4] giving higher-than-expected peak reverse currents due to the fact that less charge is stored near the anode junction than is predicted by the unity injection efficency model.
The analytical model was also not derived with consideration for punchthrough drift regions: when the punchthrough condition occurs during the reverse recovery process, the space charge region has necessarily expanded all the way to the epilayer boundary, and thus all of the charge in the drift region has been removed. Because no charge is left in the diode, the current will abruptly drop to zero, and the voltage will rise to the supply voltage at a rate determined by the (small) depletion capacitance. This results in a so calledsnappy recovery, an undesirable condition from a circuit standpoint due to the high values of di/dt it produces.
The analytical model in [4] is compared to the results of a simulation in Figure 2.7a. A drift region width of 160µm with 4.5e14 doping was used: this drift region is long enough for all of the assumptions made in the analytical model to hold. A room temperatureτHL of 1.5 µs was used. The ramp rate used was 475 A/(µs cm2), and the DC-link voltage was assumed to be 12 kV. The features that make the analytical model produce a waveform that does not agree with the simulation for this particular structure are visible: the peak reverse current is higher than predicted due to the subunity injection efficiency of the anode junction, and the reverse recovery process is snappier for the numerical simulation.
0 200ns 400ns 600ns -300 -250 -200 -150 -100 -50 0 0 6 12
timeHsL
J H A cm 2L Reverse Voltage H kV L VR JRR
(a): Analytical Model
0 200ns 400ns 600ns 800ns -200 -150 -100 -50 0 0 12 6
timeHsL
J H A cm 2L Reverse Voltage H kV L VR JRR (b): Simulation
For 15 kV class SiC diodes, one-dimensional or 2D mixed mode finite element simulation are a good choice for simulating switching characteristics. It should be noted that even finite element simulations poorly model device dynamic characteristics unless the input model is matched to measured data for a given process. Although using published physical models to calibrate a simulator is as good a start as one can make for device design given no process information, one cannot expect the simulation to match experimental results unless parameters such as lifetime reduction due to implantation damage are taken into account. This is discussed later, in chapter 5.
2.2.4 Maximum di/dt during diode turnoff
A limit is imposed on the maximum value of di/dt that can be used to turn-off a diode: the value of di/dtthat is used determines the peak currentJP R that is reached during the reverse recovery process. Physically, high values ofdi/dtincreasing JP R is the result of a reduction of the storage time for high values of di/dt. If the storage time is reduced, more charge remains in the drift region after the termination of the storage phase, necessitating higher values of current to affect its complete removal. Because the current flowing through the diode during the reverse recovery process determines the density of holes that are transiting the space charge region, a higher value of di/dt will result in a larger value of the dynamic charge pn [4]. The value of pn is given by Eq. 2.27.
psc =
JR
qvsat,p
(2.27)
If the dynamic chargepn is high enough, it will increase the effective doping concentration of the space-charge region during the reverse recovery transient, causing the reverse voltage to be supported over less distance than it would be without the presence of the dynamic charge, and increasing the peak electric field. If the peak field exceeds the material’s critical electric field, a condition known as dynamic avalanche will occur [13]. An illustration of the dynamic avalanche process for a diode switched with either a high value ofdi/dtor a low value ofdi/dt
is shown in Figure 2.8, and is explained as follows:
In Figure 2.8 (a.), in both the high di/dtand low di/dt scenario, the storage period has completed and the diode is beginning to support voltage. The absolute reverse recovery current is low in each case, sopsc is small, and the electric field profile is about the same.
In Figure 2.8 (c.), for the highdi/dtcase, the value ofpsc is sufficient to cause the electric field to exceed the critical field at the junction. The diode enters dynamic avalanche, likely resulting in a catastrophic failure of the device.
Current Waveform
time
Carrier Profile Electric Field Profile
a. b. c. A K ND psc W A K EC E W A K ND psc W A K EC E W A K ND psc W A K EC E W remaining carriers psc psc JF JPR JPR JF high di/dt low di/dt JF JPR JPR JF high di/dt low di/dt JF JPR JPR JF high di/dt low di/dt V=0.1 VBUS
V=0.25 VBUS
V=0.95 VBUS
Figure 2.8: Illustration of dynamic avalanche process in a power diode
Em =
q(ND+psc)
s
Wsc (2.28)
Wsc =
s
2sVR
q(ND+psc)
(2.29)
After substituting Eq. 2.27 for psc and solving forJR, then multiplying byVR to get units of power, the value forPcrit is given by Eq. 2.30.
Pcrit =
1 2E
2
Csvsat,p−qNDVRvsat,p (2.30)
If the assumption thatpsc ND is made, Eq. 2.30 reduces to the formPcrit = 0.5EC2svsat,p originally given in [14]. This is a reasonable assumption in silicon power devices, because the doping concentrations that must be used to achieve high breakdown voltages are small due to the material’s low critical field. In 4H-SiC, this is no longer a valid assumption, so the full form of Eq. 2.30 must be used to find the dynamic avalanche limit for 4H-SiC. Eq. 2.30 can also be stated in terms of the peak reverse recovery current JP R to compute a “critical current” that will result in dynamic avalanche for a given bus voltage.
The reverse recovery model for PiN diodes developed in [4] was used to derive a relationship between di/dt and JP R. The reverse recovery model assumes a simplified on-state charge distribution, which is removed during the reverse recovery process in several stages by a current ramp with constant di/dt. Because the equations used in the model in [4] are transcendental and require iteration to solve, no closed form solution is possible for an equation that relates
di/dtand JP R, however, the model can be used to numerically compute a solution for a value
of di/dt that results in the peak current JP R becoming equal to the critical current Jcrit for
initiation of dynamic avalanche. The results of this computation for the 150 µm thick, 4.5e14 cm-3 doped drift region with 1.5 µs lifetime discussed in this chapter are shown in Figure 2.9: an equivalent structure for a 15 kV silicon diode (WD=2.77 mm,ND=3.2e12 cm-3,τA=50µs) is shown for comparison. For the silicon diode, Pcrit was assumed to be 300 kW/cm2, for the SiC diode, Eq. 2.30 was used. Even for a forward current density of 200 A/cm2, the SiC diode can turn off with a di/dtvalue of up to 2 kA/(µs cm2).
Figure 2.9 does not provide a definitive reference for any power diode implementation (it is a solution for two particular drift regions). A more general plot for the di/dt limit can be made by making a few assumptions about the way drift regions are designed, and allowing
1
2
5
10
20
50
100
200
1
10
100
1000
10
410
510
6J
F,maxH
A
cm
2L
H
di
dt
L
maxH
A
Μ
s
×
cm
2
L
4H-SiC
Silicon
Figure 2.9: Plot ofdi/dtmax vs. JF for 15 kV silicon and 4H-SiC power diodes
Figure 2.11, Figure 2.12, and Figure 2.13:
Drift regions use a non-punchthrough design, and are designed such that parallel plane breakdown voltage is 1.25x the expected breakdown voltage to account for the effects of non-ideal edge termination. In the operational state, the diode blocks 2/3rds of its designed voltage.
Baliga’s power law [15] is used to determine the doping required to achieve a certain breakdown voltage in Si
A power law fit to Konstantinov’s form of the critical field is used to determine the required doping for a given BV in SiC. The power law is of the form BVP P = 1.94e15 ND−3/4
The required ambipolar lifetimeτAis assumed to scale linearly from zero with breakdown voltage, and has a value of 62.5 µs at 15 kV for silicon, and 10µs at 15 kV for 4H-SiC. This will result in “slow” diodes with a lowVF.
2 3 4 5 6 7 8 9 10 15 5
10 20 30 40 50 100 150
Blocking Voltage
H
kV
L
J
F,max
H
A
cm
2
L
di
dt
maxfor Silicon
100 10-1
101
102
103
¬didtmaxHAΜs×cm2L
(a): Silicon
2 3 4 5 6 7 8 9 10 15
5 10 20 30 40 50 100 150
Blocking Voltage
H
kV
L
J
F,max
H
A
cm
2
L
di
dt
maxfor 4H
-
SiC
104 2×103 105
106
107
¬didtmaxHAΜs×cm2L
(b): 4H-SiC
2
3
4
5
6
7
8 9 10
15
10
20
50
100
200
500
1000
2000
Blocking Voltage
H
kV
L
Drift
Region
Length
H
Μ
m
L
4H-SiC Silicon
Figure 2.11: Drift region length design rule used when computing maximum di/dt capability of 4H-SiC and silicon power diodes
2
3
4
5
6
7
8
9 10
15
10
1210
1310
1410
1510
16Blocking Voltage
H
kV
L
Drift
Region
Doping
H
cm
-3
L
4H-SiC
Silicon
2
3
4
5
6
7
8
9 10
15
1
5
10
50
100
Blocking Voltage
H
kV
L
Designed
Drift
Lifetime
H
Μ
s
L
4H-SiC Silicon
Figure 2.13: Drift region lifetime design rule used when computing maximumdi/dtcapability of 4H-SiC and silicon power diodes
assume unity anode injection efficiency and a high drift region minority carrier lifetime. Any effects that reduce the injection efficiency of the anode will also increase the value ofdi/dtmax by reducing the stored charge in the diode, and therefore reducingJP R (as seen in Figure 2.7). This is one motivating factor behind moving to a diode topology that has a weak anode.
2.3
Low Injection Efficiency Bipolar Diodes
In a diode with a low injection efficiency P+ emitter, the anode’s low injection efficiency causes the high-level injection boundary condition in Eq. 2.17 to no longer be true. The alternate boundary condition, which is determined either by low-level injection physics (in the case of Static Shielding Diodes (SSDs) [6] and SPEED [16] diodes) or the additional electron current carried by a Schottky contact (in the case of a MPS diode) results in the minority carrier density near the anode dropping to a low value, or close to zero, respectively. Because bipolar injection reduces the on-resistance of the drift region at higher current densities, these diodes are expected to provide better surge handling capability when compared to a pure unipolar device.
differently from the PiN diode, as a result of the differing boundary conditions and on-state carrier profile. Among the earliest examples of using a low-injection efficiency anode in a rectifier are the works of Naito [17], Baliga [18], and Hower [19]. However, examples of bipolar diodes that utilize this concept in 4H-SiC have only been reported recently in literature [20], and have not been reported for 15 kV class devices.
2.3.1 On-state carrier concentration: MPS diode
At a Schottky contact to N- material, only electron current can flow under normal conditions. Thus, the injection efficiency of the anode junction can be assumed to be zero and the injected hole concentration pn can also be assumed to be zero. Substituting pn = 0 into Eq. 2.21, an expression for the high-level injection carrier concentration in an MPS diode can be obtained [6]
n(x) = JtLa
2qDn sech
2d
La
sinh
d+x
La
(2.31)
2.3.2 On-state carrier concentration: SSD
A model for the on-state carrier concentration of a SSD is developed in [6]. The SSD is characterized by its use of a thin, lightly doped P- anode region interspersed with heavily doped P+ anode regions. Current preferentially flows through the P- regions due to their lower built-in potential.
The model developed in [6] neglects the effects of recombination in the drift region to describe the carrier concentration, e.g. the ambipolar carrier continuity equation is written as
∂2n/∂x2 = 0. This assumption is appropriate if the carrier lifetime in the drift region is high, however, in 4H-SiC, thick epitaxial regions with lifetimes high enough to make this assumption are not available. Thus, it is more appropriate to use the model developed in Section 2.2.2, which accounts for both the low injection efficiency at the anode, as well as recombination in the drift region. The results of this analysis are plotted below in Figure 2.14 for a drift region width and doping of 150 µm and 4.5e14 cm-3, and an P- emitter depth of 1 µm and various emitter doping concentrations. The curve for the MPS diode assumes a finite carrier concentration of
pn=ND at the anode junction.
2.3.3 On state forward voltage drop
0 25 50 75 100 125 150 1´1015
2´1015 5´1015 1´1016 2´1016 5´1016
Distance from AnodeHΜmL
Excess
carriers
H
cm
-3 L
MPS 1015
1016
1017
1018
Figure 2.14: Plot of Eq. 2.21,τHL= 1.5 µs,JT = 30 A/cm2,T = 400 K for various P- emitter dopings as indicated on plot
Voltage drop across the middle region
The voltage drop in the middle region of the diode depends on the on-state carrier concentration. Following the analysis for the voltage drop of a PiN diode in [4], the current densities in the drift region can be written as
Jp = qµp
pE−kT
q ∂p ∂x
(2.32)
Jn = qµn
nE+kT
q ∂n ∂x
(2.33)
Using the space-charge neutrality condition given by Eq. 2.11 and the fact thatJt=Jp+Jn, these expressions can be combined to form
E(x) = Jt
q(µn+µp)n
− kT
2qn ∂n
∂x (2.34)
By substituting Eq. 2.21 for n and integrating from−dto +d, the voltage drop across the middle region can be computed. However, given the complexity of the solution for the carrier concentration, this integration yields expressions that are too long to be useful for the purposes of developing a simple analytical model. The first term in Eq. 2.34 is of the familiar form
Z +d
−d
E(x)∂x=
Z +d
−d
Jt
q(µn+µp)n
∂x− Z +d −d kT 2qn ∂n
∂x∂x=Vm=Vm,ohmic−Vm,f ield (2.35)
The total carrier concentration in the drift region can be integrated and averaged to compute a resistivity, and the voltage drop across the drift region as a whole can be computed. The average carrier concentration in the drift region is given by
Nav=
1 2d
Z +d
−d
n(x)∂x= La
2d
pntanh
2d
La
− JtLa
2qDn
sech 2d La −1 (2.36)
The expression given above for Nav can be used to compute a specific resistivity for the drift region, which, in high level injection, is given by
ρs= 2d
1
qNav(µn+µp)
(2.37)
Eq. 2.37 can be multiplied by the current density to obtain the ohmic voltage drop:
Vm,ohmic =ρsJt=
−8d2DnJt
La(µn+µp)
JtLa
sech 2d La −1
−2Dnpnqtanh
2d
La
−1
(2.38)
Now, the second term in Eq. 2.34 should be integrated over the drift region to obtain the voltage drop due to the charge-dependent electric field:
Vm,f ield=
kT 2q Z +d −d 1 n ∂n ∂x = kT
2q ln sech 2d La
+ JtLa 2qDnpn
tanh 2d La (2.39)
Eq. 2.38 and Eq. 2.39 can now be combined using Eq. 2.35 to obtain the voltage drop across the middle region of the diode. This result is plotted vs. anode doping, as well as the case of a MPS rectifier in Figure 2.15
SSD Junction potential
In the SSD, the Maxwell-Boltzmann equilibrium condition can be invoked at both the P-/N-anode junction, and the N-/N+ cathode junction. The junction potential can be expressed in a similar form to the PiN diode junction potential:
VP−+VN+=
kT
q ln
pnn(+d)
n2 i
1015 1016 1017 1018 1019 0.0
0.5 1.0 1.5
P
-Emitter Doping
H
cm
-3L
Voltage
Drop
H
V
L
MPS
SSD
Figure 2.15: Voltage drop across the middle region of 15 kV MPS and SSD rectifiers
The total voltage drop across the diode can be obtained by adding Eq. 2.40 and Vm as derived above.
MPS Junction potential
For MPS diodes, most of the anode current flows through the Schottky contact. Thus, thermionic emission theory can be used to derive an expression for the voltage drop at the anode [6]:
VA= ΦB+
kT
q ln
JTp
AT2
(2.41)
Wherepis the ratio between the total cell width and Schottky contact width, which accounts for the increased current density at the Schottky contact. At the cathode, the voltage drop across the N-/N+ junction is given by
VN+=
kT
q ln
n(+d)
ND
(2.42)
state: the low barrier will serve to short out the P+/N junction at low to moderate current densities, leading to no injection of minority carriers. Because the models for the MPS diode were derived assuming that minority carrier injection occurs, utilizing zero or low barrier height will violate this assumption. In silicon, due to the low P+/N junction potential inherent to the material, most Schottky metals will result in MPS diodes that operate in bipolar mode. However, in SiC, the P+/N junction potential is on the order of 2.7 eV, which can lead to problems with this model. This effect is discussed further in chapter 3.
The combined junction/middle region voltage drop for SSDs with various anode dopings, as well as an MPS diode are plotted in Figure 2.16. For this figure, the barrier height in the MPS diode was taken to be 2.7 eV, and the variablep in Eq. 2.41 to be around 3.
3.0 3.2 3.4 3.6 3.8 4.0 4.2
1 2 5 10 20 50
Voltage Drop
H
V
L
Current
Density
H
A
cm
2
L
MPS
1016 1017
1018 1019
2.3.4 Stored Charge
To visualize the benefits of using a low injection efficiency structure over a normal PiN diode, a trade-off, or technology curve can be developed for diodes with anodes of varying injection efficiency. Based on the on-state carrier profile and voltage drop models developed in this profile, the stored charge density for SSDs with anode doping concentrations ranging from 1e16 cm-3 to 1e18 cm-3, as well as PiN and MPS diodes is plotted below in Figure 2.17. The results show that for an increase of about 1V in VF, it is possible to achieve a 8x reduction in stored charge.
3.4 3.6 3.8 4.0 4.2
0 2´1014 4´1014 6´1014 8´1014
V
F
30 A
cm
2Stored
Charge
H
C
cm
2
L
SSDs
MPS PiN
Figure 2.17: Stored Charge vs. Forward Drop at Jt=30 A/cm2 for various 15 kV rectifiers
2.3.5 Maximum di/dt for low-injection efficiency diodes
same drift region parameters. This should lead to an increase in the maximumdi/dtcapability of an MPS diode when compared to a PiN.
Using the same drift regions as those computed for Figure 2.9, the value of di/dtmax was calculated and plotted in Figure 2.18 by using the MPS reverse recovery model in [6] to compute the value of the peak current. For a silicon 15 kV rectifier, using an MPS topology results in nearly 2x improvement in the value ofdi/dtmax; for the SiC rectifier, the increase is around 5x. The same approach was applied to generate plots similar to those in Figure 2.10 (and using the same drift region design rules listed in Section 2.2.4): the plots are shown in Figure 2.19, and indicate that for most operating points, both the Si and SiC MPS diodes have up to 1 order of magnitude improvement indi/dtmax when compared to PiN diodes with a strong anode.
1
2
5
10
20
50
100
200
1
10
100
1000
10
410
510
6J
F,maxH
A
cm
2L
H
di
dt
L
maxH
A
Μ
s
×
cm
2
L
4H-SiCHPiNL 4H-SiCHMPSL
SiliconHMPSL
SiliconHPiNL
Figure 2.18: Plot of di/dtmax vs. JF for 15 kV silicon and 4H-SiC MPS power diodes
2.4
Conclusions
2 3 4 5 6 7 8 9 10 15 5
10 20 30 40 50 100 150
Blocking Voltage
H
kV
L
J
F,max
H
A
cm
2
L
di
dt
maxfor Silicon
H
MPS
L
101 100
102
103
104
¬didtmaxHAΜs×cm2L
(a): Silicon
2 3 4 5 6 7 8 9 10 15
5 10 20 30 40 50 100 150
Blocking Voltage
H
kV
L
J
F,max
H
A
cm
2
L
di
dt
maxfor 4H
-
SiC
H
MPS
L
105 3×104 106
107
108 ¬didtmaxHAΜs×cm2L
(b): 4H-SiC
take into account recombination in the drift region, which is an important parameter for the thick drift regions required for 15 kV SiC devices.
Chapter 3
4H-SiC MPS Diodes
Designing 4H-SiC MPS diodes presents challenges unique to the material - the high built-in potential of 4H-SiC suppresses the injection of minority carriers unless the effective barrier height of the Schottky contact is close to that ofφbi. This is discussed in Section 3.1. Based on the physics developed in the previous chapter, the fundamental parameters listed in Table 3.1 were chosen for a 4H-SiC MPS rectifier, and are used in all of the following calculations unless otherwise measured.
3.1
Design of the Schottky Barrier
In an MPS diode, in order to forward-bias the P+N junction, the barrier height of the metal must be comparable to that of the built-in potential of the junction [6]. For silicon carbide, however, this is difficult to realize due to the material’s inherent physical properties: the barrier height of a Schottky contact can be expressed as
ΦBN = ΦM−χS (3.1)
Table 3.1: Device device parameters
Parameter Value