DESCRIPTIO. LT1226 Low Noise Very High Speed Operational Amplifier

1

■ Gain of 25 Stable

■ 1GHz Gain Bandwidth

■ 400V/µs Slew Rate

■ 2.6nV/√Hz Input Noise Voltage

■ 50V/mV Minimum DC Gain, R_L = 500Ω

■ 1mV Maximum Input Offset Voltage

■ ±12V Minimum Output Swing into 500Ω

■ Wide Supply Range ±2.5V to ±15V

■ 7mA Supply Current

■ 100ns Settling Time to 0.1%, 10V Step

■ Drives All Capacitive Loads

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ESCRIPTIO S

FEATURE

The LT1226 is a low noise, very high speed operational amplifier with excellent DC performance. The LT1226 features low input offset voltage and high DC gain. The circuit is a single gain stage with outstanding settling characteristics. The fast settling time makes the circuit an ideal choice for data acquisition systems. The output is capable of driving a 500Ω load to ±12V with ±15V supplies and a 150Ω load to ±3V on ±5V supplies. The circuit is also capable of driving large capacitive loads which makes it useful in buffer or cable driver applications.

The LT1226 is a member of a family of fast, high per- formance amplifiers that employ Linear Technology Corporation’s advanced bipolar complementary processing.

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PPLICATI

■ Wideband Amplifiers

■ Buffers

■ Active Filters

■ Video and RF Amplification

■ Cable Drivers

■ Data Acquisition Systems

A O U

PPLICATI TYPICAL

Photodiode Preamplifier, A_V = 5.1kΩ, BW = 15MHz Gain of +25 Pulse Response

Low Noise Very High Speed Operational Amplifier

5.1k

LT1226 TA01

– +

LT1226

51Ω 51Ω V⁺

LT1226 TA02

2

Total Supply Voltage (V⁺ to V^–) ... 36V Differential Input Voltage ...±6V Input Voltage ...±V_S Output Short Circuit Duration (Note 1) ... Indefinite Operating Temperature Range

LT1226C ... 0°C to 70°C Maximum Junction Temperature

Plastic Package ... 150°C Storage Temperature Range ... – 65°C to 150°C Lead Temperature (Soldering, 10 sec.)... 300°C

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A W U W

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BSOLUTE XI TI S U W U

PACKAGE/ORDER I FOR ATIO

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V_OS Input Offset Voltage (Note 2) 0.3 1.0 mV

I_OS Input Offset Current 100 400 nA

IB Input Bias Current 4 8 µA

en Input Noise Voltage f = 10kHz 2.6 nV/√Hz

in Input Noise Current f = 10kHz 1.5 pA/√Hz

RIN Input Resistance VCM = ±12V 24 40 MΩ

Differential 15 kΩ

C_IN Input Capacitance 2 pF

Input Voltage Range + 12 14 V

Input Voltage Range – – 13 – 12 V

CMRR Common-Mode Rejection Ratio V_CM = ±12V 94 103 dB

PSRR Power Supply Rejection Ratio V_S = ±5V to ±15V 94 110 dB

A_VOL Large Signal Voltage Gain V_OUT = ±10V, R_L = 500Ω 50 150 V/mV

V_OUT Output Swing R_L = 500Ω 12.0 13.3 ±V

I_OUT Output Current V_OUT = ±12V 24 40 mA

SR Slew Rate (Note 3) 250 400 V/µs

Full Power Bandwidth 10V Peak, (Note 4) 6.4 MHz

GBW Gain Bandwidth f = 1MHz 1 GHz

tr, tf Rise Time, Fall Time AVCL = + 25,10% to 90%, 0.1V 5.5 ns

Overshoot AVCL = +25, 0.1V 35 %

Propagation Delay 50% V_IN to 50% V_OUT 5.5 ns

t_s Settling Time 10V Step, 0.1%, A_V = – 25 100 ns

Differential Gain f = 3.58MHz, A_V = +25, R_L = 150Ω 0.7 %

Differential Phase f = 3.58MHz, A_V = +25, R_L = 150Ω 0.6 Deg

R_O Output Resistance A_VCL = +25, f = 1MHz 3.1 Ω

I_S Supply Current 7 9 mA

ELECTRICAL C HARA TERISTICS C

^VS = ±15V, T_A = 25°C, V_CM = 0V unless otherwise noted.

1 2 3

4 5

6 7 8 TOP VIEW NULL

V⁺ NULL –IN

OUT NC +IN

V^–

S8 PACKAGE 8-LEAD PLASTIC SOIC N8 PACKAGE

8-LEAD PLASTIC DIP

LT1226 PO01

ORDER PART NUMBER

S8 PART MARKING 1226

LT1226CN8 LT1226CS8

3

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V_OS Input Offset Voltage V_S = ±15V, (Note 2) 0.3 1.3 mV

V_S = ± 5V, (Note 2) 1.0 1.8 mV

Input V_OS Drift 6 µV/°C

IOS Input Offset Current VS = ±15V and VS = ±5V 100 600 nA

IB Input Bias Current VS = ±15V and VS = ±5V 4 9 µA

CMRR Common-Mode Rejection Ratio VS = ±15V, VCM = ±12V and VS = ±5V, VCM = ±2.5V 92 103 dB

PSRR Power Supply Rejection Ratio V_S = ±5V to ±15V 92 110 dB

A_VOL Large Signal Voltage Gain V_S = ±15V, VOUT = ±10V, RL = 500Ω 35 150 V/mV

V_S = ±5V, V_OUT = ±2.5V, R_L = 500Ω 35 100 V/mV

V_OUT Output Swing V_S = ±15V, R_L = 500Ω 12.0 13.3 ±V

VS = ±5V, RL = 500Ω or 150Ω 3.0 3.3 ±V

IOUT Output Current VS = ±15V, VOUT = ±12V 24 40 mA

V_S = ±5V, V_OUT = ±3V 20 40 mA

SR Slew Rate V_S = ±15V, (Note 3) 250 400 V/µs

I_S Supply Current V_S = ±15V and V_S = ±5V 7 10.5 mA

V_S = ±5V, T_A = 25°C, V_CM = 0V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V_OS Input Offset Voltage (Note 2) 1.0 1.4 mV

I_OS Input Offset Current 100 400 nA

I_B Input Bias Current 4 8 µA

Input Voltage Range + 2.5 4 V

Input Voltage Range – –3 –2.5 V

CMRR Common-Mode Rejection Ratio V_CM = ±2.5V 94 103 dB

A_VOL Large Signal Voltage Gain V_OUT = ±2.5V, R_L = 500Ω 50 100 V/mV

V_OUT = ±2.5V, RL = 150Ω 75 V/mV

V_OUT Output Voltage R_L = 500Ω 3.0 3.7 ±V

R_L = 150Ω 3.0 3.3 ±V

I_OUT Output Current V_OUT = ±3V 20 40 mA

SR Slew Rate (Note 3) 250 V/µs

Full Power Bandwidth 3V Peak, (Note 4) 13.3 MHz

GBW Gain Bandwidth f = 1MHz 700 MHz

t_r, t_f Rise Time, Fall Time A_VCL = +25, 10% to 90%, 0.1V 8 ns

Overshoot A_VCL = +25, 0.1V 25 %

Propagation Delay 50% V_IN to 50% V_OUT 8 ns

t_s Settling Time – 2.5V to 2.5V, 0.1%, A_V = – 24 60 ns

I_S Supply Current 7 9 mA

ELECTRICAL C HARA TERISTICS C

ELECTRICAL C HARA TERISTICS C

Note 3: Slew rate is measured between ±10V on an output swing of ±12V on ±15V supplies, and ±2V on an output swing of ±3.5V on ±5V supplies.

Note 4: Full power bandwidth is calculated from the slew rate measurement: FPBW = SR/2πVp.

Note 1: A heat sink may be required to keep the junction temperature below absolute maximum when the output is shorted indefinitely.

Note 2: Input offset voltage is tested with automated test equipment in <1 second.

0°C ≤ T_A≤ 70°C, V_CM = 0V unless otherwise noted.

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C HARA TERISTICS C U

A W TYPICAL PERFOR CE

Output Short Circuit Current vs Supply Current vs Temperature Input Bias Current vs Temperature Temperature

Output Voltage Swing vs Input Bias Current vs Input Open Loop Gain vs

Resistive Load Common Mode Voltage Resistive Load

Input Common Mode Range vs Output Voltage Swing vs

Supply Voltage Supply Current vs Supply Voltage Supply Voltage

SUPPLY VOLTAGE (±V) 0

0

MAGNITUDE OF INPUT VOLTAGE (V)

5 10 15 20

5 10 15 20

LT1226 TPC01

T_A = 25°C

∆VOS < 1mV

+V_CM –V_CM

SUPPLY VOLTAGE (±V) 0

6.0 SUPPLY CURRENT (mA) 6.5 7.0 7.5 8.0

5 10 15 20

LT1226 TPC02

T_A = 25°C

SUPPLY VOLTAGE (±V) 0

0

OUTPUT VOLTAGE SWING (V) 5

10 15 20

5 10 15 20

LT1226 TPC03

T_A = 25°C R_L = 500Ω

∆VOS = 30mV

+V_SW

–V_SW

LOAD RESISTANCE (Ω) 10

0

OUTPUT VOLTAGE SWING (Vp-p)

10 20 25 30

100 1k 10k

LT1226 TPC04

15

5

T_A = 25°C

∆VOS = 30mV

V_S = ±15V

V_S = ±5V

INPUT COMMON MODE VOLTAGE (V) –15

3.0

INPUT BIAS CURRENT (µA)

3.5 4.0 4.5 5.0

–10 0 10 15

LT1226 TPC05

–5 5

V_S = ±15V T_A = 25°C I_B+ + I_B–

2 I_B =

LOAD RESISTANCE (Ω) 10

70

OPEN LOOP GAIN (dB)

100 110 120

100 1k 10k

LT1226 TPC06

90

80

T_A = 25°C

V_S = ±15V

V_S = ±5V

TEMPERATURE (°C) –50

4

SUPPLY CURRENT (mA)

6 7 9 10

–25 25 75 125

LT1226 TPC07

V_S = ±15V

100 50

0 5

8

TEMPERATURE (°C) –50

25

OUTPUT SHORT CIRCUIT CURRENT (mA)

35 40 50 55

–25 25 75 125

LT1226 TPC09

100 50

0 30

45

V_S = ±5V

SOURCE SINK

TEMPERATURE (°C) –50

3.5

INPUT BIAS CURRENT (µA)

4.0 4.25 4.75 5.0

–25 25 75 125

LT1226 TPC08

100 50

0 3.75

4.5

V_S = ±15V I_B+ + I_B–

2 I_B =

5

C HARA TERISTICS C U

A W TYPICAL PERFOR CE

Closed Loop Output Impedance vs

Frequency Gain Bandwidth vs Temperature Slew Rate vs Temperature

Voltage Gain and Phase vs Frequency Response vs

Frequency Output Swing vs Settling Time Capacitive Load

Power Supply Rejection Ratio vs Common Mode Rejection Ratio vs

Input Noise Spectral Density Frequency Frequency

FREQUENCY (Hz) 1k

0

COMMON MODE REJECTION RATIO (dB)

20 40 60 80 100 120

10k 100k 1M 10M

LT1226 TPC12

100M VS = ±15V TA = 25°C

TEMPERATURE (˚C) –50

GAIN BANDWIDTH (MHz)

1.05 1.10 1.15

25 75

LT1226 TPC17

1.0

0.95

–25 0 50 100 125

0.90

0.85

V_S = ±15V FREQUENCY (Hz)

100 10

VOLTAGE GAIN (dB)

30 50 70 90 110

1k 10k 100k 1M

LT1226 TPC13

10M 100M0 20 40 60 80 100

PHASE MARGIN (DEGREES)

V_S = ±15V

VS = ±5V

T_A = 25°C

VS = ±5V

VS = ±15V

TEMPERATURE (˚C) –50

SLEW RATE (V/µs) 400

450 500

25 75

LT1226 TPC18

350

300

–25 0 50 100 125

250

200

–SR

+SR VS = ±15V

AV = –25

FREQUENCY (Hz) 10k

OUTPUT IMPEDANCE (Ω)

1 10

100M

LT1226 TPC16

0.1

0.01

100k 1M 10M

100

VS = ±15V TA = 25°C AV = +25

FREQUENCY (Hz)

INPUT VOLTAGE NOISE (nV/√Hz)

1 100

10 1k 10k 100k

LT1226 TPC10

100 1000

10

V_S = ±15V T_A = 25°C A_V = +101 R_S = 100kΩ in

e_n

0.01 1.0 10

0.1

INPUT VOLTAGE NOISE (nV/√Hz)

FREQUENCY (Hz) 100

0

POWER SUPPLY REJECTION RATIO (dB)

40 60 80 100 120

1k 10k 100k 1M

LT1226 TPC11

10M 100M VS = ±15V TA = 25°C

+PSRR –PSRR

SETTLING TIME (ns) 0

OUTPUT SWING (V)

2 6 10

80 –2

–6

–10

20 40 60 100 120

LTC1226 TPC14

0 4 8

–4

–8 VS = ±15 TA = 25°C 10mV SETTLING

A_V = +25 A_V = –25

A_V = –25 AV = +25

FREQUENCY (HZ) 1M

18

VOLTAGE MAGNITUDE (dB) 22

26 30 34 38

10M 100M

C = 100pF

C = 0pF C = 50pF

LT1226 TPC15

20 24 28 32

36 VS = ±15V TA = 25°C AV = –25

C = 1000pF C = 500pF

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U S

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PPLICATI U W U

I FOR ATIO

The LT1226 may be inserted directly into HA2541, HA2544, AD847, EL2020 and LM6361 applications, provided that the amplifier configuration is a noise gain of 25 or greater, and the nulling circuitry is removed. The suggested nulling circuit for the LT1226 is shown below.

Offset Nulling

Layout and Passive Components

As with any high speed operational amplifier, care must be taken in board layout in order to obtain maximum perfor- mance. Key layout issues include: use of a ground plane, minimization of stray capacitance at the input pins, short lead lengths, RF-quality bypass capacitors located close to the device (typically 0.01µF to 0.1µF), and use of low ESR bypass capacitors for high drive current applications (typically 1µF to 10µF tantalum). Sockets should be avoided when maximum frequency performance is required, although low profile sockets can provide reasonable performance up to 50MHz. For more details see Design Note 50. Feedback resistors greater than 5kΩ are not recommended because a pole is formed with the input capacitance which can cause peaking. If feedback resistors greater than 5kΩ are used, a parallel capacitor of 5pF to 10pF should be used to cancel the input pole and optimize dynamic performance.

Transient Response

The LT1226 gain bandwidth is 1GHz when measured at 1MHz. The actual frequency response in a gain of +25 is considerably higher than 40MHz due to peaking caused by a second pole beyond the gain of 25 crossover point. This is reflected in the small signal transient response. Higher noise gain configurations exhibit less overshoot as seen in the inverting gain of 25 response.

Small Signal, A_V = +25 Small Signal, A_V = – 25

The large signal response in both inverting and noninvert- ing gain shows symmetrical slewing characteristics. Nor- mally the noninverting response has a much faster rising edge due to the rapid change in input common mode voltage which affects the tail current of the input differen- tial pair. Slew enhancement circuitry has been added to the LT1226 so that the falling edge slew rate is enhanced which balances the noninverting slew rate response.

Large Signal, A_V = +25 Large Signal, A_V = – 25

Input Considerations

Resistors in series with the inputs are recommended for the LT1226 in applications where the differential input voltage exceeds ±6V continuously or on a transient basis.

An example would be in noninverting configurations with high input slew rates or when driving heavy capacitive loads. The use of balanced source resistance at each input is recommended for applications where DC accuracy must be maximized.

Capacitive Loading

The LT1226 is stable with all capacitive loads. This is accomplished by sensing the load induced output pole and adding compensation at the amplifier gain node. As the capacitive load increases, both the bandwidth and phase margin decrease so there will be peaking in the

LT1226 AI03 LT1226 AI02

–

3 +

2 1

8

5k 0.1µF

7 6

4

0.1µF V⁺

V^– LT1226

LT1226 AI01

7

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PPLICATI U W U

I FOR ATIO

Compensation for Lower Closed-Loop Gains

frequency domain and in the transient response. The photo of the small signal response with 1000pF load shows 55% peaking. The large signal response with a 10,000pF load shows the output slew rate being limited by the short circuit current.

A_V = –25, C_L = 1000pF A_V = +25, C_L = 10,000pF

Lag Compensation

V_OS Null Loop

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PPLICATI TYPICAL

The LT1226 can drive coaxial cable directly, but for best pulse fidelity the cable should be doubly terminated with a resistor in series with the output.

Compensation

The LT1226 has a typical gain bandwidth product of 1GHz which allows it to have wide bandwidth in high gain

configurations (i.e., in a gain of 1000 it will have a bandwidth of about 1MHz). The amplifier is stable in a noise gain of 25 so the ratio of the output signal to the inverting input must be 1/25 or less. Straightforward gain configurations of +25 or –24 are stable, but there are a few configurations that allow the amplifier to be stable for lower signal gains (the noise gain, however, remains 25 or more). One example is the inverting amplifier shown in the typical applications sections below. The input signal has a gain of –R_F/R_IN to the output, but it is easily seen that this configuration is equivalent to a gain of –24 as far as the amplifier is concerned. Lag compensation can also be used to give a low frequency gain less than 25 with a high frequency gain of 25 or greater. The example below has a DC gain of 6, but an AC gain of +31. The break frequency of the RC combination across the amplifier inputs should be at least a factor of 10 less than the gain bandwidth of the amplifier divided by the high frequency gain (in this case 1/10 of 1GHz/31 or 3MHz).

Cable Driving

– +

200Ω LT1226

330pF VIN

VOUT

5k

LT1226 TA03

A_V = +6, f < 2MHz 1k

LT1226 TA04

R250Ω VIN

VOUT

R1 1.2k

R3 75 Ω

R4 75Ω 75 CABLEΩ LT1226

+ –

–

RC +

LT1226 VIN

VOUT

LT1226 TA05

R_IN

RF

RF R_IN

AV = – ; R_F ≥ 24 × (RIN || R_C)

VIN

VOUT

LT1226 TA06

– +

LT1226 300k 300k 1

8

10k 10k

25k

25Ω

100pF

100pF

LT1097

–

+

AV = 1001

LT1226 AI04

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of circuits as described herein will not infringe on existing patent rights.

8 Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7487

(408) 432-1900^● FAX: (408) 434-0507^●TELEX: 499-3977  LINEAR TECHNOLOGY CORPORATION 1992

LT/GP 0692 10K REV 0

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S PLI I F ED S W A CHE TIC

PACKAGE DESCRIPTIO U

N8 Package 8-Lead Plastic DIP

T_{J MAX} θJA 150°C 220°C/W

Dimensions in inches (millimeters) unless otherwise noted.

S8 Package 8-Lead Plastic SOIC

1 2 3 4

0.150 – 0.157 (3.810 – 3.988)

8 7 6 5

0.189 – 0.197 (4.801 – 5.004)

0.228 – 0.244 (5.791 – 6.198) 0.010 – 0.020

(0.254 – 0.508)

0.016 – 0.050 0.406 – 1.270

× 45°

0°– 8° TYP

0.008 – 0.010 (0.203 – 0.254)

S8 1291

0.053 – 0.069 (1.346 – 1.753)

0.014 – 0.019 (0.356 – 0.483)

0.004 – 0.010 (0.102 – 0.254)

0.050 (1.270)

BSC

1 2 3 4

8 7 6 5

0.250 ± 0.010 (6.350 ± 0.254) 0.400

(10.160) MAX

N8 1291

0.009 - 0.015 (0.229 - 0.381)

0.300 – 0.320 (7.620 – 8.128)

0.325+0.025 –0.015 +0.635 –0.381 8.255

( )

0.045 ± 0.015 (1.143 ± 0.381)

0.100 ± 0.010 (2.540 ± 0.254) 0.065

(1.651) TYP

0.045 – 0.065 (1.143 – 1.651)

0.130 ± 0.005 (3.302 ± 0.127)

0.020 (0.508)

MIN

0.018 ± 0.003 (0.457 ± 0.076)

0.125 (3.175)

MIN

LT1226 SS

1 8

NULL

BIAS 1

3 2 –IN

+IN BIAS 2

4 V^–

7 V⁺

6 OUT

TJ MAX θJA 150°C 130°C/W