A Wafer-Based Monocrystalline Silicon Photovoltaics Road Map: Utilizing Known Technical Improvement Opportunities for
Further Reductions in Manufacturing Costs Alan Goodrich*
, Peter Hacke*
, Qi Wang, Bhushan Sopori, Robert Margolis, Ted James, David Hsu, and Michael Woodhouse*
The National Renewable Energy Lab 1617 Cole Blvd.
Golden, CO USA 80401
Abstract:
In order to understand the current and potential economics for today’s most mature photovoltaic technology, we have engaged in a detailed analysis of manufacturing costs for each node within the wafer-based monocrystalline silicon (c-Si) PV module supply chain. We find that numerous pathways exist for further improvements in efficiency that directly lead to further reductions in cost: After considering some already-known technical improvement opportunities and compiling the associated manufacturing costs for each, we project a conceivable pathway for commercial production modules to have a standard power conversion efficiency of 19 - 23% and to be sold at an ex-factory gate price of $0.60 – 0.70/ WP (DC power, 2011 real U.S. Dollars). As part of that roadmap, we find that the benefit to be contributed by reducing wafer thickness from a standard 180-µm today to the wire sawing limit of 80-µm could be significant—at $0.10 to $0.12/ Wp—with the underlying assumptions that the efficiency will not be compromised and that the challenges in cell processing and module assembly can be overcome (such as maintaining current yields and throughput in commercial-scale production).
We assume that the higher efficiency cell architectures must be built upon a foundation of higher quality wafers, which adds cost at the ingot and wafering step either due to lower yields in production when using dopants other than the standard choice of boron (such as gallium or phosphorous), or in additional capital equipment costs associated with removing problematic boron-oxygen pairs. We derive that the additional price premium for making higher quality wafers by using the alternative dopants is a manageable 10 - 20% above the standard wafer price, and that the price premium for achieving higher lifetimes while retaining boron as the dopant—via the Magnetic
Czochralski approach—could probably be offset due to a higher expected device
efficiency. These adjustments to the wafer price are used within estimates of the future-case price projections for three advanced cell architectures beyond today’s standard c-Si cell and module, and they are incorporated into a final bill of materials for a complete module assembly facility located within the United States.
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This as-received paper is currently in draft form. The results herein are subject to change at any time and without notice to the reader.
1. Introduction:
With average annual growth rates in excess of 40% over the past decade [1-3], the remarkable success of the PV industry can largely be attributed to the steadfast leadership of wafer-based crystalline silicon. This leadership has been sustained by a combination of three critical comparative advantages: (1) industry leading module-area power conversion efficiencies (to date, monocrystalline silicon has maintained the highest power conversion efficiency for any commercial-scale single junction PV module [4]); (2) an established, highly coveted product ‘bankability’ for qualified suppliers (a warranty for 80% of original performance after 25 years of service is now standard [5]); and (3) by a consistent ability to offer price-competitive modules against competing technologies, which has been made possible by an ability to reduce costs throughout the c-Si supply chain.
Historically, most of the cost reductions in the c-Si technology have come about due to ‘economies of scale’ benefits [6]. However, there is a point of diminishing returns when trying to lower costs by simply expanding production capacity. In order to maintain its trajectory of historic cost reductions, innovations that enable higher cell and module efficiencies will be of increasing importance to technology; and while the advanced cell architectures needed to achieve these higher efficiencies require greater initial investment in the capital equipment and starting materials, sufficient gains in efficiency can oftentimes work to offset these added costs. For c-Si there are also multiple pathways to lower costs even further through reductions in the cost of producing the polysilicon feedstock, better silicon utilization in wafer fabrication, and through improvements in industrial cell and module assembly processes.
Another strategic pathway to realizing these cost offsets is through vertical integration. Driven by regional differences in electricity and labor rates, as well as its still quite small scale, the supply chain for c-Si modules has historically been quite disaggregate in that it has been comprised of distinct firms specializing in feedstock, wafers, cells, or modules (see Figure 1). As the PV industry continues to grow, however, vertical integration (and an associated globalization of operations) will play an
intermediate products in-house—a firm is able to gain leverage over the often volatile, market-driven price demands of suppliers.
As a stark illustration, one can consider the effects that polysilicon prices upon manufacturing costs, as this has been one of the most volatile cost inputs for any solar technology. The price for this material went from around $200/ kg in 2007 to highs around $400/ kg in 2008, principally due to the fact that new polysilicon production facilities could not be constructed and qualified quickly enough in order to address the supply-demand imbalances that existed around that time (due, in no small part, to the rapid increase in demand from PV). And while prices did go down from those highs to around $75/ kg in the first quarter of 2011, and then to less than $30/ kg at the beginning of this year, in a game that will be won or lost by pennies-per-watt, the long-term ability of a PV company to more carefully control these costs to a stable level through vertical integration—and by careful coordination of capacity expansions between each of the primary steps—is likely to be one key strategic pathway for sustaining a competitive edge in the future.
Of course, in the quest to grow to the scale that is widely hoped for, the long-term goal for the PV industry is that it must become successful enough in its own right so as to not require continued government subsidies. Arriving at such a point would also help to alleviate the wild swings in supply and demand that have been a defining characteristic for this industry since its conception. But to assess the viability of such a thought, it is necessary to fully understand just how high or low the price for modules (and indeed complete systems) can be without compromising the long-term financial viability of the different players that are involved—including vertically integrated firms that internally
sustainable price for each product within the supply chain—based upon a detailed analysis of all necessary inputs—rather than trying to formulate an answer while only seeing the fair-market values of the day.
In this paper we endeavor to provide a detailed breakdown of the major inputs needed to estimate the current- and full-potential cost and price requirements for c-Si modules. In compiling the analysis with our ‘bottoms-up’ method, we consider the full suite of underlying materials, labor, financing, and capital equipment costs for each step within the supply chain. Assuming all of the inputs for our models are reasonably correct, with this method we are able to provide an insightful comparison between the minimum price needed to sustainably continue PV manufacturing operations and the fair market prices that be gathered from sources such as module and/ or polysilicon price surveys. More importantly, by this same method we can determine how the cost and price requirements for c-Si could evolve over time, after gathering the cost parameters associated with a representative technology ‘roadmap’. We begin with an overview of our cost modeling methodology and a statement of assumptions behind establishing the minimum sustainable prices for each step in the supply chain.
2. Methods
2.1 Methods for Establishing Minimum Sustainable Product Prices and the Costs of Capital Financing
We begin our cost-modeling efforts by establishing a relevant process flow for the manufacturing facility, based upon extensive literature surveys, visits to facilities already in place (when available), and through discussions with company executives and researchers. With the process flows in hand, we then amass the cost-of-ownership considerations for all of the steps. These considerations include the relevant materials and equipment costs; operational cost parameters (including labor content, material yield losses, cycle times, and energy requirements); and the costs of financing the purchase of the land, building, and capital equipment needed to begin production. The labor and
After accounting for the expected throughputs, downtime, etc. for each piece of equipment needed to execute the process flow, the total capital equipment requirements are calculated on the basis of meeting an annual production volume set to meet the full economy-of-scale benefits for that specific step in the supply chain (which we set to be 15,000 metric tonnes per year for polysilicon production, tens of millions of wafers per month in ingots and wafering, and 500 MWp(DC) – 2 GWp(DC) of annual production capacity for cell and module assembly). To represent these costs, the total installed equipment for each step is expensed over its assumed useful lifetime, set by an assumed rate of technology obsolescence. For that, we assign a ten-year, straight-line depreciation schedule for the polysilicon and wafering equipment; a five-year, straight-line schedule for cells; and a seven-year, straight-line schedule for modules. The average annual cost of the manufacturing facility—building only—is also calculated based upon a linear depreciation schedule, with an assumed useful lifetime of 20 years. Dividing the total of these annual depreciation estimates by the targeted annual production volume then provides our depreciation costs on an average per-area or per-watt basis.
Within one section of our Microsoft Excel-based models we set up a pro forma discounted cash flow (DCF) for the manufacturing facility. This DCF is a necessary framework for accurately deriving the minimum product price that a company would need in order to generate enough of a profit to satisfy the required rate of return expected from both debt and equity investors. Because it is a DCF, we are able to incorporate crucial inputs such as inflation and taxes into the derivation process; additionally, it presents the ability to apply the five-, seven-, or ten-year Modified Accelerated Cost Recovery System (MACRS) depreciation schedules on the installed capital equipment (in accordance with the assumed useful lifetimes stated above for each step). With the length of the DCF set by these assumed depreciation schedules, and the discount rate set by the required rate of return, the minimum sustainable product price is then derived by an iterative computational process that runs until the net present value returns a value of zero.
The required rate of return, or ‘cost of capital’, for investors in an enterprise is classically derived from an assessment of the firm’s relative risk (generally measured by a parameter called a ‘beta’) and its capital structure, which includes consideration of both
appropriate values be established for the rates of both debt financing (KD, such as that
provided by banks) and equity financing (KE, such as that provided by stockholders). We
use the global capital assets pricing model (Global CAPM) to derive these rates and then, by weighting them by their relative contribution to the overall capital structure, arrive at a weighted average cost of capital (WACC) [8, 9]:
WACC= MVE BVD+MVE ! " # $ % &KE+ BVD BVD+MVE ! " # $ % &KD(1-T) (1)
Where the ‘leverage ratio’ is the relative amount of debt (i.e., the BVD / (BVD + MVE) term), and T is the corporate income tax rate. This corporate tax rate and
the expected costs for debt and equity financing are naturally dependent upon the country in which the manufacturing takes place. For the sake of brevity, in this paper we limit our scope of WACC (Table 1) and other expected PV manufacturing costs to what would be typical for manufacturing in the United States, where the average effective corporate tax rate is around 28% [10].
If the representative firm is publicly traded, all of the inputs needed for a WACC calculation are updated daily and are available online [11]. (As an important note, we use the long-term beta when estimating KE in the Global CAPM methodology). By surveying
the current financial structure for today’s noteworthy U.S. c-Si players—all of them publicly traded—we estimate that a WACC of around 8.5% is probably typical for manufacturers located in this country. Looking forward, for several reasons the inputs for the WACC will be expected to change over time for the PV industry because, if the costs of PV modules and systems continue to fall—and if utilities widely adopt the technology because they view it to be a sensible substitute for their usual choices—one should expect that the perceived risk and return requirements for investments into PV companies and installation projects will eventually become more similar to that expected from investments in traditional sources for power generation. In Table 1 we lay out our
An additional discussion of how these might vary for a different manufacturing site selection is provided elsewhere [12].
Weighted Average Cost of Capital (WACC) Assumptions Used for Derivations of Minimum Sustainable Prices
2011 Long-Term
BVE BVE+ BVD
0.60 0.70
Levered Cost of Equity (KE) 12% 7.5% Leverage Ratio BVD BVE+ BVD ! " # $ % & 0.40 0.30
Levered Cost of Debt (KD) 4.5% 4.5%
Corporate Tax Rate (T) 28% 28%
WACC 8.6% 6.2%
Table 1. WACC assumptions for U.S. c-Si PV manufacturing. The 2011 WACC
is used for the benchmarking technology cases shown throughout this paper; the mature market WACC assumption will be specified within the figure legends or captions when it is used.
In the following sections we will provide technical summaries of the underlying processing steps and manufacturing costs for each node within the c-Si supply chain. The derived WACC’s are critical inclusions to fully understanding the minimum sustainable prices for each step in the c-Si supply chain because even the vertical integration strategy does not eliminate the need to sell intermediate products with a margin that is commensurate with meeting a required rate of return. That is, a transfer price must be applied to all input materials within the overall supply chain—even when they are transferred within the same company [13].
3. Polysilicon feedstock
3.1 The Siemens Production of Polysilicon Chunk
The very first step in the fabrication of a silicon wafer is the production of metallurgical grade silicon via the high-temperature reduction of silica (typically from lumpy quartz, not sand) with coke and carbon electrodes in an electric arc furnace:
1900 oC
SiO2 + C Si (mg) + CO2
The elemental purity of this metallurgical grade silicon—which currently sells for around $2.50/ kg—is approximately 98%, but the material purity requirement for the most efficient c-Si devices is closer to 9N. The most widely used process for the production of the much more pure polysilicon feedstock material is a chemical vapor deposition (CVD) method called the Siemens process, the sequence of which is shown in Figure 2.
In order to remove the impurities contained within metallurgical grade silicon, the first step in the Siemens CVD process involves, as an overall intermediate, the production and distillation of trichlorosilane (TCS). Facilities that manufacture more than 2,000 metric tons per annum (mTA) of polysilicon generally find it most economical to manufacture their own TCS onsite. The production of extremely pure TCS can be achieved by the oxidation of metallurgical grade silicon with hydrochloric acid at moderate temperatures; most of the impurities that were present within the metallurgical grade Si are then left behind while the TCS is distilled:
300 oC
Si (mg) + 3HCl SiHCl3 (l) + H2
Eventually, solid polysilicon is produced in a batch process as TCS is hydrogenated on the surface of silicon rods placed inside of large bell jars, or ‘Siemens
ingots, but the filaments used within Siemens reactors are much smaller than the ingots used to make wafers and cells). The as-produced filaments of today are typically cropped into a 7 x 7 x 2500 mm elongated square using slurry-based wire saws. The cropped scrap can be remelted in-house for future Cz pulls, while the approximately 10-15% of the filament removed as sawing—or ‘kerf’—loss has essentially no value. As final steps before the CVD chamber is sealed, the filaments are mechanically shaped to fit the electrical contacts made for each rod and the native oxide is etched off using a dilute aqueous HF solution.
Figure 2: Process flow for the production of solar grade silicon feedstock via the Siemens
process.
Electrical current is passed through the resistive silicon filaments until the temperature approaches 1150 o
C. This rather high temperature serves to activate the growth of solid polysilicon, Si (ps), on the surface of these rods as a result of the hydrogenation of TCS with an HCl catalyst. The decomposition of trichlorosilane to produce dichlorosilane (SiH2Cl2) is one of several side reactions that also occur in the course of this process. Fortunately, this intermediate can also react to make polysilicon, and so—even though the TCS stream usually contains 6 to 9% DCS—most polysilicon producers choose not to bother separating the two, which leaves the reaction series to most generally be described as follows [14]:
1150 oC
SiHCl3 (l) + H2 Si (ps) + 3HCl 3SiHCl3 (l) + 3HCl 3SiCl4 + 3H2
4SiHCl3 (l) Si (ps) + 3SiCl4 + 2H2
A typical 300-mTA reactor accommodates 48 rods; the Siemens process is stopped once a diameter of around 125 mm is reached for each. Approximately 125 kg of hydrogen is consumed per hour in a reactor of that size and the process is approximately 20% efficient in its use of the TCS for each pass through the chamber. A total processing time of approximately 60 hours per batch is typical, including a total time of around 24 hours for filament placement, oxide etching, and for harvesting of the rods. As final steps, the silicon rods are smashed into chunks and packaged in nitrogen- or argon-filled containers for shipping.
In order to drive the reaction sequence towards the production of polysilicon, it is helpful to pump off the H2 and SiCl4 as they are produced within the bell jar. Fortunately, these effluents are actually quite useful in that they can be recycled for the production of trichlorosilane that can, of course, be used again in later rounds of polysilicon production. The hydrogenation of silicon tetrachloride, more commonly called the ‘direct
Or the H2 and SiCl4 can be reacted with metallurgical grade Si in the ‘hydrochlorination’ process [14]:
2H2 + 3SiCl4 (l) + Si(mg) 4HSiCl3
Generally speaking, the yields for hydrochlorination are more difficult to control and it is a more technically challenging process. Thus, companies with less experience— but that do want to quickly scale up and establish a presence in this upstream step of the c-Si supply chain—are more likely to achieve success with the direct chlorination approach [15]. The direct chlorination method does, however, require nearly double the capital equipment investment and uses significantly more energy (120 kWh/ kg for direct chlorination versus 70 - 90 kWh/ kg for hydrochlorination). The most well established polysilicon suppliers, many of whom reside within the U.S., employ the hydrochlorination method, while new entrants most typically rely upon direct chlorination.
3.2 Mechanisms and Considerations for the Fluidized Bed Reaction (FBR) Production of Polysilicon
The process of polysilicon production via the ‘Fluidized Bed’ process is an altogether physically different approach than that of the Siemens process [16]. The end product of the FBR process is also quite different in that polysilicon granules ranging in size from 100 to 1500 µm are produced instead of the much larger chunks [17].
A fluidized bed reactor is a cone shaped vessel in which small crystalline silicon seed particles are suspended by an upward-flowing ‘fluidizing’ gas, which is typically hydrogen. By some means the particles must be heated to a temperature that is higher than the decomposition temperature of the reactant gas (commonly SiCl4 or TCS), and—once that is achieved—purified crystalline silicon layers build up layer-upon-layer onto the fluidized beads. Physically, the fluidization of seed particles is based upon the upward drag force of the gases being approximately equal to the downward gravitational pull on the particle, based upon its mass (W = mg). After reaching a size whereby the weight becomes greater than the upward force of the fluidizing gas, the heavier
There are several advantages to this approach in that it is much more efficient in the overall use of the reactant gases; that it does not require the fabrication, shaping, and placement of crystalline seed filaments; and that it requires significantly less energy (only around 10 kWh/ kg). The material form factor of the FBR granules is also quite advantageous in the subsequent step of melting polysilicon because granules can be continuously fed into Cz pullers to bear up to 10 children ingots per initial charge, versus having to reload polysilicon chunk in single batch processing. However, there are numerous technical challenges in qualifying new FBR facilities—in particular in optimizing equipment that can control the heating of the fluidized beads in a controlled manner without losing an important temperature differential between the reaction zone and the walls of the reactor cone [16]—and so there are only a handful of companies that have the capability of providing this material.
3.3 Cost Model Results for Polysilicon Production
In Figure 3 we show our compiled manufacturing cost model results for the two approaches to polysilicon production most commonly employed within the U.S. The depreciation expense is the largest cost in both cases (as the basis for our calculations, our total calculated capital equipment and facilities investment was $74 per kg of capacity for a U.S. hydrochlorination Siemens-based factory, and $71 per kg of capacity for a U.S. hydrochlorination FBR-based factory). The much greater energy intensity for the Siemens route is responsible for the higher contribution of energy costs that can be seen in the figure. Within the U.S., electricity rates as low as $0.025/ kWh (2011 U. S.) are available for industrial customers located in regions near hydroelectric dams, which is the lowest cost method for generating electricity in this country. Not surprisingly, given the large
Figure 3. Model results for polysilicon production costs and minimum
sustainable prices for U. S. based 15,000 mTA production facilities with onsite TCS production. The two most commonly employed methods for U.S. polysilicon production—Siemens production of polysilicon chunk via the hydrochlorination process and FBR granules—are shown, where the minimum sustainable prices were derived from the indicated WACC. The ‘polysilicon’ and ‘saw wire’ components correspond to the Cz pulling and shaping of filaments.
While many analysts believe that polysilicon producers will be forced to lower long-term contract prices to around $20/ kg as early as this year [18], by our estimates price levels much further below this level would not be sustainable. An increased use of the silicon granules produced via the FBR process may offer a long-term ability to lower polysilicon prices to a range approaching the $15/ kg; however, there is widespread belief within the c-Si community that there will be insufficient quantities of this material available—for at least the foreseeable future—to entirely displace polysilicon chunk because the necessary new facilities are not being built at a sufficient rate. And so, despite numerous apparent cost-savings advantages in its production and later utilization in the Cz process, the extent to which the FBR material will contribute to global
contribution to global supplies will likely be limited to around 2% in 2015, 10% in 2020, and 20% in 2030 [19]. After incorporating these estimated FBR contributions, and adjusting minimum sustainable prices in accordance with the mature market WACC, we estimate that the long-term, composite minimum sustainable polysilicon price could be between $16 to $20 per kg (2011 real U.S.) for both U. S. and abroad production locations. Our long-term composite price calculation, based upon the 80/ 20 mix of chunk/ granules, is $17/ kg.
4. The Czochralski Process of Pulling Monocrystalline Silicon Boules, Cropping, and Wafering
4.1 Technical Overview
The next step in the supply chain often takes place in a separate location from feedstock production—even in the case of vertically integrated firms—and consists of melting polysilicon chunk and/ or FBR granules; pulling a Cz boule (or ‘ingot’) from the melt; cropping the crown, tail, and sides of that ingot into a precise shape that minimizes scrap losses; and cross-sectional sawing of the boule into individual wafers. In this section we profile the most widely used processing methods and boule sizes before outlining the cost benefits of changing key wafer product features such as thickness.
The Cz boule casting process has fundamentally changed very little over the past several decades for both the integrated circuit and solar industries. This age-old approach to casting an ingot is carried out by immersing a rotating crystalline silicon seed crystal into molten polysilicon and pulling the seed up from the melt. The seed serves the purpose of providing a template for the growth of a single crystal of silicon throughout the bulk of the boule—set in length and diameter by the rate of the pull, the amount of polysilicon that can be melted in the melting crucible, the temperature gradient within the
The exact size of an as-produced boule has been carefully selected in order to minimize material losses in the subsequent cropping and wafering steps, and after considering the mechanical fidelity of wafers for all steps through module assembly. If producing today’s standard wafer thickness of 180 µm, the typical diameter of an uncropped ingot is 205 mm and the total length is 2159 mm (including the tapered ends of the crown and tail). The final length of a cropped boule is 1729 mm, with a total of 215 mm cut off of the crown and tail, and the cropped boule diameter is 165 mm. From there, the cylindrical shape of the cropped boule is then sawn into the shape of an elongated square brick with rounded corners—a so-called ‘pseudo-square’ shape—by cutting off chords of material down the length of the boule. After accounting for the corner losses, the total cross-sectional area of the brick (and, thus, of the pseudo-square shaped wafers used in cell and module assembly) is currently a standard 237 cm2
with a flat-edge width of 156 mm.
Figure 4. Process flow for standard Cz growth of mono-crystalline silicon ingots
and subsequent wafering. Typical material losses in production are shown on the outside of the processing steps, where the solid scrap generated through sawing of the Boule crown, tail, and chords is recycled for further ingot pulls (at an assumed yield of 100%), but the kerf loss in wafering is not. The given ‘Capex’ numbers within each step refer to the associated initial capital equipment expenses divided by the annual production capacity of the facility.
The bulk scrap that is generated during this shaping process—as well as the scrap generated during the cuts of the crown and tail—is readily remelted during later rounds of ingot casting (after being chunked and etched in order to remove the native oxides). The Si/ SiO2 sawdust material that is also generated, however, is not currently known to be recoverable. This sawdust, or ‘kerf loss’, remains in the form of a very fine powder that is extremely difficult to mechanically separate from the SiC based slurry used during the cutting process. And even if kerf could be fully recovered, one could not simply mix it with the crown, head, and chord scrap because kerf possesses an intractable concentration of chemical contamination when generated by the standard wire sawing process. With the large number of cuts undertaken to produce all of the wafers that can be taken from a completed boule, it is most unfortunate to wafer manufacturers that this kerf loss is generally unusable today as it is the dominant contributor to the net material loss in this step of the supply chain [21].
A wide range of processing options exist to accomplish the cropping and wafering steps: inner and outer diameter saws, diamond-wire saws, band saws, etc. [22, 23]. The diameter of the selected cutting wire directly affects the amount of the boule that is lost as kerf. Currently, for both the standard slurry-based and diamond-wire sawing options, the typical wire diameter of 120 µm produces 140 µm of kerf loss for each cut. Although diamond-wire is initially more expensive than the standard cutting wire, it does have the advantage of having a slower wire degradation rate. More significantly, it may also provide a future pathway for kerf recycling because the chemical contamination is greatly reduced (diamond-wire uses a simple aqueous solution as the cutting fluid rather than the standard wire cutting solution of SiC in a polyethylene glycol slurry) [24]. As a tradeoff, however, diamond-wire cutting may produce a rougher wafer surface laden with micro-cracks [25], which must then be rectified—at an additional cost—during the downstream step of cell processing.
4.2 Cost Analyses of Ingot Casting and Wafering
In Figure 5 we present our aggregated estimates of current and projected costs for producing, cropping, shaping, and wafering monocrystalline silicon ingots. Because a lot of the necessary steps are difficult to automate, a point of note is that a major cost driver for producing wafers is the contribution of labor costs. First, the cropped and shaped bricks must be manually glued to a glass substrate before being placed into the wafering machine. After the brick is cut, the wafers are released from the glass by immersing the entire unit into an aqueous solution designed to dissolve the glue—the result is a stack of thin wafers that adhere to each other by virtue of water’s surface tension. Separating wet wafers from one another, without incurring high mechanical yield losses in handling, requires a level of dexterity that has thus far been best accomplished by human hands. And so, with relatively high labor rates, this cost would be expected to be significant for a U. S. -based wafering facility.
In the figure we carry through our assumption that the increased use of the FBR material could provide a contribution towards enabling sustainable global polysilicon prices around $17/ kg. While it is currently not possible to solely rely upon granules in the Cz pulling of ingots because current equipment configurations require that the larger
Siemens-based chunks be present in the initial material loading and melting steps, its
increased use within this step of the supply chain could enable a measurable decline in the depreciation expense as it enables the effective uptime of the capital equipment to be improved through semi-continuous feeding. If the full potential of 10 children ingots per initial charge could be achieved, we estimate that the associated savings could work out to around $3 per m2
of produced wafers relative to the benchmark case of just one ingot per initial charge when using just polysilicon chunk. A wafering firm would, of course, first have to be able to secure sufficient quantities of the granules in order to realize this savings, and it is entirely possible that this could very well be limited to those c-Si companies that are vertically integrated.
Figure 5. Current and projected costs and minimum sustainable prices (in $/ m2 ) for producing standard wafers via Cz pulling of single crystal silicon ingots and subsequent cropping and wafering. In consideration of the smaller boule diameters needed for thinner wafers, the corresponding changes in wafer area are indicated at the top of the figure. The modeled facility size is set for annual production of 120 million and 480 million wafers in the 2011 and long-term cases, respectively. Waterfall chart to quantify specific cost reduction opportunities (and penalties) for each implemented technology described within the text.
The cost of the wire and slurry that is consumed in the standard cutting process is also significant. In Table 1 we highlight the major costs associated with today’s standard wire approach and the attractive technology of diamond-wire sawing. With the given inputs, and a presumably negligible difference in capital equipment costs, we derive that the diamond-wire approach may enable an overall cost savings of up to 14%, separate from the additional potential benefit of kerf recycling.
Cost of Ownership Inputs for Standard Wire versus Diamond-Wire for Cropping and Wafering Monocrystalline Silicon Ingots
Standard Wire Diamond-Wire
Wire Diameter 120 µm 120 µm
Kerf Loss per Cut 140 µm 140 µm
Cutting Rate (mm/ min) 0.37 1.1
Cutting Fluid and Cost SiC in PEG $1.40/ kg - $2.00/ kg
Water ($ 0.39/ 1000 liters)
Wire Cost $2.80/ km $5.60/ km
Wire Life (cm2 of wafers
produced per m of wire) 80 24
Table 2. Cost of ownership considerations for standard and diamond-wire saw
approaches for the cropping and wafering of monocrystalline silicon boules.
At first thought, the contribution of future wafer costs to module manufacturing should be expected to decline over time as product efficiencies rise and as the wafer thickness is reduced. Indeed it may even seem that this could happen at any time since cell efficiencies greater than 20% have already been demonstrated on extremely thin— less than 50 µm—monocrystalline silicon substrates [26-28]. Once the thickness of a wafer is reduced from the standard 180 µm to 140 µm, however, with today’s understanding of wafer handling the boule diameter (and the final cross-sectional area) of a wire-sawn wafer must be reduced from a standard 205 mm (237 cm2
) to 165 mm (155 cm2
) in order to maintain acceptable yields in wafering, cell processing, and module assembly. This oftentimes leads to a cost penalty associated with thinner wafers— primarily because the kerf loss grows in proportion to the increased number of cuts needed to wafer the longer ingot, because the total yields for all steps in the supply chain might be lower due to more frequent wafer breakages, and due to some additional equipment costs incurred from an effectively lowered throughput in the Cz pullers and in the sawing equipment.
There appears to be a general consensus that the limit in wafer thickness for a sawn wafer is probably around 80 µm, below which mechanical yield losses would ostensibly become unacceptable for currently known and demonstrated sawing and handling techniques [29]. While the guidelines in boule diameter for wafers below 140 µm thickness are less well known, in our projected cost estimates we utilize an underlying assumption that it will become possible to increase the length of ingots as the diameter is reduced in order to utilize the full capacity of the crucible, although this will ultimately depend upon whether new Cz equipment capable of achieving uniform heating across an increased pull-zone length can be demonstrated. We also assume that the cross-sectional area appropriate for a 140-µm wafer is also appropriate for an 80-µm wafer.
There are several approaches that ultimately seek to reduce or eliminate kerf loss altogether. These include ideas such as the epitaxial growth and lift-off of film silicon, cast wafers, laser or ion-based cleaving approaches for wafer separation from a Cz ingot, etc. Each of these approaches would have its own proprietary cost structure and additional considerations for how they would integrate into the overall c-Si supply chain. Without attempting to incorporate all of the specifics for every conceivable approach, our ‘long-term’ or ‘best-case’ wafering cost estimates are based upon a mass balance assumption that the complete elimination—or complete reclamation—of kerf loss can be achieved, but without increases in the equipment-, labor-, materials-, or facilities-related expenses. Assuming this becomes possible at some point in the future, this cost savings could result in an approximately 20% reduction in total wafering costs from the 2011 benchmark.
5. Cells
5.1 The Standard Monocrystalline Silicon Solar Cell Manufacturing Process
In the next step of the supply chain, most c-Si solar cell production is currently based upon a very standardized process designed to make cells with the p-/ n- electrical junction on the entire front surface of the wafer and a full-area, aluminum-based surface field on the back [30]. A representative series of the relevant steps are shown below in Figure 6.
Figure 6. Process flow for the standard screen-printed c-Si solar cell.
First—because wafers are typically received from multiple supply sources and because they can be damaged during sawing and shipping—each individual, as-received wafer must be tested in order to assure that it will yield an acceptable cell at the end. A typical contactless method used today is to measure the lifetimes of minority carriers within the wafer (holes in the case of an n-type wafer, electrons in the case of p-type wafer) via the quasi steady-state photoconductance technique. The usual instrument for this measurement is commonly called a ‘Sinton’ instrument—so named because of the pioneering work of Ron Sinton to develop instruments capable of quickly screening cells for this property [31]. An acceptable, stabilized minority carrier lifetime for wafers intended for use in a standard cell is currently around 20 µs; a higher efficiency cell requires lifetimes more on the order of milliseconds [32, 33]. Assuming that a wafer
1. Test Wafer 2, Saw Damage Removal & Surface Texturization
5. PECVD of SiNx:H 6. Screen Printing:
Front Side Ag Metallization, Al BSF, and Ag rear busbars.
Co Fire Inks. 7. J-V Measurements/Sort 3. POCl3 Diffusion 4. PSG Removal & Edge Isolation 15 - 17% Cells
possesses an acceptable minority carrier lifetime, it is then passed on to the wet chemical processing steps of saw damage removal and surface texturization.
Because the wire sawing process is extremely abrasive, if left untreated the wafer surface would retain a high density of dangling bonds and other defects that would actively serve to accelerate electron-hole recombination in an illuminated cell. The cutting process also introduces microcracks below the surface of the wafer, which severely compromise its resilience to breakage during handling in cell processing [22]. As a first step to ameliorating these problems, an aqueous chemical treatment (typically NaOH or KOH) is utilized to etch away between 5 - 15 µm of saw damage from the top surface of the wafer. With the alkali metal as a spectator ion, the etching reaction proceeds as follows [34]: Si + 2 H2O + OH - HSiO 3 - + 2 H 2 The etch rate of this chemical reaction is different for different crystallographic orientations. These anisotropic differences in etch rates produce a wafer surface with randomly distributed small pyramids having a square base; fortuitously, these pyramids provide the foundation for front-surface light trapping [35]. At the conclusion of this wet bench chemical processing step, the surface recombination velocity will have been reduced by several orders of magnitude and the surface is ready for the formation of the
p-/ n- junction.
In a well-designed solar cell, the internal electric field profile should work to usher the movement of all photogenerated electrons and holes towards their appropriate electrical contacts. This is typically achieved by forming a p-/ n- junction within the most photoactive region. The standard c-Si solar cell is typically made with a boron doped (p-type) base wafer. The formation of the n-doped region—called the emitter—is formed over the entire topside of the wafer as the doping characteristics are inverted from
p- type into n- type by the high-temperature drive-in of phosphorous [36]. In this step the
During cooling the surface of a POCl3 treated wafer becomes glassy and it possesses a higher concentration of carbon, transition metals, and other undesired impurities than the base by virtue of gettering, whereby the impurities aggregate within the phosphosilicate glass (PSG) layer because their solubility is higher in that material. Because this glassy layer makes it is difficult to make a good electrical contact to the bulk silicon, it is necessary to include a processing step for removal of a PSG layer. To do this, an HF dip is typically used for an initial etch, followed by a chemical bath treatment in an aqueous solution of HF, HNO3, and H2SO4. So that only one p-/ n- junction is formed within the solar cell, this chemical treatment is also used to remove the shallow phosphorous diffusion that creeps into the wafer backside, which is still present even though it was only the topside that is ostensibly exposed within the tube furnace [37].
While the random pyramidal surface texture produced from saw damage removal is helpful, the loss in photocurrent from light reflection can be reduced even further by the deposition of an antireflection (AR) coating. As a standard material, hydrogenated silicon nitride (SiNx:H) is able to serve this purpose as it possesses a different index of refraction than that of silicon; additionally, the hydrogen within SiNx:H that is released during a later firing step is able to provide additional surface and bulk electrical passivation beyond the alkaline etch treatment [38-40]. The plasma-enhanced chemical vapor deposition (PECVD) approach is currently the most widely employed method within the PV industry for depositing SiNx:H. In this process, the AR coating is formed during the plasma-activated reaction between silane (SiH4) and ammonia (NH3) gases that are introduced to the PECVD chamber.
The screen printing of Ag and Al pastes for the formation of the front and rear electrical contacts—a consistently more cost effective approach than vacuum-based metallization approaches such as evaporation or sputtering—has been in use by the c-Si industrial community since as early as 1975 [41]. In this process, a conveyer belt moves c-Si wafers along a queue where they are picked up (either by a robotic or human arm) and placed onto a printing table. An H-pattern screen mounted in an aluminum frame is overlain on the frontside of the cell and the metallization paste is squeegeed over the wafer surface with a defined pressure. This handling and printing process can be repeated at an impressive net rate of 2 to 3 seconds per wafer in today’s screen printers,
wafers are moved into a drying furnace. Lead borosilicate glass frit (PbO-B2O3-SiO2) within the Ag paste then etches through the SiNx:H layer during this firing process in order to form a direct electrical contact with the underlying emitter region, and the wafer is then moved on to the next table for printing of the rear side Al paste.
The specific choice of Al for the backside metal is a strategic one. After driving off the binders within the paste, this metal is known to produce a back surface field (BSF) within a standard cell by establishing a more heavily doped (p+
) region near the Al-Si interface [42, 43]. This Al BSF creates a potential energy barrier for electron-hole recombination on the standard wafer back surface, as well as providing a driving force for injection of (ground-state) minority carrier electrons back into the device. An Al backside can also provide a benefit—albeit not as great as some other options used in more advanced cell architectures—as a reflector of light off of the back surface [30].
A final screen-printing of Ag or Al/Ag busbars, later soldered to tabbing ribbons in the series interconnection of cells into modules, completes the screen-printing steps. At the end of all three of the printing steps, the entire standard cell assembly is typically fired at around 750 o
C in order to drive off the undesired additives used to make the metal paste [44].
The final step in the standard processing approach is to test the current-voltage (J -V) characteristics of each cell that is produced on the line. They are binned according to their current density at maximum power point in order to minimize mismatch losses between cells when they are series-connected within modules.
5.2 Introduction of Potential Pathways to Improve Efficiencies beyond the Standard c-Si Cell
While the standard approach to cell processing has been the dominant manufacturing strategy for quite some time, it is increasingly clear that—in order to remain competitive within the future landscape of PV—it will become necessary to lower costs even further. For all steps within the c-Si supply chain, as well as at the installed
€
η =Maximum Possible Powerout
PowerIn = FF × Jsc× Voc AM1.5(λ)dλ λmin λmax
∫
=FF × Jsc× Voc 1000W/m2not be able to deliver the 20 - 25% power conversion efficiency that other industrially-relevant devices are capable of delivering [45].
To define this all-important consideration, the efficiency of a solar cell is broadly calculated as follows:
(9)
Where AM 1.5 represents a modeled profile of the expected number of photons for each wavelength within the solar spectrum after it passes through the earth’s atmosphere (by specifying an idealized atmospheric condition—and at a specified latitude and angle of incidence—the total integrated energy content of this solar profile can be set to 1 kW/ m2
); and the FF, Jsc, and Voc represent the respective efficiency parameters of fill factor (unitless), short-circuit current (in A/ m2
or mA/ cm2
), and open-circuit voltage (in Volts). For c-Si, in consideration of the absorption profile of the semiconductor in comparison to the AM 1.5 spectrum (as well as the factors that limit the Voc and FF), the maximum theoretical power conversion efficiency limit is around 29.8% for a 100-µm wafer [46].
To a first-order approximation—that is, assuming ideal diode behavior and superposition—the Voc can be estimated by equation 10, where n, k, T, and q are constants at a fixed temperature [42]:
(10)
As equation 10 shows, maximizing the Voc implies maximizing the Jsc while also minimizing J0. This Jo parameter, called the saturation or recombination current density, is a broad representation of the overall net rate of electron-hole recombination within a solar cell, meaning that reducing recombination is absolutely critical to improving the Voc. While the theoretical limits for the J0 and Voc in a c-Si cell are estimated to be around 0.27 fA/ cm2
and 0.845 V [45], there exists a seemingly inexhaustible list of sources for Voc ≈ nkT q ln Jsc J0 " # $ % & '
€
Jsc= QE(λ) λmin λmax
∫
× AM1.5(λ)dλradiative, conduction-band to valence-band (Auger) recombination; Shockley-Read-Hall (SRH) recombination on the front, edge, and back surface of the wafer; defect mediated—again SRH—recombination in the bulk; metal-to-silicon contact recombination; p-/ n- junction (or ‘depletion layer’) recombination, and the list goes on. The Auger recombination term defines the lower limit to the J0 because—at the thermodynamic limit of a perfect detailed balance—the rate of electron-hole pairs being put back into the solar cell must equal the rate that is generated by light absorption [46]. As for the other, non-radiative sources of recombination, there are a multitude of potential remedies that are commonly recognized and we introduce some of them within Table 3.
By calling upon the same underlying assumptions used to derive the open-circuit voltage expression, we are also able to simplify our discussion of the short-circuit current to the following [42]:
(11)
Where the term QE(λ), called the external quantum efficiency, is the probability of harvesting a particular photon of incident light with a given wavelength. The maximum possible current (i.e., at short-circuit conditions) of a solar cell and module can then be derived by integrating these probabilities over the AM 1.5 spectrum.
To improve the probability that the desired photon-to-current conversion process will occur, there are several considerations that need to be addressed: (1) the absorption profile and thickness of the absorber layer must be sufficient for the full harvesting of sunlight; (2) from the moment of light absorption to the final collection of current at the metal contacts, problems of electron-hole recombination must be overcome within the bulk material and at every interface (again, this is also important for parallel gains in voltage and fill factor); and (3) reflection and parasitic absorption losses need to be minimized. There are some very architecture-specific causes for the observed losses in
Table 3. Overview of some of the technical improvement opportunities—
organized by Technology Groups 1, 2, and HIT—that are available to improve the efficiencyof c-Si cells and modules. Taken in isolation, the projected improvement for each cell parameter is a minimum for each item (see text for an overview). In the calculation of module efficiencies, which are shown in parentheses at the bottom of the table, the assumed cell-to-module derate is 89%.
Cell Performance Parameters Standard c-Si (2011) Technology Group 1 (p-type wafer) Technology Group 2 (n-type wafer) HIT (n-type wafer) Short-Circuit Current Density: JSC (mA/cm2) 34 38 41 40 • Backside optical mirror [47] • Higher aspect ratio front gridlines [48] • Buried front metal contacts[49] • Selectively diffused emitter junctions [34]
• Reduce front-side shadowing losses by moving contacts to the back [50]
• Improved light trapping through novel surface texturing and higher internal light reflection [51, 52]
• Lightly doped FSF [53] • SiO2 passivation[53]
• Develop a TCO with reduced free-carrier absorption [45, 54] • Develop a
heterojunction window layer with reduced absorption [54] Open-Circuit Voltage: VOC (V/cell) 0.60 0.70 0.74 0.75 [55] • Selectively diffused emitter junctions [34] • Improve wafer quality: Alternative dopants or magnetic Cz [56-58]
• Improve surface and bulk passivation [50, 59] • Reduce resistive (I2 R) losses without compromising optical losses by covering more solar cell area in a back-contact scheme [45] • Ion Implantation [60-62]
• Use tightly focused Si-metal contacts to reduce contact recombination losses [63, 64]
• Use n-type wafers with ≈10 ms minority carrier lifetimes [32]
• Use n-type wafers with ms minority carrier lifetimes [32] • a-Si:H/ c-Si heterojunction surface passivation [65] • Use a TCO for charge-carrier transport and anti-reflection coating, and develop a new one with a higher electrical conductivity [66] Fill Factor: FF (%) 78 80 82 80 • Improve conductivity (σ) through electroplating [67] • Develop and improve new metal and selective emitter paste
chemistries [68, 69] • Selectively diffused emitter junctions [34]
• Improve back, front, and edge surface passivation
• Use n-type wafers with ms minority carrier lifetimes [32] • a-Si heterojunction surface passivation [45]
• Develop new TCO [66] AM 1.5 Power Conversion Efficiency (%): 16% Cells (14.5% modules) 20 - 22% [70-72] (18.7%) 25% [73] (22.4%) 24% [74, 75] (21.4%)
In organizing Table 3 we have attempted to compile the major technical improvement opportunities we have researched into completed hypothetical cells called ‘Technology Group 1’, ‘Technology Group 2’ (or ‘IBC’), and ‘HIT’. It needs to be stated up front that these cells—and the following processing flows associated with each—were explicitly designed for cost-modeling purposes only and have not necessarily been fully commercially demonstrated. Nonetheless, they do appear to be reasonable cell architectures, industrially relevant process flows, and efficiency projections based upon an exhaustive literature survey and innumerable conversations we have had with experienced players within the c-Si community. The first difference between these technology groups is in the choice of base doping within the wafer: p-type for Group 1, and n-type for Group 2 and HIT. Other key differences can also be noted within the table.
5.2 Technology Group 1:
Front-side metallization on a p-type Cz wafer (20 – 22% cell efficiency)
5.2.1 Front metal contact buried into the wafer with a locally diffused emitter
The highest efficiency c-Si solar cell to date, at 25% [76], is based upon an architecture called the Passivated Emitter Rear Locally-diffused, or PERL, cell. This architecture is designed in such way that the electrical connection between the front-side
n++ emitter region (e.g. selective emitter paste or
H3PO4 Diffusion) SiNx
Al BSF
Front Electrode Stack: • Electroless Ni • Electroplated Cu alloy
Front Passivation Layer (e.g. SiO2) High lifetime p-type base
Backside Mirror & Passivation Layer
(SiC, SiO2, or SiNx)
Ag Busbars
Point contacts between Si and Al BSF
exactly, several of its underlying concepts are clearly appearing within many of the new equipment designs and industrial research and development programs [71, 77]. Because this cell is also based upon a p-type base, making it quite amenable to the standard industrial cell processing approaches already in place, we have chosen to model an industrially scalable derivative of the PERL cell.
While not the only contributor to the high efficiency, the PERL concept incorporates the idea of a heavily doped emitter region that is narrowly focused at the point of contact between Si and the frontside metal, in addition to a lightly doped region over the entire wafer front surface. Today this design is more commonly called a ‘selective’ emitter rather than a ‘locally diffused’ emitter. There are several advantages to this design over the standard cell, primarily in the business of optimizing the electrical connection between the front metal and the silicon without creating unnecessarily high rates of recombination over the unmetallized regions of the wafer’s front surface [36, 78]. This is achieved by creating two different levels of doping density within the cell:
n doping (with carrier concentrations, Nd, on the order of 1019 cm-3
) over the entire wafer front surface with something such as a light POCl3 diffusion; and n+
doping (Nd ≈ 10
20 cm-3
) directly at the point of contact between the metal and the emitter. In principle, this should make it possible to establish an electric field within the device that will properly usher the photogenerated electrons and holes towards their appropriate electrodes while also greatly reducing the recombination associated with moving them from the silicon into the metals [79]. The use of POCl3 also retains the benefit of impurity gettering. The overall expected result when employing such a design is a lowered value in the overall J0 (and a correspondingly higher Voc), as well as a slight benefit to the Jsc of the cell due to a higher quantum efficiency of blue photons [34, 80].
There are a variety of manufacturing processes already in place or being developed that could quite conceivably deliver cells of this type. Of particular interest are the industrially-relevant methods for the formation of the n+
region: the options of either screen-printing dopant pastes [69, 80], or using a laser-assisted doping of the wafer from a stream of H3PO4 [81, 82], are two interesting processes that appear to be amenable to incorporation within a standard c-Si cell processing line. As for how that might work, we have incorporated both options within a step of a cost model designed around the
hypothetical process flow for an industrially scalable derivative of the PERL cell (Figure 8).
In this process flow it is postulated that the standard processing steps of 1 -5 would be retained. Steps 1 – 4 could be used for establishment of the light n doping of the wafer surface. The incorporation of SiNx:H on the front (step 5) is envisioned to still be beneficial as an anti-reflection coating and for mitigating Jo due to front-surface recombination [38, 45].
We postulate than an appropriate next step might be to carry out a laser ablation in order to make the laser buried emitter-to-metal contact. In this step, a laser is focused onto the wafer to create localized heating well above the melting temperature of silicon (1410 o
C) and silicon nitride (1900 o
C) within a very short time (ns) by a focused laser pulsed at around 30 kHz frequency repetition rates [81, 83]. Molten silicon nitride and silicon is ejected from the wafer by the laser, leaving a very precisely aligned groove in its path. The ablation process does create a thin layer of damage on the wall of the groove that must be removed with something like an NaOH etch as, if left untreated, dislocations generated by the lasers in the local crystal structure will glide into the bulk during subsequent thermal processing steps. We have included this as step 7.
1. Test Wafer 2. Saw Damage Removal & Surface Texturization
20 - 22% 9. Light-induced plating of Cu on Ni seed 3. In-Line POCl3 10. PECVD of Backside Mirror and Backside Surface Passivation stack
(SiC, SiO2, and/ or SiNx)
8. Laser-induced local diffusion of n++ emitter.
Selective emitter paste or aqueous doping. 13. J-V measurements/ sort 5. PECVD of SiNx 12. Screen Print Al BSF and Ag Busbars. Cofire. 4. PSG removal 6. Laser Grooves 7. Laser damage removal
11. Laser opening of dielectric for ohmic
We see the laser groove as being quite advantageous to both the dopant paste and aqueous-based approaches to emitter drive-in, primarily because it establishes a pathway to higher aspect ratio grid lines on the front of the cell (a benefit we take up next). The reader should note that steps 6 and 8 would likely require separate lasers.
5.2.2 Moving from screen-printing to electroplating for front-side metallization
For the most part there appears to be little rush to replace the standard screen-printing of Ag as it is a proven, high throughput technology with good alignment control and low wafer breakage rates. However, there are multiple beliefs for why this approach to frontside metallization is ultimately unsustainable.
One reason that is commonly expressed is that—at some point—the c-Si technology will eventually become a victim of its own success in that the demand for Ag from it alone will drive its price to an unacceptably high level. Without confirming or denying that particular line of conjecture, we don’t foresee the need to cling to the standard Ag screen-printing approach anyway because there are more elegant approaches to metallization that can deliver much finer line widths, are already industrially scalable, and that can be based upon much cheaper metals.
The next step of our modeled process flow incorporates the light-induced plating approach to deposit a copper grid on top of an electroless seed of nickel [49, 84, 85]. This metal layer stack could conceivably move c-Si cells away from the full screen-printing of silver and towards the much more sensible, long-term alternative of Cu metallization. Even if this choice is developed, as it already has been within the integrated circuits industry, we have included an additional step of a Ni barrier/ seed in the process to be but one example of a material that will likely be needed to prevent the diffusion of Cu into the cell—which is detrimental to the reliability [86]—and to also serve as an electrical channel for the electrodeposition of Cu from solution.
In the first step of this approach, a very narrow seed layer around 5 µm in width (much thinner than the usual full Ag line widths of 160 µm) would be deposited in the trenches via screen-printing, ink jet printing, or aerosol printing [48, 67] (note: our cost model results are based upon screen-printing of the barrier layer). The light induced
with the same metal (Ni in our model) or, if need be, with a different metal (Cu in our model). The very elegant LID plating process is driven by employing the photovoltaic effect for a cell immersed in an electroplating bath [70, 71]: After applying the necessary reduction potential and exposing the cell to light, the photogenerated electrons flow to the surface and then into metal ions within the surrounding solution. The plating process then proceeds until the desired line conductivity (cross-sectional area) is reached [87].
This light-induced plating process has been used for quite some time in several higher efficiency cell designs because it has demonstrated an absolute efficiency improvement of at least 0.3 – 0.5% over screen printing [88]. One of the main contributors to the efficiency improvement has been that this approach to metallization can produce much thinner completed line widths around 30 - 50 µm [67, 71, 88]. This is advantageous in reducing losses to the Jsc due to shadowing and reflection of light from the frontside metal; but using thinner line widths does require either a higher density of grid lines on the wafer surface, or lines with a higher aspect ratio, in order to limit resistive losses and to move the same amount of photocurrent that the thicker, screen-printed lines can. It is on this point that the laser groove beautifully serves another purpose: Controlled by the trench depth and width, the metal aspect ratio can be moved from around 1:4 to 1:2 [71], and the line conductivity can be improved while also reducing the amount of total dead area on the cell [70]. As final notes for why we have chosen to include the replacement of screen-printing with a laser-buried groove in our Technology Group 1 cells, this concept has also been shown to reduce the area-dependent contact recombination losses between metals and silicon [67], and moving away from the dielectric glass frit that is contained within Ag paste should also lead to lower overall series resistance losses within the grid array [68].
