edp70

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TECHNICAL MANUAL

PART NUMBER 10B52041PT1C rev. 5

EDP70

UNINTERRUPTIBLE POWER

SYSTEM

TECHNICAL HANDBOOK

The copyright of this handbook is the property of Chloride Power Electronics Limited.

The information contained herein may not be copied, communicated to a third person nor stored in a data retrieval system without agreement in writing from Chloride Power Electronics Limited.

In pursuing a policy of continuous product development we reserve the right to vary product design, specification or components without prior notice.

Whilst every effort has been made to ensure the accuracy of the information in this handbook, Chloride Group PLC cannot be made liable for any errors, incidental or consequential damages.

This manual includes:

– the description of the software used up to FSB = 29

and the one used from

FSB = 30

CHLORIDE

SILECTRON

Via Umbria, 6 I – 40060 Osteria Grande BO ITALY Tel. (++39) (+51) 6959111 Fax. (++39) (+51) 945634

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The control logic, which is traditionally supplied by low voltage, has low power part of this type of equipment powered by 5V and +12V logic power supplies which are referenced to potentials other than earth zero volts so that high voltages with respect to earth exist on some circuit boards in the equipment. With all supplies isolated the battery (288V or 396V DC) is still live and appropriate precautions must be taken.

1.2 Electric Shock

Switch off the supply or use dry insulating material to protect yourself while pulling the casualty clear of any conductor.

DO NOT TOUCH THE CASUALTY WITH YOUR BARE

HANDS UNTIL HE IS CLEAR OF ANY CONDUCTOR.

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Chap 1 = SAFETY

1.3 Safety Warning

1) If either the AC supply or the batteries are connected, do not remove the access covers unless you have undergone a Chloride approved training course.

2) Arrange safety cover. Ensure somebody is available to isolate the electricity supply if necessary.

3) Stand on an approved rubber insulating mat when working on the equipment.

WARNING ! : Some rubber mats contain a carbon based pigment and are not suitable!

4) Remove watches, rings earrings and other metal jewellers and any loose metal pens, tools or metal objects from pockets before working on the equipment. 5) Do not touch printed circuit boards, except in ’Bypass’ mode. High voltages

exist, there is an electric shock hazard. 6) Use only insulated tools.

7) Batteries contain ACID, which is poisonous and corrosive. It can cause burns on contact with skin and eyes. If acid is spilt on clothes or gets into eyes, wash well with plenty of clean water.

Batteries can give off EXPLOSIVE gases. Keep sparks, flames and lighted cigarettes away.

Batteries are ELECTRICALLY LIVE at all times.

Even if the case is damaged they are still capable of supplying high short circuit currents.

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Chap 2 = MAINTENANCE PROCEDURES

2 MAINTENANCE PROCEDURES

2.1 Tools and Test Equipment

In addition to the usual hand tools, the following equipment is needed:– 1) Oscilloscope. Dual beam, at least 15MHz band width.

This should be a fully floating earth type because it will be used to measure signals with reference to potentials other than earth.

2) Digital multimeter. This must be accurately calibrated. 3) A fused in–line wire link with adaptor.

4) Protective insertion and removal tools for handling CMOS integrated circuits which are susceptible damage from incorrect handling.

2.2 Procedures

When troubleshooting in this equipment remember that high voltages exist on printed circuit boards and on exposed terminals. Therefore do not touch any component until you have checked it is safe.

When monitoring test points, always switch to BYPASS mode to fit the probe or meter, then switch to an operating mode to make the observation. Finally return to BYPASS to remove the measuring instrument. This will avoid inadvertent fuse blowing from spurious signals.

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Chap 2 = MAINTENANCE PROCEDURES

2.3 Fuse Blowing

NOTE ! The machines are equipped by circuit breakers only. No fuses are fitted as reliance is placed on the installation.

1) Switch to bypass mode. Wait 3 minutes.

2) Check all the switches, excepted By–Pass, are OFF, and remove the battery fuse.

3) Use a multimeter to check all the power components in the inverter including snubbers, power transformer and filter circuits (refer to section 3 of manual). 4) When power components are verified, disconnect base drive (plugs PL10–13) 5) Turn on main switch. Verify DC rail voltage, and that the control and drive logic

is working correctly (refer to section 5 of manual). 6) Switch off main switch. Wait 3 minutes.

7) Refit battery fuse F2 and base drive connectors. If F2 was faulty replace it.

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Chap 2 = MAINTENANCE PROCEDURES

2.4 Fans replacement

Driver board

holes for Driver board

1 – Remove the Driver following the arrow 2 – Unscrew the fan’s support screw

3 – Remove the fan following the arrow Fan support

fixing’s screw

Procedure for fans replacement

on UPS ratings 30 or 40 kVA

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Chap 3 = POWER ASSEMBLY DESCRIPTION

3 POWER ASSEMBLY DESCRIPTION

The UPS described here is a machine which guarantees uninterrupted power supply to the load both with or without the primary supply voltage, even when handling the most rigorous and sophisticated load.

Therefore this system is used as an interface between the mains supply and users requiring an uninterrupted energy source.

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Chap 3 = POWER ASSEMBLY DESCRIPTION

BATTERY CHARGER–RECTIFIER

The rectifier converts the mains ac voltage into DC voltage in order to feed the inverter and the battery.

INVERTER

The inverter transforms the DC voltage supplied by the rectifier, or the battery into ac voltage for feeding the load.

STATIC CHANGEOVER SWITCH UNIT

The static changeover switch transfers the power supply to the load, without any loss of continuity, from the inverter to the reserve supply and viceversa every time the power supply characteristics stray beyond the tolerances accepted by the load. Essentially, the static changeover switch is composed of:

a) an inverter static switch comprising 3 pairs of thyristors connected in anti–parallel in the inverter output.

b) a reserve static switch comprising 3 pairs of thyristors connected in antiparallel in the reserve line.

c) Logic control and command which carries out the following functions: – driving the thyristors of one of the static switches, according to the logic

described below.

– checking the reserve and inhibiting the reserve static switch if the latter strays beyond the parameters permitted by the load.

– checking the inverter output, ordering the load to be transferred onto the reserve network when the latter is beyond the parameters permitted by the load, or when the current required by the load persists in exceeding the maximum value permitted by the inverter.

Under normal working conditions the static changeover switch supplies the load from inverter output (privileged power source).

If an anomaly occurs, fast sensors order the load to be switched over to reserve, if this is necessary.

A short circuit in the output of the unit automatically causes the load to be switched over to reserve; if the latter is not available, or is unsuitable. the unit protects itself and guarantees correct supply to the load only if the short circuit is eliminated by fuses of a size sufficient to effect correct selection of the protection systems.

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Chap 3 = POWER ASSEMBLY DESCRIPTION

Power Assembly description:

The EDP70 comprises the following main assemblies:

1) Input Choke / Input Autotransformer L1 / AT1 2) Rectifier Module

3) DC Choke L2

4) DC Smoothing Capacitors CE 5) Inverter Module,

Inverter Transformer T2, AC choke (not needed if integrated

magnetics fitted.),

Filter Capacitor C2

6) Static Switch Module 7) Display Module

3.1 Input Choke / Input Autotransformer

These devices make a separation of the main supply from the distortion generated by the rectifier.

The autotransformer, fitted on the rating up to 20kVA only, adapts the voltage level.

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Chap 3 = POWER ASSEMBLY DESCRIPTION

3.2 Rectifier Assembly

In a three phase system the rectifier is a fullwave phase controlled bridge utilizing 6 thyristors. This assembly converts the AC power into voltage regulated DC power. Regulation is accomplished by controlling the conduction angle of the thyristors.

This function is controlled by the rectifier control board which samples the actual DC output via an isolation amplifier on the interface pcb, compares it with a reference to determine the error and adjusts the duration of the thyristor ’ON’ periods to attain the correct DC voltage.

The battery current is sensed by a hall effect current transformer. This is used to limit battery current and monitors discharge.

Rectifier control board (See also section 4.1), also produces the gate drive pulse via the interface pcb to turn on the 6 thyristors.

3.3 DC Choke

The choke L2, fitted on the rating up to 20kVA only, in conjunction with capacitor CE forms a low–pass filter circuit. On the ratings above 20kVA this is done by the AC choke L1.

This provides the voltage smoothing and current ripple reduction on the DC supply which is necessary to ensure correct operation of the inverter.

The current to the battery is smoothed again by the saturable choke L3, assuring then a trouble free battery charging.

3.4 DC Capacitor

A bank of electrolytic capacitors CE in conjunction with the DC choke form a filter as above described.

Resistors in the inverter bridge are fitted across the bank to ensure safe discharge of these capacitors when the UPS is OFF (allow 3 minutes for discharge).

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Chap 3 = POWER ASSEMBLY DESCRIPTION

3.5 Inverter Assembly

The power AC waveform is constructed by pulsing chopped DC through the primary of transformer T2.

The induced waveform in the secondary is an AC voltage at the inverter frequency 50 or 60Hz but superimposed on top of this are AC voltages at higher frequencies, giving a slight ripple. This ripple is attenuated by C2. The chopped DC waveform is generated using pulse width modulation. The sample of inverter output is compared with a synthesized waveform. An error amplifier ”closes” the loop giving a full servo controlled system. The chopping frequency across the primary is 64 times the output frequency.

i.e 50 x 64 = 3200Hz (for 50Hz output).

Six power darlington transistors are configured around the primary winding of the inverter transformer in such a way that the current DC bus may be pulsed through the inverter primary in either direction by turning on the appropriate pair of these solid state switches.

Each switch is turned on by current applied to the bases. Rapid turn off is ensured by the control logic negatively biasing both bases to drain away the charge stored in the transistor junction.

The inverter pcb generates the inverter drive signals and the signals to levels suitable for driving power transistors. A switch mode power supply is used to derive a regulated logic power supply from the DC bus. This allows the inverter to be started whenever the DC bus is live without needing the rectifier to be on (during a power failure for instance).

3.6 Static Switch Assembly

The static switch is a make–before–break changeover switch which has no moving parts. It uses thyristors as the power switching elements, triggering by signals from the static switch control board.

The control logic is configured such that normally it connects the inverter to load but in the event of an overload or malfunction, it can transfer the load to the reserve supply without interruption. In order to avoid phase jumps or reversals the inverter is synchronized and phase locked to the reserve.

3.7 Display Assembly

This assembly drives the front panel displays, the audible alarm remote alarm unit, RS232 and AS400 alarm interfaces.

This pcb also monitors the state of the system, performs some control, logic and display functions.

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4.1 = Rectifier Control Pcb

4 CONTROL LOGIC DESCRIPTIONS

4.1 Rectifier Control Pcb

Refer to circuit diagram 04.11.240 become 15C90073

This circuit converts a 3 phase input supply to a stabilized D.C. rail. Achieved using a 6 pulse controlled rectifier.

Power Circuit:

The three–phase AC main, through a high reactance star connected auto–transformer or an AC choke, supplies a fully controlled 3 phase thyristor rectifier. The DC filter choke and the integrated AC chokes have been optimized to reduce harmonic distortion of the input current waveform. Isolated current feedback is derived from a hall effect current sensor in the battery lead. Voltage feedback is derived via impedance buffer amplifiers assuring electrical isolation > 300 kΩ.

Control Circuit:

The main functions of the control circuit are:

– Provide firing pulses for the thyristor bridge giving a regulated DC rail, – Battery current limited to values from 1.5 to 30A (selectable)

– Firing pulses inhibited under the following conditions:– – REMOTE SHUTDOWN facility activated,

– INCORRECT connection of input supply (PHASE ROTATION error), – PHASE FAIL.

– Battery test facility, reducing the rectifier output voltage by 20%, – Soft start ensures D.C. rail ramps up over a period of 10 seconds.

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4.1 = Rectifier Control Pcb

Power Supply:

This is derived from the primary of the main three phase autotransformer via T6, T7 and T9 (mounted on the Transformers board and connected in star configuration). The transformer secondaries are fed into a full wave rectifier circuit formed by diodes D4 to D9. This provides an unregulated DC rail smoothed by C4. REG1 is a 5V regulator used to power all subsequent circuits. C5 decouples the output of REG1.

Firing Angle Generation:

The 3 phase input sample is taken from the secondaries of T6, T7 and T9 (mounted on the Transformers board) attenuated and put on a 2.45V level. The reduced signals are fed into 3 crossing detectors (IC1a, b & c), each detector compares two of the waveforms. The outputs of each of these is a square wave corresponding to the cross over of two of the phases (See Fig 1). The phase crossing square waves are then applied to 3 EXOR gates (IC 6), again each gate compares two of the signals. The resultant pulses correspond to the required firing ranges.

The EXOR gates have open collector outputs which when activated provide a discharge path for a 100nF capacitor (C6, C7 & C8). With output deactivated the capacitor is allowed to charge through a 100K resistor (R35, R38 & R45). The time constant of the RC is much greater than the firing range pulse thus a ramp generator is formed.

Ramp signals are fed into a further three comparators (IC2 a, b, c) together with a common demand signal resulting in an output pulse with width proportional to the demand signal and in the correct time slot. These pulses are fed into a custom logic array which steers them to the appropriate gate drive circuit. Figure 2 shows some of the outputs for firing angle less than 60 degrees. Figure 3 shows the outputs for a firing angle greater than 60 degrees.

The isolated gate drive circuits are positioned on the interface board. At the heart of these circuits are optically isolated triacs. Resistors R59 to R64 set the drive current for the opto–triacs to 10mA.

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4.1 = Rectifier Control Pcb

R R Line to neutral Voltages Y B R>Y Y>B B>R Zero Crossing Detectors Firing Ranges OP’s from Ramp Generators Firing Pulses for ”B” input of Logic Array R>Y XOR B>R

Y>B XOR R>Y

B>R XOR Y>B Voltage Demand Y B Fig. 1

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4.1 = Rectifier Control Pcb

R G1 : Pin 19 G2 : Pin 18 G3: Pin 17 G4: Pin 16 Y B Firing Pulse for G2 Output of Logic Array Fig. 2

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4.1 = Rectifier Control Pcb

R G1: Pin 19 G2:pin 18 G3: Pin 17 G4: Pin 16 Y B Firing Pulse for G2 Output of Logic Array Fig. 3

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4.1 = Rectifier Control Pcb

Voltage Control Loop:

Voltage feedback is via a high impedance buffer amplifier on the interface PCB. The voltage feedback signal is scaled to 2.2V at nominal output voltage, and fed into the non–inverting input of IC3d configured as a frequency compensated error amplifier comparing the feedback signal with a reference set by VR1. An increase in the output reduces the DC rail voltage.

Soft Start:

This circuit ensures that at switch on the DC rail ramps up slowly over a period of approximately 10 seconds.

The circuit, formed round IC3c acts as a virtual capacitor exhibiting an equivalent capacitance 100 times that of C3 at the junction of R14 and R15. At switch on the virtual capacitor charges through R15 to the 2.45V reference level which is buffered to the output of IC3 suppling the voltage reference pot VR1.

Battery Test:

To test the batteries the DC voltage is reduced by 20%.

This test is initiated by the microprocessor controlled display driver PCB. Under test conditions PL6/12 is pulled low causing the output of IC4a to change state connecting R17 to 0v forming a potential divider with R26 which reduces the reference voltage seen by the virtual capacitor circuit.

Charge is taken out of C3 reducing the voltage across VR1 and hence the reference to the voltage feedback amplifier.

When PL6/12 is released R17 is switched out and the charge on C3 increases, the output voltage ramps up to the nominal level.

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4.1 = Rectifier Control Pcb

Current Limit:

This circuit, which is built around IC3b, limits the battery charge current to values from 1.5A to 30A, depending on the status of SW1 (see table on schematic diagram).

Working like the battery test by reducing the charge on C3.

IC3b forms a frequency compensated error amplifier. The non–inverting input is connected to a reference. Current–feedback signal is connected to the inverting input, if it is higher than the reference level the output of the amplifier goes low rapidly discharging the virtual capacitor circuit via D1 and R11. When the current limit is released the output voltage again ramps up slowly.

Trips and inhibit:

Pin 8 of the custom logic array is configured as an active low inhibit input, it is also connected via an inverter (IC6d) to the gate of FT1. With the inhibit line low, FT1 is switched on discharging C3 resetting the soft start.

The inhibit line can be pulled low by any one of the following trips:

– Rectifier Shutdown:

This operates when PL6/13 is pulled low, it is connected to a simple comparator circuit which switches low inhibiting the system. This function is controlled directly from:

– the display control board

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4.1 = Rectifier Control Pcb

– Phase Fail/Rotation:

This circuit ensures that the 3 phase supply has been correctly wired or if there has been a phase failure.

An unbalanced star load is connected across the supply sample (R48, R49, R50 and C8). Under normal conditions an AC signal appears at the star point of the load. This signal is rectified and smoothed by D10 and C10. The smoothed level is attenuated by R51 and R52 and fed into the non–inverting input of comparator IC1d. The inverting input is connected to a 2.75 reference level. Under fault conditions the signal at the star point reduces causing the voltage at the non–inverting of IC1d below 2.75V which switches the output low setting the inhibit line low via the rectifier shutdown comparator.

Temperature Compensation:

A temperature sensor (IC7) provides temperature compensation in the feedback loop. It is designed so that the output voltage of the system is reduced as the temperature rises.

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4.2 = Inverter Drive Board

4.2 Inverter Drive board

Refer to circuit diagram 15C70512

4.2.1 Frequency generation:

The frequency generator uses a crystal QZ1, and pins 9 and 12 of IC17. These together generate a frequency of 2.4576 MHz which is fed into IC17 pin 1 as a clock. The output of IC17 pin 16 is the clock frequency divided by 6 (or divided by 5 if SW1.2 is OFF). This frequency is 409.6kHz (419.52kHz) and is fed into the binary divider IC18. The output at TP5 is 50Hz (60Hz) and is fed back into IC17 as a stable 50Hz reference frequency which is used if the reserve supply is out of limits. If the reserve is healthy then the reserve zero crossing detector output is used as the frequency for the inverter. In either case, the selected waveform appears at IC17 pin 15.

The selection is made depending on the condition of the reserve. If RES FAIL input is active (HIGH) then the 50Hz reference at IC17 pin 2 is used. Otherwise, the reserve zero crossing detector output at IC17 pin 5 is used. In a system where the static switch board is not fitted, opening SW1.1 forces the signal at IC17 pin 2 to be used as no reserve zero crossing detector circuit is present.

The signal out of IC17 pin 15 is used as the frequency reference for the phase–locked–loop (P.L.L.). The feedback for the P.L.L. comes from IC17 pin 14, which represents the actual frequency of the inverter. If the inverter voltage is not low and the reserve static switch board is present (SW1.1 ON) then this signal is taken from the inverter zero crossing detector output connected to PL4 pin 17. Otherwise it is taken from the 50Hz output of the divider chain on page 2 of the diagram.

Using the outputs of both zero crossing detectors enables the phase–locked–loop to compensate for phase shifts through the output filter. However, when the inverter output voltage is low, the zero crossing detector output may not be reliable and therefore the signal at IC17 pin 6 is used.

IC17 pin 13 output is a fixed 2.4576MHz frequency reference which is used by the PWM generation circuit as a timing reference.

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4.2 = Inverter Drive Board

4.2.2 Phased Locked Loop:

IC10, IC11 and IC13 form the phase locked loop. Its function is to ensure that the inverter output remains phase locked to the reserve at all times.

It uses the reference and feedback signals from IC17 pin 15 and 14 respectively. Phase comparator 2 output (IC10 pin 13) goes active when the signals are not in phase as shown in Fig 4. At all other times PC2 output is tri–state. While PC2 output is active, PCP output (IC10 pin 1) is low.

Typical waveforms for PLL using phase

comparator 2, loop locked at fo

FIG 4

Signals PC2 and PCP are fed into IC19. The output of IC19 at pin 19 is the inverse of PC2 but with its active period limited to a maximum of 1/20 of the cycle period (at 50Hz). The inversion compensates for the inversion in the integrator which follows. By limiting the maximum active pulse to such a low value, all active pulses which occur while the system is not phase locked will be the same width. This and the integrator IC13 enable a linear frequency slew rate to be obtained. The integrator uses a capacitance multiplier circuit in its feedback loop. This allows non electrolytic type capacitors to be used.

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4.2 = Inverter Drive Board

The output of the integrator is a d.c. level which is fed into the input of the voltage controlled oscillator part of IC10 via a potential divider R96, R88. As the voltage level varies, the output frequency of the VCO at IC10 pin 4 varies accordingly. The rate of change of d.c. voltage, which determines the VCO slew rate, is set by the combination of R84 and equivalent capacitance of C47 and capacitance multiplier IC13.

With H1 the frequency slew rate can be changed from 0.3 to 3 Hz/Sec.

The VCO input at IC10 pin 9 is buffered and appears at pin 10 (TP4). A higher level at this point causes a higher operating frequency for the VCO.

P7 sets the operating range for the VCO for 50Hz. Setting of P7 is obtained by switching SW1.1 OFF and adjusting P7 until the voltage at TP4 settles to approximately 2.5V d.c. w.r.t 0V.

P8 sets the operating range for the VCO for 60Hz. Setting of P8 is obtained, after P7 setting, by switching SW1.1 OFF and adjusting P8 until the voltage at TP4 settles to approximately 2.5V d.c. w.r.t 0V.

This can be done with the inverter ON or OFF. Reset SW1.1 as required.

4.2.3 Waveform generation:

The 1.6MHz generated by the phase–locked–loop is fed into a series of four internally synchronous four stage counters IC14 and IC10. Each divide by 2 output is available giving a total of 15 frequencies from 1.6384MHz to 50Hz. From this, two 8 stage counters are derived. The first one from 409.6kHz to 3.2kHz is used to generate a 3.2kHz triangle wave. The other, from 6.4kHz to 50Hz, generates 3 phase shifted sinewaves.

IC11 and IC16 form an 8 bit multiplexer selecting which of the counters become the address lines A0 – A7 of the EPROM IC15.

The data required to generate the triangular wave and three sinewaves are stored in the EPROM with each waveform occupying a block of 256 bytes. Address lines A8 and A9 determine which block of memory is to be accessed.

IC12 is a four channel digital to analog converter. Channel 1 generates the triangular wave with an amplitude set by the voltage difference between pin 5 (REF A) and pin 6. This is a proportion of the d.c. voltage.

Channel 2, 3 and 4 generate the three sinewaves. The positive peak voltage is set by the voltages at pins 4, 21 and 20 respectively (REF B, REF C, REF D). FT1 is switched ON when the inverter is switched OFF, charging C41 from –6.2V to 0V, through D11. When FT1 is switched OFF C41 discharges slowly (t = R63 ? C41), providing a soft start at the inverter output.

The input at PL4 pin 14 is a variable d.c. level from the display board. This level and hence, the output voltage is changed by a switch selection on the display board.

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4.2 = Inverter Drive Board

REF B, REF C and REF D are output of the average voltage and current control loops. There is control in d.c. for each phase.

The amplitude of the three sinewaves is determined by the setting of P1, P2 and P3.

Trimmer P4, for the current loop, is set at 150% of the output nominal current. IC9B monitors the overcurrent > 150% and generates a current limit alarm signal at PL4 pin 15.

When the output current of any phase is > 150% nominal one of the three regulators intervenes to decrease the reference for the respective output phase. Voltage and current feedback are derived from the UPS output current and inverter voltage, which appear, rectified, at PL4 pin 7, 8 and 9 for the inverter voltage and PL4 pin 10, 11 and 12 for the output current. Trimmer P5 is utilized for the inverter manual operation. Outputs of the DAC are shifted and buffered, to produce reference sinewaves at TP8, TP9 and TP10 centered on 0V for the A.C. voltage control loop (page 5). This control operates on each phase.

The triangle–wave from IC12 on sheet 2, is filtered to produce a triangle–wave of 8Vpp centered 0V (TP17). The control for one phase is schematically described by the following figure, where the P.D. regulator for the phase R – shown on figure – is done by IC23B, C83, R110, R116D, R119 and C139.

Each error signal (Verr) is compared to the trianglewave by the three comparators IC40A, IC40B and IC38A. The three PWM signals at IC40 pins 1 and 7 and at IC38 pin 1 are fed into PWM control chips IC26, IC27 and IC28 which generate dead time of 10.4µSec. (15.2µSec. if H2 is not fitted) and generate complementary outputs for a single input.

IC15 and IC19 provide a current protection by switching off the PWM when the IPK is active. Signal INV OFF forces the outputs into tri–state when the inverter is switched off.

The PWM at TP11 to TP16 is fed into the DRIVER board through the transistors T4 to T9.

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4.2 = Inverter Drive Board

The desaturation signals from the BASE DRIVE boards are filtered and fed into IC35. When one of these signals is active then the inverter will be stopped. The outputs of IC35 send these information to the display board.

The overtemperature input at PL5 pins 1 and 2 comes from a normally closed thermostat. This signal stops the inverter and is then passed to the display board. If the inverter is stopped by a desaturation or overtemperature condition, then it is latched off by IC35. This can be reset by the INV RESET signal from the display board. The inverter can then be restarted with the inverter start signal.

Peak current limit is derived from the transducers on the inverter currents. The IPK signal active switches OFF the PWM.

The trimmer P9 provides the setting of the level of the peak current.

The outputs IC47 pins 1 and 7, which are proportional to the DC component of the inverter current, are fed into comparators IC40, producing dynamic adjustment of the offset.

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4.3 = STATIC SWITCH PCB

4.3 Static Switch pcb

Refer to circuit 04.13.170 become 15C90074

Inverter Zero Crossing Detector:

The inverter output waveform is sensed using a transformer that is on the Transformers pcb. IC13A buffers the inverter zero crossing detector from the transformer and raises the zero crossing center point to VREF1. IC16A is a comparator that gives a square wave output that is phase related to the inverter output. VR1 is used to adjust the phase of the ZCD to bring the inverter and reserve exactly in phase. The ZCD output is then fed to the PLL on the inverter pcb and also to the out of sync detector.

Reserve Zero Crossing Detector:

This is the same principle as the inverter ZCD using IC13B and IC168, except there is no phase adjustment.

Reserve High/Low Trips:

The output from IC13B is also used for the reserve high low trips. IC17A and B form a precision rectifier and therefore the output of IC17B is a full wave rectified reserve signal. This is then smoothed to give a DC proportional to the reserve voltage. IC15A and B form a window comparator, so if the reserve voltage exceeds the limits either NRVL or NRVH go low. The reserve trips are set up for 220V operation. For 230V, SW2.1 is closed, this reduces the DC voltage into the reserve low/high trip comparators. For 240V, SW2.2 is used. The trip levels can be adjusted using VR2.

SW2.3 must be always OFF, and SW2.4 always ON.

Static Switch Failure:

A logic signal (UPS LOW), coming from Interface board, enters on PL7 pin 28. If for any reason the static switch fails and half or all the output waveform is lost, UPS LOW goes low, then IC14 pin 1 goes high and IC15 pin 13 (NSSF) goes low.

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4.3 = STATIC SWITCH PCB

5V Power Supply:

The 5V power supply is fed from the interface pcb, there supplied by the reserve input and by the chopper. This is also backed up from the reserve power supply so that +5V is supplied to the control circuit even in the event of a power supply failure.

C12 and ZD1 protect the ICs from any overvoltage.

Two references are used for the static switch pcb: – VREF1 is a reference for the sense signals and VREF2 for the comparators.

Clock Generation:

IC6A in conjunction with crystal XL1 forms the main clock at 2.4576Mhz. The clock frequency is then divided by either 5 or 6 depending on SW1.3. Thus the clock frequency (IC6 pin 17) also used for synchronizing the rest of the control logic, is shown on the following table:–

SW1.3 UPS Frequency f on IC16 pin 17 ON 50Hz 409.6 kHz OFF 60Hz 491.5 kHz

Reserve Frequency Detector:

FRDT1, FRDT2 act in conjunction with a 4020 counter to form a frequency detection circuit that can be externally programmed for specific limits using SW1.7 and SW1.6. SW1.6 SW1.7 Frequency Tolerance ON ON 0.75 % ON OFF 1.5 % OFF ON 2.5 % OFF OFF 6.0 %

FPA and FPB are used to derive the start and stop signals for the frequency detector. Whenever the zero crossing detector goes high, FPA is generated, this is immediately followed by FPB. FPB resets the external counter, that then free runs. The counter outputs are read when the following FPA occurs ( at the next zero crossing).

The values read on the counter outputs means the reserve frequency.

If FPA occurs outside the time window, then it increments a 3 bit counter S1 to S3. After 8 consecutive times, NRFOL goes low. If the frequency returns within limits before the counter reaches 8, it is immediately reset.

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4.3 = STATIC SWITCH PCB

Input Latches IC18:

This synchronizes the digital inputs to the control logic circuitry.

Out of Sync Detector:

The latched versions of the ZCD outputs, FRESL and FINVL are exclusive ORed together giving a pulse with an on time equal to the phase difference of the reserve and inverter (pin 12).

On the leading edge of this pulse an internal counter is triggered and halted on the falling edge. If the counter reaches a preset number (Set by SW1.5 and SW1.4), then the reserve and inverter are considered to be out of synchronization. This signal then ORed with the reserve voltage low and reserve voltage high to give NOOS (active low) if any of these three are true.:

SW1.4 SW1.5 PHASE TOLERANCE OFF OFF 5 degrees

OFF ON 10 degrees ON OFF 15 degrees ON ON 20 degrees

Static Switch Logic:

The status of the static switches is determined by pin 15 NOUT of IC5, low = inverter to load. A transfer to reserve is instantaneous unless an out of synchronization is detected, in which case the transfer will have a 20mSec break to prevent large voltage differentials appearing across the static switches (transfers are limited to critical alarms only when NOOS is low). IC7 generates the out of sync transfer pulse. A re–transfer to inverter is delayed by 5 seconds by IC8 to prevent multiple switching of the static switches under load fault conditions.

In general all the inputs to IC5 (pins 2 to 9) must be high for the inverter to supply the load and ”System Normal” to be on. If either of the reserve trips NRVOL or NRFOL are low, then the inverter static switch will feed the load irrespective of the status of the inverter trips.

If the inverter is supplying the load and either NFAULT, NININVHI, NOL go low, then providing the reserve alarms are all healthy, NOUT will switch high transferring the load to reserve. Then the alarm that forced the transfer has cleared, the load will re–transfer to inverter after a further 5 seconds. NOL is a combination of either IPEAK or OL (overload) alarms.

If NOOS is low and a transfer is requested, a short pulse is generated at pin 18, NOOST, which triggers the 20mSec timer (IC7). The output of IC7 is fed into the gate drive logic IC where it inhibits the gate drive signal.

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4.3 = STATIC SWITCH PCB

Output Control:

IC6 pin 8 governs the status of the static switch. The static switch control can be overridden by SW1.1 and SW1.2 as shown on the following table:–

SW1.1 SW1.2 Static Switch Output OFF OFF normal operation ON OFF reserve

OFF ON inverter ON ON reserve

Static Switch Failure Logic:

If a static switch failure occurs (NSSF = 0), this is used to set the latch (IC19A) high. IC19 o/p remains high until reset.

Also the state of the static switch is registered by IC19B, thus IC19 pin 13 (I) = 1 for inverter static switch failed or 0 for reserve static switch failed. The outputs of the two latches are fed to SSF and I or IC6 which in turn locks the static switch to reserve or inverter using LKOU and R.I.

The reserve static switch failure circuit is overridden in the case of a reserve fault and the inverter static switch circuit is overridden in the event of an inverter fault (IC10, SSFAIL).

If the opposite static switch power input is out of limits, a transfer is not initiated under SSF conditions, but IC10 pin 13 is set low so that static switch failure indication is latched.

If there was a transfer to reserve from inverter and it was under these circumstances that the reserve static switch failure was detected, then the timer IC8 is overridden by RSSF to IC8 pin 8 going low. This causes an immediate transfer back to inverter.

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4.3 = STATIC SWITCH PCB

Output Buffers:

The digital output control lines are buffered by IC11 and IC12. These have open collector outputs.

RTL and ITL are used to drive opto couplers on the interface pcb for the static switch thyristor gate drives.

STATIC SWITCH TRIP SETTINGS:

Nominal Voltage 380V 400V 415V Reserve voltage Low 342V 358V 374V Reserve voltage low (reset) 365V 380V 396V Reserve voltage high 419V 438V 457V Reserve voltage high (reset) 405V 422V 439V

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4.4 = DISPLAY CONTROL BOARD

4.4 Display Control board

Refer to circuit diagram 04.14.670 become 15C90072

General:

The display control circuit is based around the Philips PCB80C552 single–chip 8–bit microcontroller. This is based on the 80C51 CPU with 256 bytes of RAM, timers, Analog–to–Digital converter, PWM outputs, digital I/O ports and a full duplex UART on board. For detailed information on this component refer to the relevant data sheets.

Although there are many 80C51 based microcontrollers with similar features to the 80C552 there is currently no direct second source for this component. To increase the capability of the 80C552 and to perform all of the functions required for the display control board, additional RAM, EPROM, EEPROM and digital input and output lines have been added.

Addressing and Data Bus:

The 80C552 can access up to 64K of program memory and additional 64K of data memory. When accessing external memory Port 0 and Port 2 of the 80C552 form the address and data buses. The lower order 8 bits of the address are output through Port 0 and latched by IC4 when ALE (Address Latch Enable, IC2 pin 48) goes high. The 8 bit data is then written or read through Port 0. Port 2 provides the higher order 8 bits of the address.

When reading program memory (EPROM), data is read when PSEN (Program Store Enable, IC2 pin 47) goes low. Reading and writing to data memory is controlled by RD (Read IC2 Pin 7) and WR (Write IC2 Pin 6)

Data Memory:

The 64K data area is made up of RAM and digital input and output lines. 32K is allocated to the RAM, although only 8K is used (IC12 pin 26 tied to +5V by LK3D).

IC5 and IC6 are the output data latches. When the address is 8006h or 8007h IC19 pulls the /CSOUT 0 or /CSOUT 1 low, respectively. When this line returns high the data appearing on the data bus is latched through to the output.

IC8 and IC9 provide open collector outputs for these signals.

IC10 is a series of darlington drivers used to drive the LEDs on the mimic board. Four outputs from IC6 and 2 outputs taken directly from IC2 are the signals for the LED drives.

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4.4 = DISPLAY CONTROL BOARD

The enable pin (pin 1) of IC5 and IC6 is driven from Pin 18 of the 80C552. At power up and under reset conditions, this pin is held high. IC5 and IC6 outputs are then forced to tristate and the internal pull up resistor at the inputs to IC8 and IC9 can pull these lines high. The outputs of IC8 and IC9 are then off until the microcontroller generates the required enable signal.

This prevents spurious output pulses at power up.

The drive signal for the buzzer comes from the PWM 0 output (pin 4) of the 80C552. This is set to high or low to switch the buzzer on or off. (HIGH = ON)

Frequency Inputs:

The inverter and reserve zero crossing detector outputs are fed into pins 16 and 17 of the microcontroller via buffer IC3. Pins 16 and 17 are coupled to timer T2 of the 80C552 which is configured as a 16 bit counter, free running at 1MHZ. At each positive going edge of the signals at Pin 16 and 17, the contents of timer T2 is saved to a register.

By reading this register following two consecutive edges, the period of the squarewave can be determined and hence its frequency can be calculated.

Analogue Inputs:

Port 5 of IC2 is used for the analogue inputs for the analogue to digital converter on board the 80C552. This is a 10 bit converter with eight multiplexed inputs. The inverter voltage and load current waveforms appear on pins 1 and 68 of IC2. These waveforms are sampled once every 250 micro–seconds during the sampling cycle and from this data R.M.S calculations are performed. For this reason only small noise filters can be used on these lines. The other four analogue inputs are DC levels which are read once every l00mSec. Each of these inputs has a filter comprising of a l00KΩ resistor and a 1µF capacitor.

The analogue reference for the analogue to digital converter is derived from a 2.5 volt zener diode. This voltage represents the full scale voltage for all of the analogue inputs. The accuracy of this voltage is not critical as any error is compensated for in software by the self calibration routine.

Analogue Output:

Pin 5 of IC2 is a PWM output controlled by the 80C552.

This is configured to operate at a frequency of 23.5kHz with a duty cycle variable from 0 to 100%. The squarewave output from pin 5 is filtered by R6 and G13 to give a d.c. level proportional to the duty cycle of the PWM at the base of TR2. TR2 acts as a buffer for this analogue voltage. The greater the duty cycle at pin 5, the higher the d.c level at PL8 pin 43. This d.c level is used to vary the inverter output voltage, by varying the reference level on the inverter drive board.

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4.4 = DISPLAY CONTROL BOARD

EEPROM:

IC1 is a 93C46 128 byte by 8 bit EEPROM. This device can also be configured as 64 x 16 by pulling pin 6 high.

The clock, data in and data out pins of the EEPROM are connected to Port 4 of the microcontroller. The clock pin (pin 2 of IC1) is used to clock serial data into or out of the EEPROM and is only used when data is being written to or read from the device. Chip select for the EEPROM is derived from the GAL, IC7. This line (CSEE) is set active by writing a 1 to address 8008h. It is cleared by writing a 0 to this address.

Crystal Oscillator:

The oscillator for the microprocessor is built into the 80C552 device and requires only the crystal QZ1 and capacitor C10 and C11 to produce the necessary clock.

The oscillator which is used for the RS232 baud rate is based around the GAL, IC7. This uses a 4.9152 MHz crystal frequency which is then divided by 16 to provide a frequency reference of 307.2 kHz. This is then fed into the timer1 input of the microprocessor. The 80C552 then performs the necessary division to provide a baud rate of 1200, 4800, 9600 or 19200 baud depending on the setting of the relevant DIL switches.

RS232C Interface:

The RS232C port uses the UART (Universal Asynchronous Receiver Transmitter) which is part of the 80C552. The data lines are TXD (IC2 pin 25) for data transmitted from the microcontroller and RXD (IC2 pin 24) for data received.

Where necessary, data flow through external devices such as the RS232C to RS2422A converter can be controlled using the line DTR (from IC2 pin 23). These three lines are buffered by IC3 and leave the display control board in TTL format. Conversion into RS232C levels is performed on the interface board.

LCD Interface:

The LCD module is driven through the parallel ports on the 80C552. Port 4 is used for the data transfer and three lines from Port 1.

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4.5 INTERFACE PCB

4.5 Interface board

Refer to circuit diagram 15C70516

This PCB performs the following functions:–

i) Supply section: provides a distribution of supply voltage for the boards. ii) Acts as a distribution point for routing control signals.

iii) provides a start–point ground for all other PCBs.

This start–point is connected to chassis through the inductance L1. iv) Provides Open–collector drives for the rectifier and static switch

photo–triac.

v) Provides isolation for RS232, AS400 and R.A.U. interfaces using relays. vi) Provides control logic and drive circuit for D.C..

vii) Provides the display pcb with two positive signals (charge/discharge current) derived from the hall–effect current transducer.

viii) Provides precision rectification of A.C. signals to feed the display pcb. ix) Provides Output Voltage, Reserve Voltage and Mains Voltage detectors. x) Provides rectifier current limit.

4.5.1 Precision Rectifier:

– Inverter and Reserve Current

As the micro–processor analog inputs can only accept positive signals within the range 0V to 2.5V, the inverter and reserve sample circuits are followed by precision rectifiers. The reserve and the inverter full–wave precision rectifiers have a gain of 0.66.

– Load Current

A 1000 : 1 load current transformer is connected to burden resistors R170, R171 and R172. These resistors will change depending on the unit with J1 and J2. An A.C. voltage proportional to 1/1000 of the load current is produced across the burden resistors. This signal is full–wave precision rectified, with a gain of 1, by IC26, IC28 and IC31.

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4.5 INTERFACE PCB

4.5.2 DC Rail Voltage Monitor:

This circuit provides a low voltage signal proportional to the DC rail voltage. To enable op–amp IC25 and IC27 to run with a single supply rail, the ”center–point” of the input attenuator is biased at 2V. The two inputs from R174 and R176 are buffered by two high impedance op–amps IC25B and IC27A, and fed to the differential amplifier IC27B.

The output through the trimmer P8 is fed to the microprocessor, while the signal on the common–point of resistors R268 and R269 is fed in the rectifier and inverter control.

4.5.3 Battery Current Conditioning:

A 1000 : 1 hall effect current transducer is used to provide an isolated signal proportional to the battery current. The current transducer burden resistor R194 or the parallel R294, R210 and R212 according if the current transducer has current or voltage output.

The voltage across the burden resistor is positive for charge currents and negative for discharge currents. The charge current circuit, with output at TP14, has IC33A configured as a non–inverting amplifier with a gain of 2. The diode, in its output, blocks negative voltage during battery discharge.

The discharge current circuit, with output at TP15, has IC33B configured as an inverting amplifier with a gain of 0.332. The diode, in the output, blocks negative voltage during battery charge.

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4.5 INTERFACE PCB

4.5.4 DC Battery Contactor Drive Circuit:

A low level on pin 9 or pin 10 of IC40 will initiate the contactor to open. A low level on pin 9 means By–pass switch and Output switch simultaneously closed.

The signal on pin 10 is low only when:–

PSFA = 1

and /INVSTAT = 1 and /BATTEST = 0

The circuit comprising of components IC34, R233, C88, R221 and R222 provides a 1 second time delay. This ensures that the inverter has stopped before the battery contactor is opened.

Initially, at power up, the level at IC34 pin 1 is LOW until the VDC rail is ranged up over 288V (i.e. for 144 cells).

This is done to synchronize the start of the timer, IC39, with the powering up of the contactor output drive stage.

The HIGH level on the input of IC36 pin 5 is inverted and splits into two paths:– 1) In one direction it starts the timer IC39; its pin 8 goes LOW for 10 seconds and then stays HIGH. This signal inverted by IC36 turn on IC30, providing full drive current for 10 seconds to the contactor, which is connected between PL11.7 and PL11.6.

2) Having pulled the contactor IC30A, a reduced level of current, limited by R199, can flow through IC30A when IC30B stops conducting.

This allows saving current (energy) once the contactor has been supplied. The contactor will open under the following conditions:–

i) At the end of battery discharge. i.e. Low battery condition, ii) When the bypass and output breakers are simultaneously ON, iii) When the emergency Power OFF is initiated,

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4.5 INTERFACE PCB

4.5.5 RS232 Interface:

The RXDATA, DSR, CTS and DCD inputs to the UPS feed onto the IC19 and IC22, RS232 line driver IC.

These signals, through the IC19, IC22 and the opto–couplers go to the display pcb. The TXDATA, DTR and RTS lines from the display pcb drive the opto–couplers. The signals pass through the opto–couplers onto the RS232 line drive IC, which translate the TTL levels to the EIA–standard–RS232.

The supply for IC19 and IC22 (+5VRS) is isolated and derived from the main S.M.P.S. through the voltage regulator IC1.

The use of opto–couplers and an isolated RS232 supply enable the RS232 interface to be fully isolated avoiding sections damage to the UPS in the event of incorrect connections to the RS232 port.

4.5.6 AS400 Interface:

The AS400 socket on the rear of the UPS is connected to the interface pcb via PL21 flat cable. All AS400 outputs are derived by switching relays.

The ’UPS ON and Supplying Load” output is provided by RL5 driven by a rectifier circuit, and fed from the load output sample transformer.

The ”Reserve to Load” output is provided by RL4 which is driven by IC30. This signal feeding the IC30 comes straight from the display pcb.

The ”Primary supply fail” and ”Shutdown Imminent” are driven by RL3 and RL2 respectively.

When the bypass breaker is operated then these outputs are inhibited.

4.5.7 Remote Alarm Unit Interface (R.A.U.):

An unregulated A.C. power supply from the RAU is derived from an output voltage transformer. The RAU output signals for ”Load on Reserve”, ”Mains failure”, ”Shutdown Imminent”, ”Inverter fault” and ”Summary Alarm” are derived by switching relays. The input signals to the relays drivers are derived from micro–processor outputs on the display pcb.

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4.5 INTERFACE PCB

4.5.8 Inverter, Reserve and Rectifier Thyristor Drives:

The following figure shows the circuit which drives photo–triacs (on the firing board) for SCR static switch.

A B

C

D

When ITL is active (load on inverter) the output of IC14 is LOW, the current through the resistors A and C switches on the photo–triac, and is limited to 10 mA. The resistor B and D limits the voltage in the diode of photo–triac.

The same currents are for the drivers for rectifier’s SCRs.

4.5.9 V OUT Detector:

The circuit (IC11) senses the VOUT and generates an alarm signal /UPS when the output voltage is lower or higher than 17% of the nominal.

The switch SW1 allows the selection of the nominal voltage as follows:– VOUT SW1.1 SW1.2

380V OFF OFF 400V ON OFF 415V ON ON

Such signal is sent to the reserve static switch board and generates an alarm of ”static switch failure”.

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4.5 INTERFACE PCB

4.5.10 V RES Detector:

This circuit senses the average value of the 3 voltage of the reserve which are summed by IC35.

The output of the sum is a voltage about 2.05VDC (at 380V). In addition, when EPO or wrong phase rotation failure sensors are active, such increases, and signal allows to open the reserve static switch and therefore disconnecting the load. Such signal that goes into the reserve static switch board provides an alarm for LOW/HIGH reserve voltage.

4.5.11 V MAINS Detector:

As the V OUT detector, this sensor is based on the LOW/HIGH window and provides an alarm to the microprocessor and the rectifier (turning OFF it) when the input voltage to the rectifier is not within the range of +/–20%.

4.5.12 Backfeed Protection:

OP1 is an opto–coupler which receives a signal from the backfeed protection board and generates an alarm for the micro–processor (pin 9 of PL23).

4.5.13 Hydrogen Detector:

The output of the opto–coupler is logic signal that goes to the rectifier control and reduces the voltage reference for the DC (e.g. from 327V DC nominal to about 288V) and generates an alarm on the display ”Battery Charge Inhibited” when the input signal is active, for instance when there is hydrogen in the battery cabinet.

4.5.14 Emergency Power OFF (EPO):

When the EPO is active, the opto–couplers OP12, OP13 and OP15 switch ON, then:–

– the rectifier shutdown, – the inverter is inhibited, – static switch is open, – battery contactor is open. In this situation, the load is not supplied.

4.5.15 Rectifier Current:

The rectifier current is buffered by IC37, and fed into the display board for the measurement and the rectifier control loop in the rectifier board.

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4.6 = BASE DRIVE PCB

4.6 Base Driver board

(Ref. 15C70533)

There are two distinct power driver stages on the driver board, one is used to drive the high switch of the power H–bridge (DC/ac converter), the other one to drive the low switch of the power H–bridge. These two stage are identical but are electrical insulated.

The driver is supplied by the SMPS board (15C70514), receives the PWM signal from the inverter control board (15C70512), transmits desaturation signal to the inverter control board and drives the power switch of H–bridge through connector 2K. (Connector 2K is common to the two driver stages)

Referring to the first section, the input pwm signal is opto–isolated by opto–coupler OP1, a on delay time of about 1.5µs is added by a RCD network (R17,C15,D8) operating with a Schmitt inverter. This signal drives a current generator that sources current to the base of power transistor (power module), the current is selectable from 1 to 6A by J1 & J9, the source current is supplied by T7 a T0220 NPN darlington power transistor. The sink current, when the power module is driven off,is limited by the value of R3 plus R4, this current is sunk by T5 a T0220 PNP darlington power transistor.

Desaturation is sensed by a fast precision comparator (U3) and sent to the inverter control board by a fast opto–coupler OP2. This signal has a memory to achieve a more reliable protection action. During switching, the desaturation signal is masked to avoid false alarms.

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4.7 = SMPS BOARD

4.7 SMPS BOARD

(Ref. 15C70514 )

DC input voltage: 230V to 550V AC input voltage: not allowed Output power: 110W maximum

The SMPS supplies the following outputs:

+8V 2.5A (isolated) control +8V 0.3A (isolated) interface +/– 17V 0.5A (isolated) control

+7V/–11V 3Apk (isolated) H–bridge driver +7V/–11V 3Apk (isolated) H–bridge driver +7V/–11V 3Apk (isolated) H–bridge driver +7V/–11V 3Apk (isolated) H–bridge driver +7V/–11V 3Apk (isolated) H–bridge driver +7V/–11V 3Apk (isolated) H–bridge driver There are two distinct power stage converters:–

– a Buck to supply a regulated unisolated voltage of 150V,

– a Push–Pull powered by 150V to obtain the above mentioned insulated output supplies.

The “Buck” stage:

The Buck converter is controlled by a Siemens TDA4919 (IC1), a PWM single ended controller operating in voltage mode, an internal under–voltage comparator with hysterisis is used to inhibit the output driver of IC1 when the DC rail falls down 165V.

The operating frequency (about 50kHz) is set up by the value of C5 and R3 while the pwm ramp slope is determined by the value of C4, which has to be at least five times the value of C5, and by R39 and R40 that perform a feed forward control action. Resistor R24 senses the Buck current, and ratio of R5 and R8 sets the threshold level of the current limiter. A multiple RC network (R23,C15,R12,C11) is used to clean up the current signal. Soft start action is present to limit the current when the output capacitors are charged, the duration of the soft start can be programmed by the size of the capacitor C6. A voltage reference of 2.5V is available at pin 11, it provides a highly constant temperature characteristic and it is used as reference signal for under–voltage comparator, current limiter comparator and as set–point in the control output voltage.

The power switch (S5) is a T03P N channel power mosfet rated at 1000V Vds and 8A Id @ 25·C, the free wheeling diode (D6) is a 1000V 12A very fast recovery epitaxial diode.

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4.7 = SMPS BOARD

A voltage dependent resistor (VR1) protects the circuit against the risk of voltage spikes present on DC rail. An input RFI filter (C22,C23,C24) attenuates high frequency attenuations, C22 and C24 are metallized paper capacitors.

At start up, IC1 is powered by a linear power supply (S4 T1 Z3) which is locked out when feedback from an auxiliary output of the Push Pull transformer(TR4) is present, when this action is performed a green led (DL1) lights up.

The input rectifier voltage feedback is obtained from a voltage divider (R27,R28,R29,R30,R31), this signal is available at connector 2M.

Toroidal inductor LS1 and polypropylene capacitor C27 form the output filter,the output voltage is sensed by a differential amplifier IC3, the feedback control network uses the internal opamp of TDA4919, variable resistor P1 sets the output voltage to 150V.

The “Push–Pull” stage:

The Push Pull converter is controlled by a Siemens TDA4918 (IC2), a PWM controller operating in voltage mode, an internal overvoltage comparator with hysterisis, is used to inhibit the output drivers of IC2 if the output of buck goes over 190V, due to a buck failure.

The operating frequency (about 50kHz) is set up by the value of C35 and R51, while the pwm ramp slope is determined by the value of C34, which has to be at least five times the value of C35. No feed forward actions is performed in this stage and the duty cycle is fixed at 50%, the dead–time is generated inside the TDA4918 and can be externally modified.

The resistor R72 senses the Push Pull current and the ratio of R56 and R59 sets up the threshold level of the current limiter, a multiple RC network (R58,C43,R71,C41) is used to clean up the current signal.

A soft start action is present to limit the current when the output capacitors are charged, the duration of the soft start can be programmed by the size of the capacitor C36. A voltage reference of 2.5V is available at pin 11, it exhibits a highly constant temperature characteristic and it is used as reference signal for overvoltage comparator and current limiter. At startup IC2, is powered by a linear power supply (S3,T2,Z8) which is locked out when feedback from an auxiliary output of the Push Pull transformer (TR4).

Four transformers (TR1,TR2,TR3,TR4) are paralleled together in Push Pull stage to deliver the supplies needed to power the circuits, each secondary has a rectifier with two capacitors. An electrolytic capacitor to smooth and a ceramic to remove high frequency noise.

The outputs of the PWM controller ICs are active high and can deliver all the current needed to drive power mosfet transistors, the voltage supply of this stage is separated from the logic so noise in control circuits is avoid.

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5a = SOFTWARE DESCRIPTION ( FSB < 30 )

5a

SOFTWARE FUNCTIONAL DESCRIPTION

(for UPS having FSB status < 30)

5a.1 General

The software for the microcontroller on the display control board reads all of the digital inputs, analog inputs and both frequency inputs. It generates alarms which cause messages to be displayed and outputs from the display control board to be driven. This document describes the conditions which need to be met in order to generate each of the messages and outputs.

All digital inputs are read once every 100mSec. Analog and frequency measurements are also read every 100mSec. All digital inputs are not filtered in software as filtering is performed in hardware by capacitors mounted on the PCB. Analog measurements, including frequencies, are filtered. This filter takes the average of a given number of samples and is updated every time a new sample is taken.

5a.2 Accessing Information

All of the information can be accessed through the LCD Display by using the 3 arrow keys on the front panel of the UPS. The information is arranged in columns. The and keys allow movement up and down the selected column and the

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5a = SOFTWARE DESCRIPTION ( FSB < 30 )

5a.2.1 The first column contains information relevant to the UPS as a whole.

The first page will normally show the UPS rating on the first line with one of the following messages on the second:

SYSTEM NORMAL TESTING BATTERY SYSTEM IN ALARM

If the battery is discharging or the inverter is in overload operation then an additional page of information is inserted at the top of the first column. This will be in the form:

BATTERY DISCHARGING AUT **min DIS **min

or

OVERLOAD INV STOP **m:**s

If both conditions are true then both pages of information will be accessible. The top of the column will be the one showing the shortest time before inverter shutdown.

If none of the arrow keys is pressed, then after 5 minutes the display will return to the top page of the first column of information. This top page will automatically change according to the UPS operating condition as described above.

Following the UPS status, each of the measurements available in the UPS can be displayed. These are:

D.C. Voltage and Rectifier Current D.C. Voltage and Battery Current Inverter Voltage and Frequency Reserve Voltage and Frequency Load Currents

Load Peak Factor and Percentage Loading Total time on Inverter

Total time on Reserve

Number of mains failures and Total Duration

Pressing the key moves down through this list. The key can be used to move back up. At the end of the measurements, the software revision and release date is displayed. Note that the revision and release date of the

software is also displayed for 2 seconds when the machine is switched ON or if the retrofit option has been selected.

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5a = SOFTWARE DESCRIPTION ( FSB < 30 )

5a.2.2 The second column contains information relevant to the Rectifier and Battery.

The first line of the display will show:

RECT/BATT ALARMS

While the second line will show the first active message from the following:

NO ALARM ACTIVE PRIMARY SUPPLY FAIL PHASE FREQUENCY ERROR

BATTERY FAULT BATT CONTACTOR OPEN BATTERY DISCHARGING SHUTDOWN IMMINENT

DC VOLTAGE HIGH DC VOLTAGE LOW HARMONIC FILTER OPEN

BATT. CHARGE INHIBIT MAINS INPUT SWITCH OPEN

If more than one of these alarms is ON, pressing the key will move through the list of active messages.

After the last active alarm, pressing the key will move through the following pages of measurements:

D.C. Voltage and Rectifier Current D.C. Voltage and Battery Current

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5a = SOFTWARE DESCRIPTION ( FSB < 30 )

5a.2.3 The third column contains information relevant to the Inverter.

The first line of the display will show:

INVERTER ALARMS

While the second line will show the first active message from the following:

NO ALARM ACTIVE INVERTER FAULT

OUT OF SYNC OVER TEMPERATURE BYPASS SWITCH CLOSED

SHUTDOWN IMMINENT DC VOLTAGE HIGH

DC VOLTAGE LOW INVERTER NOT RUNNING

INVERTER INHIBITED INVERTER BLOCKED INVERTER VOLTS HIGH

INVERTER VOLTS LOW OVERLOAD

STOP DUE TO OVERLOAD STATIC SWITCH FAULT

CURRENT LIMIT SYSTEM TEST MODE

If more than one of these alarms is ON, pressing the key will move through the list of active messages.

After the last active alarm, pressing the key will display Inverter Voltage and Frequency.

edp70

TECHNICAL MANUAL

EDP70

UNINTERRUPTIBLE POWER

SYSTEM

TECHNICAL HANDBOOK

This manual includes:

– the description of the software used up to FSB = 29

and the one used from

FSB = 30

CHLORIDE

SILECTRON

CONTENTS

1

SAFETY

1.1 General

1.2 Electric shock

1.3 Safety warning

2

MAINTENANCE PROCEDURES

2.1 Tools & Test equipment

2.2 Procedures

2.3 Fuse blowing

2.4 Fans replacement

3

POWER ASSEMBLY DESCRIPTION

3.1 Input choke / Input autotransformer

3.2 Rectifier Assembly

3.3 DC choke

3.4 DC capacitor

3.5 Inverter Assembly

3.6 Static Switch Assembly

3.7 Display pcb Assembly

4

CONTROL LOGIC DESCRIPTIONS

4.1 Rectifier control pcb

4.2 Inverter pcb

4.3 Static Switch pcb

4.4 Display pcb

4.5 Interface pcb

4.6 Base drive pcb

4.7 S.M.P.S. PCB

5a

SOFTWARE FUNCTIONAL DESCRIPTION

(for UPS having FSB status < 30)

5a.1 General

5a.2 Accessing information

5a.3 Measurements

5a.4 Alarm Message and digital output

5a.5 Buzzer

5a.6 LEDs

5a.7 Inverter Stop/Start

5a.8 RAU & AS400 outputs

5a.9 POWER HISTORY

5a.10 Battery autonomy

5a.11 RS232 port

5a.12 Inverter Voltage control

5a.13 Display Board trip settings

5a.14 DIL Switch settings

5b. SOFTWARE FUNCTIONAL DESCRIPTION

(for UPS having FSB status > = 30)

5b.1

GENERAL

5b.2

ACCESSING INFORMATION

5b.3

MEASUREMENTS

5b.4

ALARM MESSAGE AND DIGITAL OUTPUT

5b.5 BUZZER

5b.6 LEDS

5b.7

INVERTER STOP/START

5b.8

DATA STORAGE METHOD DESCRIPTION

5b.9

RECTIFIER STARTUP CONTROL

5b.10 RAU & AS400 OUTPUTS

5b.11 POWER HISTORY

5b.12