7. Memory Interfacing With Example.pptx

Memory interfacing

Prepared By AJIT SARAF Memory structure and it’s requirements.

Basic concepts in memory interfacing. Address decoding and memory address.

 Basics of 8085:

 Types of memory and memory interfacing.

 Decoding techniques – Absolute and Partial

Module 1

Memory structure and it’s requirements (RAM)

R/W Memory N M Output buffer Input buffer I N T E R N A L D E C O D E R Input data Output data A10 A0 WR CS RD N = number of register M = word length

Logic Diagram for RAM

2048 8

Memory structure and it’s requirements (ROM)

Output buffer Output data A11 A0 CS RD N = number of register M = word length

Logic Diagram for EPROM

I N T E R N A L D E C O D E R EPROM 4096 8

Example:

If a memory is having 13 address lines and 8 data lines, then the number of registers / memory locations = 2^13 = 8129 word length = 8 bit

Note: The number of address lines of a microprocessor depends on the Size of the memory.

128

7

64

6

32

5

16

4

8

3

4

2

2

1

Memory size in bytes

No. of lines

65536=64k

16

32768=32k

15

16384=16k

14

8129=8k

13

4096=4k

12

2048=2k

11

1024=1k

10

512

9

256

8

1) 8085 can access 64 KB of memory, since address bus is

16-bit. But

it is not always necessary to use full

64Kbytes address space. The total memory size depends

upon the application.

2) Generally EPROM is used as a program memory and

RAM is used as data memory. when both are used then

total 64 KB address will be shared by both.

3) The capacity of program memory and data memory

depends on the application.

Basic concepts in memory interfacing (Rules)

4) It is not always necessary to select 1 EPROM and 1

RAM. We can have multiple EPROMs and multiple

RAMs as per the requirement of application.

5) We can place EPROM / RAM anywhere in full 64

Kbytes address space. But program memory (EPROM)

should be located from address 0000H since reset

address of 8085 microprocessor is 0000H.

6) It is not always necessary to locate EPROM and RAM in

consecutive memory addresses.

Basic concepts in memory interfacing (Rules)

using 1) Absolute / Full Decoding 2) Partial / Linear Decoding. Solution: A10A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 A15 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Address MEMORY ICs Starting address Of EPROM End address Of EPROM Starting address Of RAM End address Of RAM A14A13 A12A11 0000H 1FFFH 2000H 3FFFH

+ 5V RESETIN LE 8085 7 4 3 7 3 A0 – A7 AD0 -AD7 D0 – D7 + 5V READY TRAP RST 7.5 RST 6.5 RST 5.5 RESETOUT 6 MHz 75 K 1 uF 1 uF X1 X2 ALE A8 – A15 1 uF INTR INTA SW D0-D7 A0-A7 A8-A15 IOR IOW MEMR MEMW D7-D0 A12A11 A10 A9A8 A7-A0 OE EPROM (8K) 2764 CS D7-D0 A12A11 A10 A9A8 A7-A0 OE WR RAM (8K) 6264 CS WR RD IO/M G1 G2 G VCC Y5 Y6 Y1 Y2 A B C 7 4 L S 1 3 8 G1 G2 A13 A14 A15 Y0 Y1 A B C 7 4 L S 1 3 8 VCC G

Absolute Decoding Technique / Full Decoding

D0-D7 A0-A7 A8-A15 IOR IOW MEMR MEMW D7-D0 A12A11 A10 A9A8 A7-A0 OE EPROM (8K) 2764 CS D7-D0 A12A11 A10 A9A8 A7-A0 OE WR RAM (8K) 6264 CS WR RD IO/M G1 G2 G VCC Y5 Y6 Y1 Y2 A B C 7 4 L S 1 3 8

Linear Decoding Technique / Partial Decoding

A13

Q.2) Design a microprocessor system for 8085 such that it should contain 16k byte of EPROM and 4k byte of RAM using 8 Kbyte EPROMs and 2k byte RAMs.

Solution:

Memory Ics A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ADDRESS

s.a of EPROM1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H e.a of EPROM1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1FFFH s.a of EPROM2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2000H e.a of EPROM2 _{0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3FFFH} s.a of RAM1 0 1 0 X X 0 0 0 0 0 0 0 0 0 0 0 4000H e.a of RAM1 _{0 1 0 X X 1 1 1 1 1 1 1 1 1 1 1 47FFH} s.a of RAM2 _{0 1 1 X X 0 0 0 0 0 0 0 0 0 0 0 6000H} s.a of RAM2 0 1 1 X X 1 1 1 1 1 1 1 1 1 1 1 67FFH

D0-D7 D7-D0A12A11 A10 A9A8 A7-A0OE EPROM (8K) 2764 CS D7- D0 A10 A9 A8 A7-A0 OE WR RAM (2K) 6116 CS D7-D0A12A11 A10 A9A8 A7-A0OE EPROM (8K) 2764 CS D7- D0 A10 A9 A8 A7-A0OE WR RAM (2K) 6116 CS WR RD IO/M G1 G2 G VCC Y5 Y6 Y1 Y2 A B C 7 4 L S 1 3 8 A0-A7 A8-A15 MEMW MEMR IOR IOW A13 A14 A15 G1 G2 G VCC Y0 Y1 Y2 Y3 A B C 7 4 L S 1 3 8 A11 A12 A11 A12

Q.3) Interface 2kb EPROM to 8085 using EPROM (1k X 4) chips, 74LS138 decoder and full address decoding and give the address map.

Solution:

Memory Ics A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ADDRESS

s.a of EPROM1 _{0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H} e.a of EPROM1 _{0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 03FFH} s.a of EPROM2 _{0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H} e.a of EPROM2 _{0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 03FFH} s.a of EPROM3 _{0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2000H} e.a of EPROM3 _{0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 23FFH} s.a of EPROM4 _{0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2000H} e.a of EPROM4 _{0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 23FFH} D7- D4 A9 A8 A7-A0 OE WR EPROM (1K) CS D3- D0 A9 A8 A7-A0 OE WR EPROM (1K) CS D3- D0 A9 A8 A7-A0 OE WR EPROM (1K) CS D7- D4 A9 A8 A7-A0 OE WR EPROM (1K) CS WR RD IO/M G1 G2 G VCC Y5 Y6 Y1 Y2 A B C 7 4 L S 1 3 8 MEMW MEMR IOR IOW A13 A14 A15 G1 G2 G VCC Y0 Y1 A B C 7 4 L S 1 3 8 A12 A11 A10 A8-A15 D0-D7 A0-A7

Q.4) Design an 8085 based system for the following specifications: (a) CPU working at 3 MHz.

(b) 8kB EPROM using 4kB devices. (c) 4kB RAM using 2kB devices. (d) One 8259 PIC in I/O mapped I/O. (e) One 8255 in I/O mapped I/O.

Draw the complete interfacing diagram with latches, chip select logic, Reset circuit.

Memory Map:

Memory Ics A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ADDRESS

S.A. of EPROM1 _{0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H} E.A. of EPROM1 _{0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0FFFH} S.A. of EPROM2 _{0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1000H} E.A. of EPROM2 _{0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1FFFH} S.A. of RAM1 _{0 0 1 0 X 0 0 0 0 0 0 0 0 0 0 0 2000H} E.A. of RAM1 _{0 0 1 0 X 1 1 1 1 1 1 1 1 1 1 1 27FFH} S.A. of RAM1 _{0 0 1 1 X 0 0 0 0 0 0 0 0 0 0 0 3000H} E.A. of RAM1 _{0 0 1 1 X 1 1 1 1 1 1 1 1 1 1 1 37FFH}

Solution: I/O Map

Ports and Registers A7

A15 A6 A14 A5 A13 A4 A12 A3 A11 A2 A10 A1 A9 A0 A8 ADDRESS Port A 0 1 0 0 0 0 0 0 40H Port B 0 1 0 0 0 0 0 1 41H Port C 0 1 0 0 0 0 1 0 42H CWR 0 1 0 0 0 0 1 1 43H 8259 Chip 0 1 0 1 0 0 0 0/1 50/51H + 5V RESETIN LE 8085 7 4 3 7 3 A0 – A7 AD0 -AD7 D0 – D7 + 5V READY TRAP RST 7.5 RST 6.5 RST 5.5 RESETOUT 6 MHz 75 K 1 uF 1 uF X1 X2 ALE A8 – A15 1 uF INTR INTA SW D0-D7 D7-D0A11 A10 A9 A8 A7-A0 OE EPROM 1(4K) CS D7- D0 A10 A9 A8 A7-A0 OE WR RAM2 (2K) CS D7-D0A11 A10 A9 A8 A7-A0OE EPROM2 (4K) CS D7- D0 A10 A9 A8 A7-A0OE WR RAM1 (2K) CS WR RD IO/M G1 G2 G VCC Y5 Y6 Y1 Y2 A B C 7 4 L S 1 3 8 A0-A7 A8-A15 MEMW MEMR IOR IOW A12 A13 A14 G1 G2 G VCC Y0 Y1 Y2 Y3 A B C 7 4 L S 1 3 8 A15 A11 A11

D0-D7 WR RD IO/M G1 G2 G VCC Y5 Y6 Y1 Y2 A B C 7 4 L S 1 3 8 A0-A7 A8-A15 MEMW MEMR IOR IOW A12 A13 A14 G1 G2 G VCC Y4 Y5 A B C 7 4 L S 1 3 8 A15 8 2 5 5 8 2 5 9 PA PB PC OE WR OE WR A0,A1 A0 CS CS D0-D7 D0-D7 IR0 IR7 CAS0 CAS1 CAS2 INT INTA Reset INTA INTR RESET OUT SP/EN Vcc + 5V

University Questions (ELECTRONICS)

1) Design a system based on 8085 with following configuration

(i) 8K x 8 EPROM using 4K x 8 chips (10 Marks)

(ii) 8K x 8 RAM using 4K x 8 chips Draw memory map and interface diagram.

 Dec-2012

2) Design 8085 based system with following specifications :

(i) CPU operating at 3 MHz. (12 Marks)

(ii) 16 KB program memory using 4 KB devices. (iii) 4 KB data memory using 2 KB devices.

(iv) One 8 bit input port and one 8 bit output port performing interrupt driven I/O and interfaced in I/O mapped I/O mode. Use exhaustive decoding approach. Give detailed I/O map and memory map and neat interfacing diagram.