CAO CH-2.pptx

UNIT-2



Store program control concept



Flynn’s classification of computers

(SISD, SIMD, MISD, MIMD)



Multilevel viewpoint of a machine:

digital logic, micro architecture, ISA,

operating systems, high level language



Structured organization; CPU, caches,

main memory, secondary memory

units & I/O;



Performance Metrics(NUMERICALS)

A

device

that accepts data,

processes the data in

accordance with a stored

program

, generates results,

and usually consists of input,

output, storage, arithmetic,

logic, and control units

BLOCK DIAGRAM OF DIGITAL COMPUTER

Random-access memory (RAM)

Central processing unit

(CPU)

Input-output processor

(IOP)

Input

devices

Output

devices

A digital computer consists of a

number of processors

interconnected with memory and

Input/Output devices

A

Processor or CPU (C

entral

P

rocessing

U

nit

)

fetches

instructions from memory, and

executes them one after another

A

Memory

is where programs

and data are stored

I/O devices

allow for interaction

between users and computer

Computer architecture

=

Instruction set

architecture

+

Instruction is the fundamental unit of work.

Specifies two things:

opcode: operation to be performed

operands: data/locations to be used for operation

An instruction is encoded as a sequence of

bits.

(Just like data!)

A computer’s instructions and their formats is

known as its

Instruction Set Architecture

(ISA)

.

Instruction code format with two parts : Op. Code + Address

Op. Code

: specify possible operations

Address

: specify the address of an operand

INSTRUCTION CODE FORMAT

instruction

COMPONENTS OF INSTRUCTIONS

Operations (opcodes)

Number of operands (Number of data

locations)

add value in src1 to

value in src2 and place the

result in dst.

ADD R1, R2, R3 R1  R2 + R3

add r1,r2,r3

NUMBER OF OPERANDS PER

INSTRUCTION

No Operands HALT NOP

1 operand NOT R4 R4  R4

2 operands ADD R1, R2 R1  R1 + R2

Instruction set architecture is the attributes of a computing system as seen by the assembly language programmer or compiler. This includes

Instruction Set (what operations can be

performed?)

Instruction Format (how are instructions

specified?)

Data storage (where is data located?)

Addressing Modes (how is data

accessed?)

Exceptional Conditions (what happens if

something goes wrong?)

Instruction Formats

Fields in Instruction Formats

1)

Operation Code Field

: specify the operation to be

performed

2)

Address Field

: designate a memory address or a

processor register

3)

Mode Field

: specify the operand or the effective

address (

Addressing Mode

)

The influence of the number of addresses on computer instruction we will evaluate with Three address instruction

Two address instruction one address instruction

Zero address instruction

X = (A + B)*(C + D) using

- 4 arithmetic operations : ADD, SUB, MUL, DIV

- 1 transfer operation to and from memory and general register : MOV

- 2 transfer operation to and from memory and AC register : STORE, LOAD - Operand memory addresses : A, B, C, D

- Result memory address : X

INSTRUCTION FORMATS

Three-address instructions:

ADD R1, A, B R1 ← M[A] + M[B] ADD R2, C, D R2 ← M[C] + M[D] MUL X, R1, R2 M[X] ← R1 * R2

Two-address instructions: MOV R1, A R1 ← M[A]

ADD R1, B R1 ← R1 + M[B]

MOV R2, C R2 ← M[C] ADD R2, D R2 ← R2 + D

MUL R1, R2 R1 ← R1 * R2 MOV X, R1 M[X] ← R1

The most common in commercial computers

Each address fields specify either a processor register or a memory

INSTRUCTION FORMATS

One-address instructions: LOAD A AC ← M[A]

ADD B AC ← AC + M[B] STORE T M[T] ← AC

LOAD C AC ← M[C]

ADD D AC ← AC + M[D] MUL T AC ← AC * M[T] STORE X M[X] ← AC

All operations are done between the AC register and memory operand

Zero-address instructions: PUSH A TOS ← A PUSH B TOS ←B ADD TOS ← (A +B) PUSH C TOS ← C PUSH D TOS ← D

ADD TOS ← (C + D)

MUL TOS ← (C + D) * (A + B) POP X M[X] ← TOS

Stack-organized computer does not use an address field for the

instructions ADD, and MUL

Machine organization is the view of the computer that is seen by the logic designer. This includes

Implementation, Capabilities &

performance characteristics of functional

units (e.g., registers, ALU, shifters, etc.).

Interconnections of these units

Information flows between these units

Control of information flow i.e.Logic and

means by which such information flow is

controlled

•

Design better programs,

including system software such

as compilers, operating systems,

and device drivers.

•

Optimize program behavior.

•

Evaluate (benchmark) computer

system performance.

THE VON NEUMANN MACHINE

The model for almost all

conventional processor

architectures. Comprises:

A

Memory

containing a numbered

sequence of cells

(words)

referenced by their

addresses

(

Linear Store

)

An

ALU

(

A

rithmetic

L

ogic

U

nit) to

perform operations (program steps)

using temporary storage cells

(registers)

A

Control Unit

to ensure an

The stored program concept was proposed about fifty years ago; to this day, it is the fundamental architecture

Von Neumann’s proposal was to store the program instructions right along with the data.

The von Neumann model states that

the program must be stored in memory.

The memory of modern computers

hosts both

A program

its corresponding data

A program is made of a finite number of

instructions.

The control unit

fetches one instruction from memory interpret it

execute it

The instructions are executed one after another.

Every computer today is based on the von Neumann Model. It is based on 3 ideas:

1. Four subsystems

2. Stored Program Concept

3. Sequential Execution of Instructions

von Neumann model

• _{Four subsystems:}

1. Memory – the storage area of programs and data.

2. ALU – arithmetic/logic operations take place

3. Control Unit – controls Memory, ALU, and I/O

PROGRAM STATEMENTS AND

COMPUTER INSTRUCTIONS

Computer instruction

Field specifying the operation to be

executed

Field specifying the data

In 1966, Michael Flynn proposed a classification for

computer architectures based on the number of

instruction steams and data streams (Flynn’s

Taxonomy).

Flynn uses the stream concept for describing a

machine's structure

A stream simply means a sequence of items (data or

instructions).

Instruction Stream

Sequence of Instructions read from memory

Data Stream

Operations performed on the data in the

processor

FLYNN’S CLASSIFICATION

OF COMPUTER

Flynn’s Taxonomy

SISD: Single instruction single data

– Classical von Neumann architecture

SIMD: Single instruction multiple data

MISD: Multiple instructions single data

– Non existent, just listed for completeness

MIMD: Multiple instructions multiple data

– Most common and general parallel machine

FLYNN’S CLASSIFICATION

OF COMPUTER

SISD (Singe-Instruction stream, Singe-Data stream)

SISD corresponds to the traditional mono-processor ( von Neumann computer). A single data stream is being processed

by one instruction stream.

SISD – Single Instruction Single Data Systems

FLYNN’S TAXONOMY

Characteristics

- Standard von Neumann machine

- Instructions and data are stored in memory - One operation at a time

Limitations

Maximum speed of the system is limited by the Memory Bandwidth (bits/sec or bytes/asec)

- Limitation on Memory Bandwidth

SIMD (Single-Instruction stream, Multiple-Data streams) Each instruction is executed on a different set of data by different processors i.e multiple processing units of the

same type process on multiple-data streams.

SIMD – Single Instruction Multiple Data Systems “Array Processors”

FLYNN’S TAXONOMY

SI

SISD

SISD

SISD

SD

SD

SD

Characteristics

- Only one copy of the program exists

- A single controller executes one instruction at a time

Examples:

MISD (Multiple-Instruction streams, Singe-Data stream) Each processor executes a different sequence of

instructions.

In case of MISD computers, multiple processing units operate on one single-data stream .

In practice, this kind of organization has never been used

MISD- Multiple Instructions / Single Data System

Multiple Instructions Single Data

FLYNN’S TAXONOMY

SI

SISD

SISD

SISD

SD

MIMD (Multiple-Instruction streams, Multiple-Data streams)

Each processor has a separate program.

An instruction stream is generated from each program. Each instruction operates on different data.

This last machine type builds the group for the traditional multi-processors. Several processing units operate on

multiple-data streams.

Characteristics

- Multiple processing units

- Execution of multiple instructions on multiple data

MIMD Multiple Instructions Multiple Data System:

“Multiprocessors”

Multiple Instructions Multiple Data

SI

SI

SI

SISD

SISD

SISD

SD

SD

Processor Organizations

COMPUTER ARCHITECTURE

CLASSIFICATIONS

Single Instruction, Single Instruction, Multiple Instruction Multiple Instruction

Single Data StreamMultiple Data Stream Single Data Stream Multiple Data Stream

(SISD) (SIMD) (MISD) (MIMD)

Uniprocessor Shared Memory Multicomputer

THE COMPUTER LEVEL HIERARCHY

MULTILEVEL MACHINES

Digital Logic Level

 This level is where we find digital circuits (the chips).

 Digital circuits consist of gates and wires.

The next level up is the M

icroarchitecture

level

At this level we see a collection of (typically) 8 to 32

registers that form a local memory and a circuit

called an

ALU

(

Arithmetic Logic Unit

) capable of

performing simple arithmetic operations.

Control Level

A

control unit

decodes and executes instructions and

moves data through the system.

Control units can be

microprogrammed

or

hardwired

.

•

A microprogram is a program written in a low-level

language that is implemented by the hardware.

•

Hardwired control units consist of hardware that

directly executes machine instructions.

Architecture (ISA) level.

This level consists of the instructions that can be

carried out by the computer.

Programs written in machine language need no

compilers, interpreters, or assemblers.

System Software Level or O

perating system

level

Controls executing processes on the system.

Protects system resources.

Assembly Language Level

Acts upon assembly language produced from Level

5, as well as instructions programmed directly at

this level.

The User Level

Program execution and user interface level.

The level with which we are most familiar.

High-Level Language Level

The level with which we interact when we write

programs in languages such as C, Java and more.

Programs written in these languages are translated

to level 3 or 4 languages by translators known as

compilers

.

A computer’s native language, machine language, is difficult for

human’s to use to program the computer

Due to this difficulty, computers are often structured as a series of

abstractions, each building on the one below it

In this way, complexity can be mastered

This approach is called

structured computer organization

ALU (Arithmetic Logic Unit )

Control unit

General purpose register,

Instruction registers

There are several ways to place these components

and interconnect them.

Arithmetic and logic unit (ALU), and all CPU

registers are connected via a single common

Internal bus

Bus is used to transfer the information between

different components of the CPU and termed as

Single bus organization

External bus to CPU connect the CPU with the

memory module and I/O devices

Registers

The Registers are very fast storage locations inside the processor itself. There are many registers including :

• _{memory address register (MAR) –}

holds the address of a location in memory

• _{memory data register (MDR) – holds}

data just read from or written to memory

• _{program counter (PC) – holds the}

address of the next instruction to be fetched

• _{Instruction register (IR) – holds the}

current instruction being executed

• _{general purpose registers – can be}

(k

x

m)

array of stored bits (

k

is

usually 2

)

Address

unique (n-bit) identifier of location

Contents

m-bit value stored in location

Basic Operations:

LOAD

read a value from a memory location

STORE

write a value to a memory location

How does processing unit get data

to/from memory?

MAR: Memory Address Register

MDR: Memory Data Register

•

To read a location (A):

1. Write the address (A) into the MAR.

2. Send a “read” signal to the memory.

3. Read the data from MDR.

•

To write a value (X) to a location (A):

1. Write the data (X) to the MDR.

2. Write the address (A) into the MAR.

3. Send a “write” signal to the memory.

INTERFACE TO MEMORY

MEMORY

MAR

MDR

Functional Units

ALU = Arithmetic and Logic Unit could have many functional units.

some of them special-purpose (multiply, square root, …)

Registers

Small, temporary storage

Word Size

number of bits normally processed by ALU in one instruction

also width of registers

PROCESSING UNIT

PROCESSING UNIT

PROCESSING UNIT

The internal part of

the CPU consists of data paths connecting

registers and the ALU

The ALU performs simple arithmetical/logic

operations (ADD, AND,OR)

It takes its operands from the registers and store the result back in them

The process of reading operand and storing result back is called data-path cycle

The faster the data-path cycle is the faster the computer runs

ALU AND THE DATA-PATH

Orchestrates execution of the program

Instruction Register (IR) contains the

current

instruction

.

Program Counter (PC) contains the

address

of the next instruction to be executed.

Control unit:

reads an instruction from memory

the instruction’s address is in the PC

that tell the other components what to do

an instruction may take many

machine

cycles

to complete

CONTROL UNIT

CONTROL UNIT

Devices for getting data into and out of

computer memory

Each device has its own interface,

usually a set of registers like the

memory’s MAR and MDR

INPUT AND OUTPUT

I N P U T K e y b o a r d M o u s e S c a n n e r D i s k

Machine cycle

The CPU uses repeating

machine cycles

to

execute instructions in the program, one by

one, from beginning to end. A simplified cycle

can consist of three phases:

fetch

,

decode

and

Processing the instructions

•

Computers, uses machine cycles.

•

A cycle is made of three phases: fetch, decode

and execute.

•

Fetch phase

: the instruction whose address is

determined by the PC is obtained from the

memory and loaded into the IR. The PC is then

incremented to point to the next instruction.

•

Decode phase

: the instruction in IR is

decoded and the required operands are fetched

from the register or from memory.

•

Execute phase

: the instruction is executed

Memory hierarchy

LEVELS IN MEMORY

HIERARCHY

Memory diskdisk

Register _Cache

Memory _{Disk Memory}

PRINCIPLE OF LOCALITY is the tendency to reference data items that are near other recently referenced data items, or that were recently referenced themselves.

• TEMPORAL LOCALITY : memory location that is

referenced once is likely to be referenced multiple times

in near future.

• SPATIAL LOCALITY : memory location that is referenced once, then the program is likely to be reference a nearby memory location in near future.

Principle of locality helped to speed up

main memory access by introducing small

fast memories known as CACHE

MEMORIES that hold blocks of the most

recently referenced instructions and data

items.

Cache is a small fast storage device that

holds the operands and instructions most

likely to be used by the CPU.

A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access

memory.

Smaller, faster memory which stores copies of the data from the most frequently used main memory locations. As long as most memory accesses are cached memory

locations, the average latency of memory accesses will be closer to the cache latency than to the latency of main

memory.

CACHE

CPUs can have at least three independent caches:

•

Instruction cache

to speed up executable

instruction fetch

•

Data cache

to speed up data fetch and store,

•

Translation lookaside buffer

(TLB) used to

RAM (Random Access Memory )

Types of Main memory

DRAM : Dynamic random-access memory

SRAM : Static random Access Memory

The word 

static

 indicates that the memory retains

its contents as long as power is being supplied.

However, data is lost when the power gets down

due to volatile nature.

It has long life

There is no need to refresh

Faster

Used as cache memory

Large size

Expensive

High power consumption

DRAM, unlike SRAM, must be

continually 

refreshed

 in order to maintain the data.

This is done by placing the memory on a refresh

circuit that rewrites the data several hundred times

per second.

It has short data lifetime

Need to be refreshed continuously

Slower as compared to SRAM

Used as RAM

Less expensive

Less power consumption

MAGNETIC DISKS(SECONDARY

STORAGE )

The read/write head floats

over the disk surface and moves back

and forth on an arm from track to track.

Disk surface spins at

3600–7200 RPM _{read/write head}

arm

The surface consists of a set of

concentric

magnetized rings called tracks