The CPU Control Unit

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Lecture # 20: Control Unit Design and Multicycle Implementation © N. B. Dodge 09/07

The CPU Control Unit The CPU Control Unit

• We now have a fairly good picture of the logic circuits in the CPU.

• Having “designed” the ALU or datapath so that it can perform the necessary instructions, we now have to do the same thing for the control unit, which decodes

instructions and provides direction to the CPU.

• The MIPS control unit decodes the six bits on either end of the 32-bit instruction word, that is, the op code **and function code* fields, to determine each instruction sequence.**

* On R-R instructions.

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The Central Processor Unit (CPU) The Central Processor Unit (CPU)

• In lecture 19, we covered processing elements (blue), including the registers, ALU, and data buses.

• We now address the control unit circuitry (red).

– Instruction decoding.

– Control signals to ALU and other control elements.

ALU

Instruction Fetch/Decode Control Unit

Registers

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Functionality of Control Unit Functionality of Control Unit

• The control unit determines ALU functions in each instruction and selects operands for the ALU.

• The operation code (the left six bits of the instruction) determines the type of operation and in some cases (such as jump instructions) the actual instruction itself.

• In the case of register-register instructions, the function code determines the instruction (for example, in the R/R instruction above, the function code 0x 20 means “add”).

00 0000 0 1000 0 1001 0 1010 0 0000 10 0000

Op. code $t0 $t1 $t2 Shift amt.

Bit 0

Bit 31 Fn. code

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Functionality of Control Unit (2) Functionality of Control Unit (2)

• As mentioned before, the control unit is a collection of decoders and multiplexers.

• The decoded

instruction fields tell (1) the ALU what function to perform, (2) what operands to

use.

⁰⁰

0000 0 1000 0 1001 01010 0 0000 10 0000

To shift amount decoder To dest. reg. decoder

Bit 31

Bit 0 To function code

decoder

To operation code decoder

To source 2 reg. decoder

To source 1 reg. decoder

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Current Architecture Current Architecture

• The ALU control uses instruction bits 0-5 to obtain information about the ALU operation in register-to- register instructions.

• Note in the following diagram that some of the

decoding is done in the register block, which has the decoding mechanism (as discussed in lecture 8, slides 8 and 9) that identifies source and destination registers in load/store and register/register operations.

• The ALU control also has input control lines from the

operation code decoder which decodes bits 26-31, and

which will be shown later.

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ALU Design with ALU Control Block Shown ALU Design with ALU Control Block Shown

ADD

P

ALU

C

+4

Instruction Address

M U X Left shift 2

Data Address Inst.

0-31 M

U

Reg. Block X Rs

Rt

Rd Write Data

Read Data 1 Read Data 2

Sign Extend

32

Write Data

Read Data

Instruction bits 0-31

16 (Bits 0-15)

32 32

32

32 32

32

32 32

32

32 5

5 5

ALU Control

Instruction Memory

Data Memory M

U X 5

6 (Bits 0-5)

M U X

ADD

ALU Control Block (function code/

op code decoder)

32

After David A. Patterson and John L. Hennessy, Computer Organization and Design, 2nd Edition

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ALU Control Block ALU Control Block

Function code (instruction bits 0-5)

3-bit ALU control bus ALU operation

bits from op code control unit

ALU Control Block Detail

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Mem. To Reg.

ALU Op.

Branch

Reg. Write ALU Srce.

Mem. Read

ADD

P

ALU

C

+4

0-31 M

U

Reg. Block X Rs

Rt

Sign Extend

32

Write Data

Read Data

16 (Bits 0-15)

32 32

32

32 32

32

32 32

32

32 5

5 5

ALU Control Control

U X 5

6 (Bits 0-5)

Reg. Dest.

Mem. Write

6 (Bits 26-31)

M U X

ADD

Read Write

Mem./Reg.

Select

Single-Cycle ALU Design with Full Control Blocks Single-Cycle ALU Design with Full Control Blocks

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Op Code Control Block Signal Identifier Op Code Control Block Signal Identifier

Op code decode/

control block

“RegDst” – Register destination control (MUX input)

“Branch” – Activates branch address change function

“MemRead” – Signals read cycle to data memory circuits

“MemtoReg” – Selects ALU or memory write to register

“ALUOp” (2 lines) – Used with function code in ALU control

“MemWrite” – Signals write cycle to data memory circuits

“ALUSrc” – Selects register and immediate ALU operand

“RegWrite” – Activates write function to register block

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Function of Op Code Control Signals Function of Op Code Control Signals

Signal Name When Signal = 1 When Signal = 0 RegDst Write reg. = $rd (bits 11–15) Write reg. = $rt (bits 16-20)

Branch ALU branch compare activated No branch activated

MemRead Memory data → write register No data read from memory

MemtoReg Memory data → write register ALU results → write register

ALUOp NA; lines go to ALU control block NA; lines go to ALU control block

MemWrite ALU or register data → memory No data written to memory

ALUSrc 2nd ALU operand is immediate (sign-extended instr. bits 0-15)

2

^nd

ALU operand is from $rt (instruction bits 16-20)

RegWrite Memory/ALU data → write reg. No input to register block

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Op Code Control Block Circuitry Op Code Control Block Circuitry

Instruction bits 26-31

TO ALU control block

“0” “23” “2a” “04”

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Instruction Disposition Showing Destination Units Instruction Disposition Showing Destination Units

00 0000 0 1000 0 1001 01010 0 0000 10 0000

Bit 31 Bit 0

To $rd destination register decoder To $rt source register decoder

To $rs source register decoder To shift amount decoder (ALU)

ALU Control

Block

TO ALU Control Block

TO Operation Code Control Block

^Op

Code Control

Block

Register Block

$rs decode

$rd decode

$rt decode

Registers

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Data/control Signal Flow Examples Data/control Signal Flow Examples

• The following diagrams illustrate the flow of control signals and data in some example MIPS instructions in the single cycle

implementation.

• The “single cycle” implementation is just a stepping stone to the final MIPS design, but this simpler example has all the features of the more complex final design in terms of data routing and the way in which the control signals determine the specific operation for each given instruction.

• Note the data flow in these instructions, and pay special attention

to the way some of the combinational devices we studied, such as

the decoder and multiplexer, are utilized extensively.

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Start of R-Type Instruction Start of R-Type Instruction

Instruction is fetched

Mem. To Reg.

ALU Op.

Branch

Mem. Read

ADD

P

ALU

C

+4

0-31 M

U

Reg. Block X Rs

Rt

Sign Extend

32

Write Data

Read Data

16 (Bits 0-15)

32 32

32

32 32

32

32 32

32

32 5

5 5

U X 5

6 (Bits 0-5)

Reg. Dest.

Mem. Write

6 (Bits 26-31)

M U X

ADD

Read Write

Mem./Reg.

Select

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Next Step of R-Type Instruction Next Step of R-Type Instruction

Registers are identified and needed operands are routed to the ALU and the PC update circuit.

Mem. To Reg.

ALU Op.

Branch

Mem. Read

ADD

P

ALU

C

+4

0-31 M

U

Reg. Block X Rs

Rt

Sign Extend

32

Write Data

Read Data

16 (Bits 0-15)

32 32

32

32 32

32

32 32

32

32 5

5 5

U X 5

6 (Bits 0-5)

Reg. Dest.

Mem. Write

6 (Bits 26-31)

M U X

ADD

Read Write

Mem./Reg.

Select

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Third Step of R-Type Instruction Third Step of R-Type Instruction

Mem. To Reg.

ALU Op.

Branch

Mem. Read

ADD

P

ALU

C

+4

0-31 M

U

Reg. Block X Rs

Rt

Sign Extend

32

Write Data

Read Data

16 (Bits 0-15)

32 32

32

32 32

32

32 32

32

32 5

5 5

U X 5

6 (Bits 0-5)

Reg. Dest.

Mem. Write

6 (Bits 26-31)

M U X

ADD

Read Write

Mem./Reg.

Select

ALU operation is selected and performed.

The ALU output is routed to write

select MUX.

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Completion of R-Type Instruction Completion of R-Type Instruction

Mem. To Reg.

ALU Op.

Branch

Mem. Read

ADD

P

ALU

C

+4

0-31 M

U

Reg. Block X Rs

Rt

Sign Extend

32

Write Data

Read Data

16 (Bits 0-15)

32 32

32

32 32

32

32 32

32

32 5

5 5

U X 5

6 (Bits 0-5)

Reg. Dest.

Mem. Write

6 (Bits 26-31)

M U X

ADD

Read Write

Mem./Reg.

Select

With the write register line active, data is written back to the destination register.

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Load Instruction Load Instruction

Mem. To Reg.

ALU Op.

Branch

Mem. Read

ADD

P

ALU

C

+4

0-31 M

U

Reg. Block X Rs

Rt

Sign Extend

32

Write Data

Read Data

16 (Bits 0-15)

32 32

32

32 32

32

32 32

32

32 5

5 5

U X 5

6 (Bits 0-5)

Reg. Dest.

Mem. Write

6 (Bits 26-31)

M U X

ADD

Read Write

Mem./Reg.

Select

Instr. lines Data store path

The word addressed in memory is written back to the identified write register

Immediate Address data Read address

The load instruction identifies the register containing the address, the

“immediate,”and the write register

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Branch Instruction Branch Instruction

Mem. To Reg.

ALU Op.

Branch

Mem. Read

ADD

P

ALU

C

+4

0-31 M

U

Reg. Block X Rs

Rt

Sign Extend

32

Write Data

Read Data

16 (Bits 0-15)

32 32

32

32 32

32

32 32

32

32 5

5 5

U X 5

6 (Bits 0-5)

Reg. Dest.

Mem. Write

6 (Bits 26-31)

M U X

ADD

Read Write

Mem./Reg.

Select

PC+4 Addr.

Immediate

Instruction lines New PC address

Active control lines Register data

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Lecture # 20: Control Unit Design and Multicycle Implementation © N. B. Dodge 09/07 After David A. Patterson and John L. Hennessy, Computer Organization and Design, 2nd Edition

Mem. To Reg.

ALU Op.

Branch

Mem. Read

ADD

P

ALU

C

+4

0-31 M

U

Reg. Block X Rs

Rt

Sign Extend

32

Write Data

Read Data

16 (Bits 0-15)

32 32

32

32 32

32

32 32

32

32 5

5 5

U X 5

6 (Bits 0-5)

Reg. Dest.

Mem. Write

6 (Bits 26-31)

M U X

ADD

Read Write

Mem./Reg.

Select

M U X

32 Left

shift

2 PC+4 (Bits 28-31)

Instruction Bits 0-25

Jump

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Lecture # 20: Control Unit Design and Multicycle Implementation © N. B. Dodge 09/07 After David A. Patterson and John L. Hennessy, Computer Organization and Design, 2nd Edition

Mem. To Reg.

ALU Op.

Branch

Mem. Read

ADD

P

ALU

C

+4

0-31 M

U

Reg. Block X Rs

Rt

Sign Extend

32

Write Data

Read Data

16 (Bits 0-15)

32 32

32

32 32

32

32 32

32

32 5

5 5

U X 5

6 (Bits 0-5)

Reg. Dest.

Mem. Write

6 (Bits 26-31)

M U X

ADD

Read Write

Mem./Reg.

Select

M U X

32 Left

shift

2 PC+4 (Bits 28-31)

Instruction Bits 0-25

Jump

PC+4 data PC jump data

PC update Jump control

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Exercise 1 Exercise 1

• On the next slide is a diagram of the complete

“single-cycle” preliminary MIPS architecture.

On a copy of that diagram:

1. Circle every element that contains a decoder.

2. Highlight the line that controls the content of the data written back to the destination register.

3. Circle the device that allows a 16-bit number to be

successfully added to a 32-bit number.

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Mem. To Reg.

ALU Op.

Branch

Mem. Read

ADD

P

ALU

C

+4

0-31 M

U

Reg. Block X Rs

Rt

Sign Extend

32

Write Data

Read Data

16 (Bits 0-15)

32

32 32

32

32 32

32

32 5

5 5

U X 5

6 (Bits 0-5)

Reg. Dest.

Mem. Write

6 (Bits 26-31)

M U X

ADD

Read Write

Mem./Reg.

Select

Print out a copy of this diagram and bring to class.

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Making the ALU More Efficient Making the ALU More Efficient

• We have now completed “design” of the basic MIPS R-2000 CPU.

• Although a good basic design, it has a serious drawback:

– Our processor is designed so that all instructions complete in one clock cycle.

– While this assures that there is sufficient time to complete any

instruction, it also means that one clock period must be long enough to accommodate the longest and most complicated instruction.

– Thus, ALL instructions take as long as the longest instruction.

• Since many (most!) instructions in the MIPS architecture take less time to execute than the longest instructions (which are usually the lw memory reference instructions), this means that we are slowing execution of our CPU a large part of the time to accommodate

instructions that occur substantially less frequently.

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Comparative Instruction Timing Comparative Instruction Timing

One clock cycle (= one instruction cycle) PC update time

Instructions accessed and inputs to register and op decoders stable Op and function codes decoded and stable

Register outputs (operands) stable ALU processing complete Memory accessed and data storage or read complete

Data written to write (destination) register if necessary Jumps and branches completed about here

Register-register instructions done about here

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Multicycle Implementation Multicycle Implementation

• A solution to the single-cycle problem is stated as follows:

– Each instruction has several phases, such as fetch/decode, register selection, ALU processing, etc.

– Instead of using a single clock cycle for the whole instruction, run the clock much faster, and have a single clock cycle for each of the elements or phases of the instruction process.

– Many instructions take fewer phases (for example, jump, branch [the fewest phases], register-register or store

instructions), so these instructions execute much faster.

– As most instructions execute faster than the longest

instructions (such as lw), the average instruction time will be

reduced substantially.

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MIPS Multicycle Concept MIPS Multicycle Concept

• Split the processing into five processing segments.

• Run the clock much faster (essentially 5X faster!).

• Do one instruction segment per clock cycle.

• PC updates, branches and jumps take 3 processing

segments since they are simpler; they run much faster.

• Register-register instructions do not require memory access. They take four instruction segments and finish in about 30% more time than jumps and branches.

• Only load memory-access instructions take a full five

processing segments (store takes only four), but do not

slow down the other instructions to their speed.

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Multicycle Implementation Multicycle Implementation

Instruction Fetch

Instruction Decode/

Register Fetch

ALU Execution

Memory Access

(if required)

Data Writeback

P C

Register Block

Op/Fn

ALU Data

Memory

Register Block

1 clock cycle

1 clock cycle Skipped for

store inst.

Skipped for reg.-reg. inst.

Skipped for jump and branch instructions

All five segments (five clock cycles) required only for load instructions

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Instruction Cycle Times Instruction Cycle Times

Instruction Step

R- Type

Memory

Reference Branches Jumps

Instruction Fetch

Fetch instruction at address [PC]

[PC]→[PC+4]

Instruction Decode /Register

Fetch

Register operands fetched; Instruction decoded and control unitsactivate appropriate ALU components

Instruction Execution

ALU output = result of operation on register operand(s)

ALU output is mem. address for

load/store

If condition met, [PC]→address output of ALU

PC address is instr.

[0-25] (shifted 2 places) + [PC 28-31]

Memory Access or ALU Data Writeback

Logical/shift/math operation result written to dest. reg.

Reg. data stored or data accessed for

load to dest. reg.

--- ---

Memory Data Writeback

--- Data written to

destination register

--- ---

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Multicycle Advantages Multicycle Advantages

• For most instructions, we save 20-40% in clock cycles and our processor is much faster, as mentioned earlier.

• Since different parts of the circuit are active only for one cycle at a time, we can use less circuitry because parts of the computer can be reused in different cycles.

– The CPU now needs only one ALU, since it can do the PC update functions prior to the ALU processing.

– Since we access memory for data and instructions in different

clock cycles, we only need one path to memory.

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Major Impediment to Multicycle Implementation Major Impediment to Multicycle Implementation

• Our multicycle processor takes up to 5 clock cycles to complete an instruction.

• Each time the clock ticks, part of the instruction is completed, not all of it.

• That means that at the end of each clock cycle, we have partial instruction results, but no place to store them!

• A first concern is therefore a way to store intermediate data as the instruction winds its way through the

various segments of processing.

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Intermediate Results Storage Requirements Intermediate Results Storage Requirements

Mem. To Reg.

ALU Op.

Branch

Mem. Read

ADD

P

ALU

C

+4

0-31 M

U

Reg. Block X Rs

Rt

Sign Extend

32

Write Data

Read Data

16 (Bits 0-15)

32 32

32

32 32

32

32 32

32

32 5

5 5

U X 5

6 (Bits 0-5)

Reg. Dest.

Mem. Write

6 (Bits 26-31)

M U X

ADD

Read Write

Mem./Reg.

Select

Need instruction

storage here Need operand storage here Need ALU out storage here Need

read data storage

here

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First-Pass Register Placement First-Pass Register Placement

ALU ^ALU^Out

Memory Address

Memory Out

Memory Write

Data

Instruction Register

Instr. 0-15

Memory Data Register

Instruction 0-31

Reg. Block

Write Data Read Data 1 Read Data 2 Rs

Rt

Rd

A

Inst. B

11-15 Instr.

21-25 Instr.

16-20

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Preliminary Multicycle Design Without Control Preliminary Multicycle Design Without Control

ALU ^ALU_Out

M U X Memory

Address

Memory Out

Data

Instr. 0-15

Reg. Block

Rt

Rd

A

Ins. B

11- 15

4

Sign Extend

Left shift 2 M

U X

Instr. 0-5 Instr.

21-25 Instr.

16-20

M U X

Note memory data path simplified

ALU now serves jump/branch PC update function

• Our preliminary multicycle processing design is more compact.

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Multicycle Design with ALU Control and PC Multicycle Design with ALU Control and PC

P

C

_ALU

ALU Control

ALU Out

M U X M

U X

Memory Out

Data

Instr. 0-15

Reg. Block

Rt

Rd

A

Ins. B

11- 15

4

Sign Extend

U X

21-25 Instr.

16-20

PC 0-31

M U X

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Completed Multicycle Design

ALU Op.

Reg. Write ALU Srce. B

P C

Left shift 2

ALU

Reg. Dest.

PC Source

M U X

ALU Out

M U X

PC Write Cond.

PC Write

M U X

Inst. / Data

Mem. Write Mem. To. Reg.

Inst. Reg. Write Mem. Read

ALU Srce. A

Memory Out

Data

Instr. 26-31

Instr. 0-15

Reg. Block

Rt

Rd

A

Ins. B

11- 15

4

Sign Extend

U X

21-25 Instr.

16-20

PC 0-31

M U X

PC 28-31

Instr. 0-25

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Multicycle Summary Multicycle Summary

• We have redesigned the MIPS CPU to accommodate a 5-segment instruction partition with each segment taking one clock cycle.

• In doing so, instruction execution time was decreased ~ 30-40%

and greater efficiency was obtained by reducing the circuitry.

• In the next lecture, we will take the final step in the MIPS design and complete the R2000 architecture.

P

C ALU

Memory Reg.

A B

ALU Op.

Cont.

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Exercise 2 Exercise 2

• On the Complete Multicycle Design Diagram on the next page, do the following:

1. Summarize the inputs into the lower MUX to the ALU.

2. Why is the 16-bit sign-extender input directly to the ALU in one case and left-shifted two places in the other?

3. Why is the output of the ALU sent directly to the

MUX that inputs an instruction address into the

PC?

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ALU Op.

Reg. Write ALU Srce. B

P C

Left shift 2

ALU

Reg. Dest. M

U X

ALU Out

M U X

PC Write

M U X

Inst. / Data

Mem. Write Mem. To. Reg.

Inst. Reg. Write Mem. Read

ALU Srce. A

Memory Out

Data

Instr. 26-31

Instr. 0-15

Reg. Block

Rt

Rd

A

Ins. B

11- 15

4

Sign Extend

U X

21-25 Instr.

16-20

PC 0-31

M U X

PC 28-31

Instr. 0-25

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The CPU Control Unit