Reversible Circuits using Heuristic Approach

International Journal of Emerging Technology and Advanced Engineering

76

Reversible Circuits using Heuristic Approach

Srikanth Ganta

, Y. Ramesh Kumar

, Golthi Venkata Gautam

1 _{M.Tech II Year, Avanthi Institute of Engineering & Technology, Cherukupalli, Andhra Pradesh} 2

Head of the Department , Department of CSE, Avanthi Institute of Engineering & Technology,Cherukupalli, Andhra Pradesh

3_{M.V.G.R. College of Engineering, Chintalavalasa, Andhra Pradesh}

Abstract— In this paper we are introducing a novel technique that reduces the number of gates that are intended for developing circuits. As per our proposal we can able to develop minimum information lossless circuits and named as reversible circuits. We are using an algorithm that is used depends on selective iterative deepening which is an iterative depth first search. Reversible circuit can be worked as takes both input and output. It finds the optimality and it can be decided. Also we used priority approach that prunes half of the tree before the search begins. Final results will be a optimal sequence of gates used to design circuit.

Keywords— Reversible circuits, multi branched tree, Toffoli gates, circuits, depth first search

I. INTRODUCTION

With the computer industry keeping pace with Moore‟s law, energy consumption has become the center of attention in digital circuit design after performance. Landauer‟s principle states that any logic computation that is not Reversible (i.e., information lossless) will dissipate a certain amount of energy for every bit of information lost regardless of the technology chosen for implementation. Today, this energy is small compared with other forms of heat dissipation. However, with the exponential packing of transistors on a chip, this energy is expected to play a dominant role in the next one to two decades reversible logic finds many applications, especially in the area of quantum computing or information-lossless circuits have applications in digital signal processing, communication, computer graphics and cryptography [1]. A completely specified n-input, n-output Boolean function is called reversible if it maps each input assignment to a unique output assignment and vice versa. Logic synthesis for reversible functions differs substantially from traditional logic synthesis and is currently an active area of research.

A major new motivation for the study of reversible circuits is provided by the emerging field of quantum computation. In a quantum circuit the operations are performed on quantum states or qubits rather than bits [6]. Since quantum evolution is inherently reversible, the resulting quantum computation is as well.

Classical reversible circuits form an important subclass of these quantum circuits.

The algorithm utilizes a Gate priority based search tree. The synthesis algorithm currently targets the generalized n -bit Toffoli gate library. Experimental results indicate that the algorithm quickly synthesizes circuits when tested on the set of all reversible functions of three variables. Furthermore, it is able to quickly synthesize all four -variable and most five--variable reversible functions that were in the test suite.

1. 1REQUIREMENTS

1. Turbo C Compiler for Windows XP/7 (or)

2. GCC Compiler for Ubuntu 10.10

1. 2CNT Library and Gates

A logic gate is reversible if the mapping of inputs to outputs is bijective, that is, every distinct input yields a distinct output, and the numbers of input and output wires are equal. If it has k inputs (and outputs), we call it a

reversible k×k gate. Three commonly used gates, composing the NCT-gate library, are shown in

A well-formed reversible circuit is constructed by starting with n wires, forming the basic circuit, and iteratively concatenating reversible gates to some subset of the output wires of the previous circuit. The outputs of each reversible gate replace the wires at its input.

Figure1: (a) A Not Gate, (b) A Two Variable CNOT

(c) A Three variable CNOT

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1.2.1 Different Kinds of Gates 1.Toffoli Gates

In Toffoli Gate, all the inputs from 1 to (n-1) are passed as outputs. The nth output is controlled by 1 to (n-1) inputs. When all the inputs from 1 to (n-1) are 1s, the nth input is inverted and passed as output else original signal is passed. A 3-input, 3-output Toffoli gate is shown in Fig 2.

This Algorithm uses Toffoli Gates for the Synthesis of Reversible Circuits with creation and the optimization of Gates for a given output permutation.

2.Fredkin Gates

The Fredkin gate is shown in the Fig 2. Here the input „a‟ is passed as first output. Inputs b and c are swapped to get the second and third output which is controlled by „a‟. Thus two inputs can be swapped by controlling the swap using another input in Fredkin Gate.

1.2.2 Creation of a Toffoli Gate

In order to create a Toffoli Gate [6], one need to know the position of NOT Gate and the positions of the connected lines to the NOT gate.

The position of the Not Gate (in line) is specified through variable „i‟ in the algorithm.

The positions of the connected lines are specified through the binary number given through „j‟ in the algorithm.

Based on value of „i‟ the value of „j‟ is rotated left shift and the resultant number is used to create a gate.

1. 3Creating a Set of Gates for a given value ‘n’

For a Given value „n‟ there exists n*2^(n-1) gates .The gates are created from 0 to n*2^(n-1).The output permutation from all gates will be stored in a “out array” along with the gate number. “-1” is the separator between output permutation and gate number. For a given number calculate it binary number and reverse it perform left shift based on position of NOT in toffoli gate [5]. Except NOT gate, 1‟s represent the connection line to NOT and 0‟s represent the NO Connection to NOT.

Algorithm for Creating set of gates

1.Allocate Dynamic memory for all input and output buffers used in Code

2.Initialize all the input and output buffers to zero 3.for every value of j from step 3-11

bin <- binary number(j)

// Calculate binary number of j bin<-reverse(bin,n-1) // reverse binary number rotate=rleft_shift(bin,n-1,i);

//(perform rotate left shift if i>=1) count1=count(rotate,n-1);

//count number of 1‟s present in it along with positions

4.top value stores the no of 1‟s present in bin and count1 array stores the positions of 1‟s present in bin array

5.if top=-1 then there is NO „1‟ in bin array results to NO connection to CNOT. Based on the value of „i‟ the NOT gate position on the line will be decided. And only NOT operation performed.

6.if top=0 there is only one connection and XOR performed between NOT and its connected line to NOT

7.if top>0 then there is more than one connection to CNOT gate from other input lines.

8.if top>0 then

c=AND(num_bin,count1);

//performed AND operation to all bits (which are // given as input(k) )are logically connected to CNOT

9.buff=XOR(num_bin[l],c);

// store the decimal value in out array

10.repeat step 5-9 for all values of k>=0 to k<2^n; 11.out=buff // storing the data in the out array 12.repeat step 3-12 for i>=0 and i<n

13.print the out array r=2^(n-1); m=2^n;

Time complexity for Creating Gates: O(n*r)

Time Complexity for getting the Output permutations from all the gates:

International Journal of Emerging Technology and Advanced Engineering

78 OUTPUT: n=2

It has 4 gates i.e., 0 to 4 n=3 value:

It has 12 gates from 0 to 11

II. OUTPUT PERMUTATION FROM ACOMBINATION OF

TOFFOLI GATES

The Combination of gates can be done by specifying the gate numbers and the input permutation. The Output Permutation from one gate will be given as input permutation to another gate and the combination output permutation from the gates will be obtained [2] .

The Algorithm for the Combination of Toffoli gates is:

1. Specify the gate numbers in a “gate” array 2. for each l in gate

for each k in out and gate[l] = out[i][j][m+1] // gate number in out

buff[l][k]=out[i][j];

//output permutation is stored in buff 3. for each l in gate

4. b =buff[l][ buff[l-1] ]

// output of l-1 gate is input to l gate and its value stored

5. buff[l]=b;

// store the contents of b in buff[l] makes piping 6. Repeat Steps 3-5 until all gates completed.

7. Print „b‟ the combinational output from given gates.

Time Complexity: O (n^2)

III. CALCULATING THE OPTIMAL NO OF GATES FOR A GIVEN OUTPUT PERMUTATION.

For a given Output permutation, in order to calculate the optimal no of gates within a solution space tree, we need gates which are used in a permutational fashion. The Data Structure used is Iterative Deeping DFS Algorithm (IDA) [4] has a time complexity of O (bd)

Where b= Branching Factor and d= depth of a shallowed goal.

3.1 Calculating the Permutations of a given value ‘n’

In order to calculate the permutations we need to have no of primary gates(n) ( gates at level 1) and level (L) and the Gate (G) to which the combinations has to be obtained [4] .

Eg: 1. If no of primary gates are 4 (0, 1, 2, 3) and Level is 2 and Gate is 0 then required combinations for Gate 0 are 01, 02, 03

Eg: 2. If no of primary gates are 4 (0, 1, 2, 3) and Level is 3 and Gate is 0 then required combinations for Gate 0 are 010, 012, 013, 020,021,023, 030,031,032

Algorithm for Calculating Permutations

1.To Calculate all the values of a Permutation we require 3^ (n-2) Two Dimensional Array (c)

2.Each 2D array is of (size-1)X(n) where size=no of gates and n=level

3.trace [] =0; r= 3^(n-2) 4.for each K to 0 dec 5.for each i to r 6.for each j to size-1

7.if(k==n) then c[i][j][n-k] <- g; // placing initially the gate „g‟

8.if(k!=1) then // placing the gate other than before one

9.for x=0 to size if( c[i][j][n-k-1]!=a[x]) then l=a[x]; 10.if( i < 3^(k-2)) c[i][j][n-k]=l;

11.if(k==1)

12.for x=0 to size if(c[i][j][n-k-1]!=a[x]) then c[i][j][n- k]=l;

13.Repeat 5-11 14.repeat 4-12 15.repeat 3-13 16.return c

International Journal of Emerging Technology and Advanced Engineering

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3.2 Searches for an Output Permutation in Solution Space (Without Heuristic)

The given output permutation is searched in solution

space tree. The Algorithm used is Iterative Deeping

Breadth first search where every permutation in each level is checked and level is incremented if search for output permutation is not found [2]. The number of permutations present in each level is (2^n)*(3^ (L-1)). Eg: n=2 if level is 1 then there are 4 permutations and if level is 2 then there are 12 permutations.

If the output permutation given by the user is matched with the permutations in the tree then the gates which are used to find the permutation will be printed

The different combinations of gates to a particular gate („g‟) are calculated at each level through above algorithm[3.1] and the combinational output from the gates are done based on algorithm[2.0] which is checked with the given output permutation.

Initially the for a given value of n , no of gates are calculated through Algorithm[1.3] and Level is 1 is checked for matching the output permutation in solution space tree [Level 1].

If it Fails in level 1, For Level 2 different Permutation for a given gate g will be calculated and combination effect of output from those permutations will be calculated and checks for a match .This procedure is repeated for all the gates present in the level L.

If if founds it displays the Gate combination else if increases the level and the continues repeating the above procedure.

The code works till the Level value=5 and the remaining levels are pruned.

Algorithm for searching an output permutation in Solution space

1. input <- 0 to 2^n; output <- {user given}; m <- 2^n; flag=0;

2. while (level <4)

3. L <- 3^ (level -2); g <-0; 4. while (g < m)

5. {gate <- perm (input, 2^n, L, g)

// g is the gate no to which diff comb. Of gates at level L is assigned to gate array

6. for i to L 7. {for j to m-1

8. {buff=sel_push (out, n, gate[i] [j], level);

// permutation data present at gate [i][j] is stored in buff

9. buff1=club (buff, level, m); // piping is done between gates data

10.if (cmp (buff1, output) then print “Found at gate”+gate*i+*j+; flag=1;

11.}} 12.}

13.repeat 2-11

14.if (flag=0) print “not found”;

Time Complexity: O (n*2^ (2n-1))

3.3 Searches for an Output Permutation in Solution Space (With Heuristic)

The given output permutation is searched in solution space tree. The Algorithm used is Selective Iterative Deeping Breadth first search where selective gates are applied to permutation in each level and it is checked with respective to its level (L) and L is incremented if search for output permutation is not found [3]. The Gates are selected based on the priority returned by heuristic compare function h_cmp (). The h_cmp () function compares the relative occurrence of given output permutation with permutation of a Gate (g).

The number of matches within a permutational data refers to its priority [5].

Eg: if gate 0 data is (1,0,3,2) and output permutation data is (1,3,2,0). There is one match between them at index 0. Therefore the Priority is „1‟.

Based on the priority, the gates will be sorted in descending order and first half of the gates are chooses for evaluation (50% confidence) and the rest of the gates will be pruned (through this method).

If the permutation founds within the search it displays the gate sequence else it continues the search within the block which pruned previously.

Since half of gates are chooses based on priority, the best possible answer lies within this priority range.

If all priority of gates sets to zero, it means its working like non-heuristic method.

Algorithm for searching an output permutation in Solution space (With Heuristic):

1. input <- 0 to 2^n; output <- {user given}; m <- 2^n; r<-2^ (n-1); flag=0; size<-n*r;

2. perm<-h_cmp(output,out,n,r,m); //performs the

International Journal of Emerging Technology and Advanced Engineering

80 3. sel=sort (perm, size); /* sorts the gates based on

priority and returns the gates on descending order including the priority no. The sel[i][0] is the priority and sel[i][1] is the gate number. */

4. startp<-0; endp<-size/2; // 0 to size/2 setting half of the gates.

5. while (level <5)

6. L <- (size-1)^(level -2); g <-0; 7. while (startp<=g && g<endp)

8. {gate <- perm (input, 2^n, L, sel[g][1]) // sel[g][1] is the gate no to which diff comb. Of gates at // level L is assigned to gate array

9. for i to L 10.{ for j to m-1

11.{buff=sel_push (out, n, gate[i][j], level); // permutation data present at gate [i][j] is stored in buff

12.buff1=club (buff, level, m); // piping is done between gates data

13.if (cmp (buff1, output) then print “Found at gate”+gate*i+*j+; flag=1;

14.}} 15.}

16.repeat 2-11

17.// if any of permutations are not matched then include the pruned gates (The next half of gates) from size/2+1 to size

Startp<-size/2+1; endp<-size; level<-2; g<-0; repeat step 4;

18.if (flag=0) print “not found”;

Time Complexity:O(n*2^(2n-2)) Results:

Permutation Gates Without Heuristic (sec)

With Heuristic (sec)

1,0,3,2,5,7,4,6 2,7,0,2 0 0 7,0,1,2,3,4,5,6 0,5,11 0 0 0,1,2,3,4,6,5,7 5,11,5 0 0 0,1,2,4,3,5,6,7 6,1,11,1,6 0 1 1,2,3,4,5,6,7,0 3,5,8 1 0 1,2,3,4,5,6,7,8,9

,10,11,12,13,14, 15, 0

7,11,17,24 4 1

0,7,6,9,4,11,10, 13,8,15,14,1,12, 3,2,5

3,17,6,10 5 0

Table which presents maximum No of elements searched (Till Level 5) in a given value n:

N Without Heuristic

With Heuristic

2 480 <240 3 193248 <96624 4 30537728 <15268864 5 3155955200 <1380730400

The Strength of the Heuristic can be seen when n>2 because it is reducing more than half of the elements being searched.

IV. CONCLUSION

The Algorithm Works on Toffoli Gate implementing Selective iterative deepening Approach. The Confidence Level in Finding out Correct permutation is 50% (default) and it can be increased till 90% but the overall search time. The Algorithm Full potential can be seen when n>2 because the no of elements in search increases to more than 1 crore and heuristic search make faster computations to

complete. Reverible circuits comes under the broad

category of VLSI technology , has a great scope of producing efficent extraction of enhanced gates in least cost manner which are useful in building reversible circuits.

REFERENCES

[1 ] D. Deutsch, Video Lectures on Quantum Computation, (2004-05), www.quiprocone.org.

[2 ] C. Bennett. Logical Reversibility of Computation. IBM Journal of Research and Development, 17, 1973, pp. 525-532.

[3 ] E. Fredkin and T. Toffoli. Conservative Logic. Int. Journal of Theory. Phys., 21 (1982), pp. 219-253.

[4 ] Logic Synthesis of Reversible Wave Cascades.

[5 ] T. Toffoli. Reversible Computing. In Automata, Languages and Programming, Springer Verlag, 1980, pp. 632- 644.