Fig. 9 shows the AC side response to the local DC fault, the same time scale as Fig. 7 has been used. The top plot shows the AC supply voltage, this is modelled as a stiff source and so is unaffected by the DC fault. The middle plot shows the line current when transitioning from normal operation to STATCOM “A” mode, while the bottom plot shows the line current under the same fault conditions when transitioning from normal operation to STATCOM “B” mode. Inspection of the results reveals that in the event of a DC-Link short circuit there is no spike in the line current. Thus using either method of fault ride through there is no need to open the AC side breaker. Furthermore it is shown that after a short transient of approximately one fundamental period, sinusoidal line currents are restored. After a second fundamental period the line current is increased to rated current to demonstrate delivery of maximum reactive power; although any reactive power operating point can be chosen, provided rated conditions are not exceeded. Thus, not only is there no need to open the AC side breaker, but further to this the AC network can be supported by operating as a STATCOM. This is a clear advantage of this topology over traditional HVDC-VSC converters.
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source converters and MMCs with FB cells, the alternate-arm multilevel converter is presented in [2, 17, 18]. This topology can block dc faults with reduced semiconductor losses compared to ; however, the direct switches composed of series connected IGBTs are still required. As a result, nearly identical switching characteristics of individual semiconductors with dynamic voltage sharing are required. Reference [13, 16, 19, 20] presents the hybrid multilevel converter which uses the two-level converter in series with cascaded FB cells. It offers ac fault ride-through capability and can block dc faults. However, the active switches of the two- level VSC still suffer high voltage stresses. The dc capacitors of the hybrid multilevel converter are also discharged by a short circuit between the positive and negative dc cables. When the dc side capacitors are charging to reestablish the rated dc link voltage, the inrush current from the ac grid is extremely high and poses a risk of system damage. Additionally, the main power stage of the proposed hybrid converter in [13, 16, 19, 20] can only generate two level output voltages, which contain more harmonics that need to be attenuated by the cascaded FB cells. Furthermore, the use of the two-level converter in the main power stage  necessitates the low power stage to track fast change rate of voltage, and this makes synchronization of the two power stages challenging.
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At 1.8s, a temporary 250ms pole-to-pole dc fault is applied (stage V). The dc voltage quickly drops to zero, the hybrid MMC reduces the active power to zero accordingly and meanwhile, it supplies 0.3 p.u. reactive power to the ac grid. It demonstrates that the hybrid MMC can not only block the dc fault, but also continue operating to regulate the ac current. Such feature shows an excellent dc fault ride-through capability of the hybrid MMC. At 1.9s and 2.0s, two attempts for building up the dc-link voltage are carried out by setting a small dc-link reference voltage though both attempts are failed due to the existing fault. As the dc fault is cleared at 2.05s, the third attempt by the hybrid MMC at 2.1s successfully builds up a small dc-link voltage and the process then moves to the dc-link voltage building stage. At 2.2s, the dc voltage has fully recovered and the active power is then gradually increased and the system recovers to normal operation (stage VI).
This paper presents the novel DC link FCL based FRT scheme to improve the FRT capability in the three-phase VSI. The proposed approach uses one set of single phase DLFCL only which is placed in the DC side of the VSI. Therefore, this approach reduces the number of the required FCLs which are used in the AC side of the VSI. In addition, in the proposed DLFCL due to implementing the non-superconductor DC reactor, the initial cost also decreases. The VSC strategy is employed during the normal operation as well as during the fault condition with the DLFCL. The proposed DLFCL can suppress severe di/dt at the first moments of the fault and protect the SDs of the VSI from damage, even at zero grid voltage as recommended by new grid codes with a high degree of reliability. Simulation studies have been carried out for worst-case scenario. From the results, it is clear that the proposed approach provides reliable performance during symmetrical fault.
Out of all the research mentioned above, in , , and , the authors used a STATCOM and distributed CPLs to achieve the maximum FRT capability of the FSWT. They have effective operation, especially in the case of asymmetrical faults. In , a STATCOM and coordinated positive and negative-sequence control, with the priority of the positive sequence, is applied to compensate for voltage dip during both symmetrical and asymmetrical faults. But this method requires more measurements and it is complicated. In a STATCOM, as a voltage source, self-turn on and turn off switches should be utilized. However, for a severe voltage dip, this method is not as effective [13, 19]. In , there are disadvantages similar to [13, 19], but the distributed CPLs need more ac/dc converters. Nonetheless, the CPLs inject a lower current to compensate for the voltage dip, in comparison with the aforementioned STATCOM.
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addressed to transmission and/or distribution systems. In most of the cases, e.g. Denmark, Germany, and Ireland, these requirements have focused on power controllability, power quality, and RTF capability [ 4]. Several studies have used the fast control action of the VSC converter to give support to the grid in case of a fault on the AC network, while carrying out a successful RTF of the DFIG wind farm, thus proving the efficiency of the VSC based power transmission for grid-code compliance . In the other hand, the design of the DFIG wind turbine also includes RTF capabilities that allow the wind turbine to remain connected during grid faults inside the wind farm network. A widely used method is the crowbar (CB) protection, which allows the disconnection of its turbine-associated power electronic converter, which helps to protect converter from the rotor induced transient currents, while adding external impedance to the rotor windings. Several investigations have shown the effectiveness of the electronic converter control of the DFIG and the CB protection to perform a successful RTF . However an aspect that has been constantly overlooked in studies is the RTF capability of the VSC-connected DFIG wind farm in case of a DC fault. The implication of a DC fault in a VSC connected DFIG wind farm is reviewed next.
Several studies have been carried out for performance as- sessment and FRT enhancement of PMSG under faults when interfaced with AC grids [8, 9]. Most of these studies focus on dissipation of excessive energy in the DC-link. On the other hand, superconducting fault current limiter (SFCL) was used in  to improve FRT capability of PMSG connected to AC grids through minimizing the mismatch between generator power and grid-side power and subsequent decreasing the overvoltage on the DC-link capacitor. In , it was proposed to store the excessive energy in the rotating parts of the gener- ator. But, this results in mechanical stresses and faster aging due to over-speeding of the generator. Also, at high wind speeds, the over-speed relay can be triggered due to violation of its allowed range. Unlike AC grids, fault behavior of PMSG interfaced with DC microgrids is different. In this case, the DC bus itself becomes faulty and the excessive energy will be reflected directly on the rotating parts of the generator. In ad- dition, the large fault currents will force generator-side con- verter to disconnect.
As adding new hardware in the DFIG, one of the common techniques is to employ fault current limiting devices to improve the FRT capability of the DFIG. Fault Current Limiters (FCLs) and Series Dynamic Braking Resistors (SDBRs) are placed in series connection of different locations in the DFIG (the stator side, the terminal, the DC link between the RSC and the DC link capacitor and the rotor side). In this paper, a review of most existing literature, which investigates the fault current limitation in the DFIG, are done. To improve the FRT capability of the DFIG, different configurations of the FCLs have been employed. Fig. 2 shows the diagram of all employed FCLs to enhance the FRT capability of the DFIG. The operational behaviour of each configuration is briefly discussed in normal and fault condition. The FCL structure can be categorized in respect to their impedance type during the fault condition. In the simulation section, the impedance type and the FCL’s location will be discussed, which have various impacts on the key parameters of the DFIG. In this paper, the detailed operation of the configurations is not taken into account and only the functionality is considered. In fact, steady state of the fault condition is discussed, which almost depends on the type and size of the impedance in the fault current limiting devices.
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The power system fault will lead to voltage dip on WTs. To maintain the grid stability, wind farm is required to keep connected in the power system for a defined time period under grid fault, this is called FRT. Actually, the voltage is not always dip to zero, it can be just a voltage sag. So many researchers put their efforts to deal with the so called low voltage ride-through problem. The main differences in FRTs requirement of different countries are the depth of voltage drop, the time period and the boundary where WTs can be tripped. New FRT needs not only the WTs keep on grid but also can provide vol- tage support or generator reactive power to the power system. So nowadays, the FRT researchers care even more subjects. How to protect the converter and DC bus of WTs, how to control the generator to generate reactive power and how to increase the voltage under grid fault are the three main study directions.
It is known that detailed modelling of MMCs consisted of huge number of switching devices, can result in excessive computational complexity and long simulation time. For a multi-terminal interconnected DC grids system, it is not efficient and practicable to using detailed models to build the whole system [13, 14]. In order to solve this issue, a simplified simulation model using average converter model for the proposed DC/DC converter using hybrid MMC topology is adopted. The average model replaces the strings of cells in each arm with a single average value cell as shown in Fig. 6. It is consisted of coupled controllable voltage source and controlled current source. Since the basic building block in the hybrid MMC is one simplified FBSM and one HBSM, all capacitors in one arm are lumped together and modelled as a single capacitor C. Fig. 6(a) and Fig. 6(b) show the average
Fig. 6 shows the results obtained when the test system is subjected to a line-to-line (asymmetrical) fault on one of the transmission line connecting the converter station 2 to the grid, with fault duration of 140ms as shown in Fig.2. At t=1s the active power command to the inverter is reduced to prevent the considerable rise of the main dc link voltage because of the trapped energy in the dc side. At t=1.14s the fault cleared. The voltage magnitude at bus B1 remains unaffected, hence confirming the hybrid VSC does not compromising the HVDC transmission system‟s decoupling future.
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Thyristor-controlled SVCs have been applied for voltage support of critical loads, reactive power compensation, and transient stability improvement in electric power transmission systems. The SVC is a combination of a thyristor- controlled reactor (TCR) with a thyristor-switched capacitor (TSC) or MSC as one compensator system which is practically connected to the PCC bus(or the wind turbine terminals) in order to provide fast voltage support and fulfill LVRT of WTs with induction generators. Based on new grid codes, this is a supplementary feature now for wind turbines to supply variable reactive power depending on network demand and actual voltage level, while the crucial problem of SVC is to inject an uncontrollable reactive current dependently on the grid voltage. Thus, the current injected by the SVC reduces linearly with the voltage sag and consequently the injected reactive power diminishes quadratically. The basic control of the SVC shown in Fig. 11 as a PI controller to control the firing angle of the thyristors of the TCR and TSC, keeping VPCC at 1pu during and immediately after the fault. A Fuzzy controller was designed for the SVC to significantly prove an improved dynamic response in terms of overshoot and settling time as compared to a conventional PI controller.
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Available online: https://edupediapublications.org/journals/index.php/IJR/ P a g e | 499 of MMC-based dc/dc topologies is that they need 2 cascaded dc/ac conversion stages. this can be a comparatively expensive answer as every dc/ac stage should method an equivalent input power, leading to poor utilization of total put in SM rating. Moreover, the inherent would like for AN intermediate ac link and electrical device rated for the complete input power more adversely impacts the full value similarly as overall conversion potency.
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This paper examines a supporting method to SSC for more reliable fault mitigation by investigating bidirectional AC/DC converter topology with DC fault current blocking capability. Replacement of semiconductor switches with full bridge cells allows instant reversal of voltage polarities to limit rapid capacitor discharge and machine inductive currents. Demonstration of this capability is realized by tracking DC fault currents in time-domain simulations of a ±270 VDC converter dynamic model built in MATLAB-Simulink. Simulation results have shown that the modified power converter topology provides a fast response to DC faults and it can be considered as a back-up to SSCs in clearing faults in ±270 VDC distribution systems.
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A protection scheme for DC faults has been designed for a multi-terminal HVDC network used to transfer energy from three large offshore wind farms to shore. The system uses open access models created in the EU-funded BEST-PATHS project, including a manufacturer-supplied wind farm model. Tripping conditions for the DC circuit breakers are found through simulation, along with current limiting inductor sizes, based on the use of a hybrid circuit breaker. Simulations of faults in the HVDC network show the ability of the protection scheme to isolate the fault, and the converter stations and wind turbines are able to ride-through the fault without tripping based on the 5ms switching time of the circuit breakers Longer switching times will cause significant rises in the offshore grid frequency, which could cause the turbines to trip.
Comparing DC P-P faults at location 1 and 2, the fault at location 1 is more severe. The P-P fault at location 1 makes the entire LVDC to experience large voltage drop as shown in Fig. 11. In this case, the upstream and downstream converters cannot limit the fault current contributions from the grid and customer sides. As for the DC P-P fault at location 2, the fault current contribution from the upstream is limited by the DC/DC bidirectional converter. This has limited the impact of the fault on the LVDC voltage profiles on the main feeder and on the point of common coupling. Such performance can allow the loads and generators connected to adjacent unfaulted feeders to ride through such faults.
In , limiting reactors are series connected with the fast acting DCCBs (e.g. solid-state DCCBs, hybrid DCCBs) to limit the fault current di/dt and decrease the fault current peak. However, all the system stations are blocked during the fault to avoid overcurrents, causing shutdown of the entire multi- terminal HVDC system. The ride-through operation of a multi- terminal HVDC system is presented in [11, 12], where additional series dc inductors and slow DCCBs are used to limit the fault current increase rate and isolate the fault. For a dc fault applied at the dc-link node, the stations connected to the healthy branches of the HVDC system are far from the fault location so the fault has less influence.
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DC fault ride-through operations of the OWF connecting with DRU-HVDC link is investigated in this paper. By injecting voltage-error-dependent fault currents, the WT converters provide fault currents during faults, which contributes the AC voltage control of the offshore network and facilitates fast system recovery after fault clearance. The onshore FB-MMC station operates on STATCOM mode during DC faults and its DC fault current is effectively suppressed around zero by the proposed fault current controller, which reduces losses and potential overcurrent risk of the MMC station during the fault. With the proposed control scheme, the system is robust to DC faults and can automatically restore normal operation after fault clearance.
Fault ride-through (FRT) is necessary for large wind farms in most power systems. Fixed speed wind turbines (FSWTs) are a fading but important sector in the fast-growing wind turbine (WT) promote. The series dynamic braking resistor (SDBR) dissipate active power and boost generator voltage potentially displace the need for pitch control and dynamic RPC. This paper uses a diplomat wind farm model to study the beneficial effect of SDBR compared to dynamic RPC. This all concluded by Andrew Causebrook, David J. Atkinson, and Alan G. Jack.
The second method is to add new structure in the configuration of the DFIG. Dynamic voltage restores (DVRs), static synchronous compensator (STATCOM), unified power quality controller (UPQC), and static VAR compensator (SVC) are applied to compensate voltage sag in the grid side of the DFIG [9-12]. The mentioned structures use many numbers of the self-turn off switches and need more measurements. Fault current limiters (FCLs), and series dynamic breaking resister (SDBR) are effective to limit the fault current level both in the stator and the rotor side [13-16]. However, both the FCLs and the SDBRs require some measurements and also in the SDBRs, they need continuous controlled switching during the normal operation. Furthermore, some structures of the FCLs utilize inductive type of superconductor, which increases initial and maintenance costs of the FCLs. The most general method is crowbar protection, which de-energizes the rotor and bypasses the RSC during the fault . The crowbar changes the DFIG to squirrel cage induction generator, which does not comply the grid code requirements [2, 17].