deep submicron VLSI circuit
Transistor sizing of CMOS VLSI Circuits in Deep Submicron Technology
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Estimation of Crosstalk Noise for 2 RC and RLC Interconnects in Deep Submicron VLSI Circuits
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A Comprehensive Study on Power Reduction Techniques in Deep Submicron Technologies
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Analytic modeling of interconnects for deep submicron circuits
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A Novel and Efficient Mixed Signal VLSI Circuit for Multimode Demodulator
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PERFORMANCE ANALYSIS OF HIGH SPEED CMOS FULL ADDER CIRCUIT FOR LOW VOLTAGE VLSI CIRCUIT DESIGN IN NANOMETER.
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LOW POWER CONSUMPTION USING CMOS VLSI DESIGN IN MODERN TRENDS
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A Voltage Scaling Method to Reduce Power in Static Rams In Deep Submicron Technology
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Efficient Implementation of Finite Field Multipliers over Binary Extension Fields
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THEORITICAL ASPECTS OF ASYNCHRONOUS CIRCUIT DESIGN TO REDUCE POWER CONSUMPTION IN A VLSI
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Implementation on Low Power Design Using Comparator for VLSI Design Circuit
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Accurate modeling of gate capacitance in deep submicron MOSFETs with high K gate dielectrics
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A REVIEW ON USING ASYNCHRONOUS CIRCUIT DESIGN TO REDUCE POWER CONSUMPTION IN A VLSI
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LOW-POWER HIGH-SPEED CIRCUIT DESIGN FOR VLSI MEMORY SYSTEMS
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Efficient VLSI Architecture for Sign Reversible Multiplier Circuit using DKG Gate
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A RISK MITIGATION DECISION FRAMEWORK FOR INFORMATION TECHNOLOGY ORGANIZATIONS
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VLSI Architecture Design Parameters and Tools: A Review
6
Semiconductor Devices and Electronic World
11
High Performance and Low Noise BCD Adder Circuit Design Using Rate Sensing Keeper
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Development of deep submicron CMOS process for fabrication of high performance 0.25 nm transistors
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