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Delay lines

Spatial Power Combining of VLF Umbrella Antenna Arrays with Multi-Delay Lines

Spatial Power Combining of VLF Umbrella Antenna Arrays with Multi-Delay Lines

... In this study, a novel SPC method for VLF transmitting antenna arrays is proposed. The proposed method can be divided into two approaches: the first approach is to separate two signals from a transmitter to the two ...

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IMPLEMENTATION OF GLITCH-FREE DIGITALLY CONTROLLED DELAY LINES

IMPLEMENTATION OF GLITCH-FREE DIGITALLY CONTROLLED DELAY LINES

... A delay can be referred to latency or the response time. A digital delay line can be defined as an element in the digital filter theory, where it will allow a signal to be delayed by a defined number of ...

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Glitch Free Strobe Control Based Digitally Controlled Delay Lines

Glitch Free Strobe Control Based Digitally Controlled Delay Lines

... controlled delay-lines (DCDL) present a glitching problem which may limit their employ in many ...controlled delay lines overcame this limitation by opening the employ of glitch free ...

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Broadband and High Efficiency Single-Layer Reflectarray Using Circular Ring Attached Two Sets of Phase-Delay Lines

Broadband and High Efficiency Single-Layer Reflectarray Using Circular Ring Attached Two Sets of Phase-Delay Lines

... seen that for different lengths of phase-delay lines, the reflection phase curves are parallel to each other with small phase variation over the very wide frequency band of 11.58–21.58 GHz. Fig. 6 displays ...

10

CMOS Phase and Quadrature Pulsed  Differential Oscillators Coupled through  Microstrip Delay Lines

CMOS Phase and Quadrature Pulsed Differential Oscillators Coupled through Microstrip Delay Lines

... a delay is necessary for proper positioning of refilling current ...a delay can be obtained with the charging of a capacitor through a dissipative media ...RC-based delay is not possible to set the ...

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A REVIEW ON GLITCH-FREE DIGITALLY CONTROLLED DELAY LINES

A REVIEW ON GLITCH-FREE DIGITALLY CONTROLLED DELAY LINES

... To remove glitches occurring in NAND-based digitally controlled delay lines (DCDLs), a novel glitch-free architecture is presented. Compared with the previous structures requiring multiple control steps, ...

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The Effect of Loss-Tangent on Laddering Behavior in Delay Lines

The Effect of Loss-Tangent on Laddering Behavior in Delay Lines

... Abstract—Delay lines come in varying topologies such as the simple meander line or the spiral delay ...these delay lines is their introduction of a laddering behavior at the ...the ...

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Automated  Design,  Implementation,   and  Evaluation  of  Arbiter-based  PUF  on  FPGA  using  Programmable  Delay  Lines

Automated Design, Implementation, and Evaluation of Arbiter-based PUF on FPGA using Programmable Delay Lines

... CUT delay can be measured with a very high accuracy and in an automated ...the delay characterization method the reader is referred to [Majzoobi et ...

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Booth 
		recoded WALLACE tree multiplier  using NAND based  digitally controlled 
		delay lines

Booth recoded WALLACE tree multiplier  using NAND based  digitally controlled delay lines

... controlled delay line (DCDL) is a digital circuit used to provide the desired delay for a circuit whose delay line is controlled by a digital control ...increasing delay control code in a ...a ...

7

Sparse Array Design for Wideband Beamforming with Reduced Complexity in Tapped Delay-lines

Sparse Array Design for Wideband Beamforming with Reduced Complexity in Tapped Delay-lines

... Abstract —Sparse wideband array design for sensor location optimisation is highly nonlinear and it is traditionally solved by genetic algorithms (GAs) or other similar optimization methods. This is an extremely ...

13

Non-uniform wordlength delay lines for FIR filters

Non-uniform wordlength delay lines for FIR filters

... When FIR filters are designed floating point arithmetic is generally used. However when implemented on hardware such as ASICs, fixed point arithmetic must be used to mini- mise cost and power requirements. Research to ...

5

A fast - Locking Pulsewidth Controlled Clock Generator for High Speed SOC Applications

A fast - Locking Pulsewidth Controlled Clock Generator for High Speed SOC Applications

... coarse delay line (CDL) and a coarse detector, a fine delay line (FDL) and a fine detector, a duty-cycle setting circuit, and a finite state machine (FSM) and control ...fine delay lines, ...

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Self-Equalized Distributed Amplifier for Wide Band Optical Transceivers

Self-Equalized Distributed Amplifier for Wide Band Optical Transceivers

... delay lines in series with gate ...which delay lines placed in series with gate ...The delay element shown in Figure 4 as line ...

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Performance evaluation of spectral amplitude codes for OCDMA PON

Performance evaluation of spectral amplitude codes for OCDMA PON

... optical delay lines and incoherent optical sources, pulse phase coding (PPC) which utilize the optical fields by using phase modulator within fiber optic delay lines for introducing 0 o or 180 ...

5

High Performance Asynchronous Pipelined QDI Templates for DCT Matrix vector Multiplication

High Performance Asynchronous Pipelined QDI Templates for DCT Matrix vector Multiplication

... data-dependent delay lines are proposed to create low overhead integrated control circuits capable of handling nonlinear pipelines and enabling high average ...

8

Wireless Readout of Multiple SAW Temperature

Wireless Readout of Multiple SAW Temperature

... designed sensors based on reflective delay lines that allow the parallel readout of four independent.. 18.[r] ...

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SAHYB 2: A Programme for the Solution of Differential Equations Using an Analogue Oriented Language  EUR 3622

SAHYB 2: A Programme for the Solution of Differential Equations Using an Analogue Oriented Language EUR 3622

... 8.3 - Fixed or variable, delay lines In many engineering problems delayed functions are necessary; for this purpose a function named DELAY is available in the programme, and is called as[r] ...

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A 3ps Resolution Time-to-digital Converter in Low-cost FPGA for Laser Rangefinder

A 3ps Resolution Time-to-digital Converter in Low-cost FPGA for Laser Rangefinder

... There are various configurations used to obtain a tapped delay lines. The figure 4 presents the simplest one. A train of buffers can be used to create a delay line. Each of the buffers should have ...

5

A Flexible Integrated Photonic True Time Delay Phaser for Phased Array Antennas

A Flexible Integrated Photonic True Time Delay Phaser for Phased Array Antennas

... Photonics represents a key technology for present and future developments of high performance antennas for civil and military applications, giving a possible solution to the limitations showed by conventional steering ...

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A Simulation Study of Cross Traffic on Expedited Forwarding in Differentiated Services Networks.

A Simulation Study of Cross Traffic on Expedited Forwarding in Differentiated Services Networks.

... delays, delay jitter, and inter-packet jitter experienced by packets within the EF aggregate are of special interest when it comes to jitter sensitive applications such as video and voice-over ...a delay ...

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