Digital Architecture

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A LOW POWER DIGITAL ARCHITECTURE USED FOR ECG ACQUISITION SYSTEM

A LOW POWER DIGITAL ARCHITECTURE USED FOR ECG ACQUISITION SYSTEM

time the output signal is reliable Fig le. The overall performance parameters of the front end are shown in Table IV. The VTC gain is defined as the ratio delay variation at the output of the VTC blocks and the input voltage range. In order to explore the noise performance of the front end, the jitter is obtained at the output of the front end. The noise power spectral density is shown in Fig. 15 and a jitter noise of 5 ns and SNR of 42 dB are obtained. Depending upon the required resolution this amount of noise may be large. Since there is a tradeoff between power and noise, in order to reduce the noise more power should be burnt. Using the proposed PSRR enhancement circuit in this paper leads to the PSRR of 67.7 dB. The power consumption of the overall front end is 274 nW and is noticeably less than other mixed-signal ECG front-end circuits. This can be considered as one of the main advantages of the proposed fully digital architecture.
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Scalable Digital Architecture of a Liquid State Machine

Scalable Digital Architecture of a Liquid State Machine

The capability to multiplex at the output layer for multiple tasks makes LSM a powerful intelligent engine. These properties are desirable in several machine learning applications such as speech recognition, anomaly detection, user identification etc. Scalable hardware architectures for spatio-temporal signal processing algorithms like LSMs are energy efficient compared to the software implementations. These designs can also naturally adapt to different temporal streams of inputs. Early literature shows few behavioral models of LSM. However, they cannot process real time data either due to their hardware complexity or fixed design approach. In this thesis, a scalable digital architecture of an LSM is proposed. A key feature of the architecture is a digital liquid that exploits spatial locality and is capable of processing real time data. The quality of the proposed LSM is analyzed using kernel quality, separation property of the liquid and Lyapunov exponent. When realized using TSMC 65nm technology node, the total power dissipation of the liquid layer, with 60 neurons, is 55.7 mW with an area requirement of 2mm 2 . The proposed model is validated for two
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Vladimir Shukhov A Critical Review on Digital Architecture

Vladimir Shukhov A Critical Review on Digital Architecture

Nowadays, architects and engineers design forms using the most convenient ways of compu- tation that lead to structures that are difficult to build. The presented comparison demonstrates that, despite new opportunities given by new technolo- gies, the design logic did not go much further than post and lintel system. If the architecture gener- ated by computational logic is called 'smartgeome- try,' perhaps engineers and architects should strive for 'wisegeometry,' geometry based not as much on calculations as on optimal construction logic in the physical world, such as that of Shukhov's structures? Perhaps 'wisegeometry' would start addressing Chris Williams's contemplation in Smartgeometry: 'Com- puters are no longer a new technology, but their impli- cations for the ways in which people will work are still unclear' (Peters and Peters 2013).
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Scalable Digital Architecture of Hierarchical Temporal Memory Spatial Pooler

Scalable Digital Architecture of Hierarchical Temporal Memory Spatial Pooler

The pre-processed MNIST dataset images are saved in a text file and sent to the spa- tial pooler architecture through VHDL testbench by behavioral simulation of RTL. The RTL testbench instantiates the HTM SP Design Under Test (DUT) and reads input patterns from a text file to the HTM SP. The HTM SP SDR ouput produced is written as a separate text file. The input binary image patterns are read in se- quentially by the testbench, and the process waits till the output for the given input is produced, to read the next input image data. This process continues until the specified number of training data samples and testing data samples have been read into the spatial pooler DUT.
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The Emergence and Impending of Digital Design in Architecture

The Emergence and Impending of Digital Design in Architecture

Abstract- The paper introduces and discusses current developments in architectural discourse, design theory, digital design models, techniques and their relations to design pedagogy. The evolution of design knowledge in architectural theory and praxis is explicated and its implications for required changes in design education are presented. The theoretical influence of architectural concepts is presented through historical references in digital architecture. This structure of design concepts is proposed as a medium of design education. An experimental design studio on: „Design as research: the exploration of digital architectural concepts‟ is presented as a pedagogical framework for educating the digital architect and a series of research and design programs carried out in an experimental design studio demonstrates this framework. Digital architectures are profoundly changing the processes of design and construction. By integrating design, analysis, manufacture and assembly of buildings around digital technologies, architects, engineers, and builders have the opportunity to reinvent the role of a “master- builder” and reintegrate the currently separate disciplines of architecture, engineering and construction into a relatively seamless digital collaborative enterprise, thus bridging “the gap between designing and producing that opened up when designers began to make drawings.
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Effective Design of an High speed Digital Fault Tolerant Architecture

Effective Design of an High speed Digital Fault Tolerant Architecture

Adder is absolutely essential block in any digital architecture. Among different types of adders ripple carry adder (RCA) is most popular in different type of computing machines because it is simple in structure and easy to implement. It has also high throughput for bit level pipelining. We have taken a 4-bit RCA to make itself reconfigurable. We will also discuss how the same approach can be applied to any system, which can be divided into some identical modules, to make the system fault tolerant. The fault tolerant designs are also cascadable to increase the number of input bits Making a system module wise self-reconfigurable is more cost effective and hardware efficient rather than trying to make the whole system fault tolerant at a time.
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Development and Analysis of VHDL Architecture of Reconfigurable Digital Modulator and Demodulator

Development and Analysis of VHDL Architecture of Reconfigurable Digital Modulator and Demodulator

965 Juha Suviola et al [6] proposed a real time implementation of FPGA based frequency synthesizer by utilizing I/Q modulation. The core structure of the systems designed around digitally synthesized programmable low- frequency I/Q tone which is then moved to the required radio frequency range using I/Q modulation. The design is specifically emphasizes in the adaptive digital pre- distortion and calibration mechanisms which improve the limited sideband attenuation with local oscillator leakage of practical I/Q modulators. A shuffled iterative bit interleaved coded modulation (BICM) receiver is presented in [7]. A development of a wideband delta sigma modulator for completely digital UHF transmitters [9]. The complete digital architecture of the transmitter provides a promising solution for software defined radio (SDR) devices and applications. The proposed fully digital transmitter consists of three main units 1) delta-sigma modulator, 2) high speed multiplexer and 3) switching-mode power amplifier.
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Systems, Architecture & The Digital Body: From Alphaville to The Matrix

Systems, Architecture & The Digital Body: From Alphaville to The Matrix

conforms to a systematic totalitarianism but, equally, an architecture which functions as the matrix for the complex system that is Alpha 60, the ‘electronic grating’ voice of which, ‘unpleasant as it is indescribable’ is omnipresent. xiii Apparently, Godard used the voice of a man who had lost the use of his vocal chords and had learned to speak from his diaphragm. xiv In the context of the film’s mise en scène it is a voice that is literally disembodied, being both everywhere and nowhere, while still (almost) recognisably human. Interior shots show what appear to be miles of indistinguishable corridors and rooms in which the extensions of Alpha 60 (microphones, tape machines and white coated human engineers and clerks) are a dominant presence. Hotel rooms and brightly lit lobbies of public buildings are familiar spaces rendered startlingly alien by their proximity in film space to the distanciated spaces of Godard’s darkened Paris. Alpha 60 speaks, articulating the super-rationalist philosophy which structures the social nexus of Alphaville, and its locution both invokes and evokes the city and the bodies that are its correlates.
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An architecture of a user-centred digital library for the academic community

An architecture of a user-centred digital library for the academic community

Zhao discusses the Personal Digital Library (PDL) (Zhao, 1998). Barry discusses the creation of personal digital libraries(Barry, et al., 1999). The North Carolina University Library (NCSU) developed MyLibrary@NCState as a portal application to the NCSU Library’s information resources (Mylibrary, 2000). MyLibrary is a Cornell University Library initiative to provide personalized library services to their patrons(Suzane, et al., 2000). At the NTU Library in Singapore, the Gateway to Electronic Media Services (GEMS, 2000) serves as a vehicle to deliver a range of information resources to all staff and students in the campus. HeadLine is one of the eLib programme’s Phase 3 projects, Personal Information Environment (PIE), uses portal- type technology to present an information environment (Gambles, 2000). The MyLibrary and HeadLine projects are designed to provide users with links to information resources.
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The Brazilian digital television system access device architecture

The Brazilian digital television system access device architecture

G. Bedicks Jr., F. Yamada, F. Sukys, C. E. S. Dantas, L. T. M. Raunheitte, C. Akamine. Results of the ISDB-T system tests, as part of digital TV study carried out in Brazil. In . 52(1): 38- 44, March. 2006. G. Bedicks Jr., F. Yamada, F. Sukys, C. E. S.

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Traditional and Digital Representations of Atmosphere in Architecture  A first systematisation

Traditional and Digital Representations of Atmosphere in Architecture A first systematisation

At present, one of the main objectives of digital visualisations in architecture is, arguably, to market projects to clients and other parties. Again, however, there are exceptions to this condition, as in works of architects and practices such as Holl (b. 1947) (Fig. 3 – top right), Zumthor (b. 1943) (Fig. 3 – top left), and Snøhetta (Fig. 3 – bottom). Holl’s restrained use of traditional media draws viewers into atmospheres of contemplation and controlled movement. Zumthor’s design is represented more vividly, to convince viewers of the space’s illuminative, material, and scalar possibilities, and of the moods which follow. Snøhetta’s vision of an interior at the National Center for Theodor Kittelsen communicates, through its view towards the adjacent forest, a feeling of discovery and wonder. This is, more precisely, represented in two children looking out at an ‘enchanted’ view, reminiscent of Kittelsen’s drawings and in an apparent homage. Here, the window opens onto a real landscape depicted fantastically, emphasised further by the light’s ephemerality and the presence of two faintly rendered animals.
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Digital Library Architecture

Digital Library Architecture

A digital library is an integrated set of services for capturing, cataloging, storing, searching, protecting, and retrieving information, which provide coherent organization and convenient access to typically large amounts of digital information. Digital libraries are realizations of architecture in a specific hardware, networking, and software situation, which emphasize organization, acquisition, preservation, and utilization of information.

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Design an High speed Digital Fault Tolerant Architecture

Design an High speed Digital Fault Tolerant Architecture

In the era of deep sub-micron technology, probability of chip failure has been increased with increase in chip density. A system must be fault tolerant to decrease the failure rate and increase the reliability of it. Multiple faults can affect a system simultaneously and there is a trade-off between area overhead and number of faults tolerated. This paper presents high speed fault tolerant architecture design for digital applications. The fault containment and parallel processing capabilities of computers network are being exploited to provide a high performance, high availability network capable of tolerating a broad scope of hardware, software, and operating system faults.
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A Quantum MIMO Architecture for Antenna Wireless Digital Communications

A Quantum MIMO Architecture for Antenna Wireless Digital Communications

Note the fundamental difference between classical and quantum MIMO systems: In contrast to the classical case, the Rx radiation state ρ rx i does not depend on position. Indeed, working with the Heisenberg picture, the state is time independent while measurement operators (observables), for instance, field strength, energy, momentum, spin, etc, are spacetime functions. The operators O j are then functions of r, although for simplicity we drop out this dependence. All q-MIMO receivers will interact with essentially the same global state of Equation (16). However, it is very difficult to directly calculate with Equation (16). In fact, in what follows we will not develop the digital receiver theory based on such factorization according to paths because the latter is unknown to the receiver. Instead, we rely on q-antenna theory to provide natural universal basis for the Hilbert space of the entire MIMO system, say a set |l indexed by l , and expand all (e.g., pure) states as
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Design and implementation of a multiprocessor architecture for adaptive digital filters

Design and implementation of a multiprocessor architecture for adaptive digital filters

filters in terms of data storage, transversal filter operations, and adaptive filter opera-. tions[r]

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Network digital evidences centralization by using honeynet architecture

Network digital evidences centralization by using honeynet architecture

25 without our awareness. With the development of information communication technology (ICT) and cybercrime (Internet crime) intelligence, modern judicature that including criminal, civil and administrative must carry out litigation by using technology; especially in dealing with organized and terrible crime. Since digital evidence has often been very effective and important, the legislative and legal authorities in each country have gradually put more credence to digital evidence. As a result, establishing guidelines which after testing become Standard Operating Procedures (SOP); are important in raising the effectiveness and credibility of digital evidence. Subsequently, the move to create a digital evidence's standard operating procedure (DESOP) is essential to the development of a sophisticated information society. We would like to discuss the establishment of DESOP from procedure and software tool (Lin, A.C et al, 2005)”.
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Architecture for using Java bytecode for processing Digital Items

Architecture for using Java bytecode for processing Digital Items

also any kind of digital content that accompany a media object. For example, a DI for the use case in the previous section will consist of resources such as album cover art, all audio and video recordings of songs, lyrics for individual songs, as well as guitar strumming instructions. All these resources will be organized using some description tools into albums or in some other manner as desired. Metadata in the DI can provide information about the QoS requirements for a particular media resource that may be utilized to stream the media across the wireless link.

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A Service Oriented Peer to Peer Architecture for a Digital Ecosystem

A Service Oriented Peer to Peer Architecture for a Digital Ecosystem

In order to determine which peers in the gradient topology host SOA registry replicas, each peer periodically calculates the replica placement threshold, using the aggregates provided by[r]

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A Parallel Architecture for Analog-to-Digital Conversion with Improved Dynamic Range

A Parallel Architecture for Analog-to-Digital Conversion with Improved Dynamic Range

The main focus of this thesis is to determine if a parallel architecture of Analog to Digital Converters (ADCs) can be used to obtain a better system dynamic range than that of a single converter. This type of configuration is applicable to a Continuous Wave Stepped Frequency (CWSF) radar system. Existing CWSF radar system has to use less power than those using a pulsed frequency. This is due to the cross-coupling term from the transmitter to the receiver. As a result, there is less power to be illuminated to the target. If the power that can be received is increased, it will lead us to believe that extra power can be used to transmit to the target – allowing targets with a smaller Radar Cross Section (RCS) to be seen.
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Improved Technique for Simulation of Digital
Forensic Architecture Framework in Cloud

Improved Technique for Simulation of Digital Forensic Architecture Framework in Cloud

The available models concentrate on part of the investigative process (dealing with gathering, analysing and presenting evidence) but a fully general model must incorporate other aspects if it is to be comprehensive. The investigation of a computer or other digital device is also more similar to a physical crime scene investigation than a physical forensic analysis because of the amount of potential evidence [9]. A physical crime scene can be processed to identify many pieces of evidence. Blood on a wall is one piece of evidence and it can be analyzed to identify the owner of the blood, the type of object that struck the victim, the location of the victim, the location of the attacker, and the time of attack [2]. Similarly, a fingerprint is one piece of evidence that can be analyzed to show identity information and orientation information about how the person was facing.
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