Digital signal processing applications are specified with floating-point data types but they are usually implemented in embedded systems with fixed-point arithmetic to minimise cost and power consumption. Thus, methodologies which establish automati- cally the fixed-point specification are required to reduce the application time-to-market. In this paper, a new methodology for the floating-to-fixed point conversion is proposed for software implementations. The aim of our approach is to determine the fixed-point specification which minimises the code execution time for a given accuracy constraint. Compared to previous method- ologies, our approach takes into account the DSP architecture to optimise the fixed-point formats and the floating-to-fixed-point conversion process is coupled with the code generation process. The fixed-point data types and the position of the scaling opera- tions are optimised to reduce the code execution time. To evaluate the fixed-point computation accuracy, an analytical approach is used to reduce the optimisation time compared to the existing methods based on simulation. The methodology stages are de- scribed and several experiment results are presented to underline the eﬃciency of this approach.
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Abstract— Digital Signal Processing is one of the most powerful technologies that will shape science and engineering in the twenty-first century. Revolutionary changes have already been made in a broad range of fields: communications, medical imaging, radar & sonar, high fidelity music reproduction, and oil prospecting, to name just a few. Each of these areas has developed a deep DSP technology, with its own algorithms, mathematics, and specialized techniques. This combination of breath and depth makes it impossible for any one individual to master all of the DSP technology that has been developed. This paper starts our journey into the world of Digital Signal processing by describing the dramatic effect that DSP has made in several diverse fields. The revolution has begun. The number and variety of products that include some form of digital signal processing has grown dramatically over the last five years. The products use a variety of hardware approaches to implement DSP, ranging from the use of off-the-shelf microprocessors to field-programmable gate arrays (FPGAs) to custom integrated circuits (ICs). Programmable “DSP processors,” a class of microprocessors optimized for DSP, are a popular solution for several reasons. In comparison to fixed- function solutions, they have the advantage of potentially being reprogrammed in the field, allowing product upgrades or fixes. And in comparison to other types of microprocessors, DSP processors often have an advantage in terms of speed, cost, and energy efficiency. In this article, we trace the evolution of DSP processors, from early architectures to current state-of-the-art devices. We highlight some of the key differences among architectures, and compare their strengths and weaknesses. Finally, we discuss the growing class of general purpose processors that have been enhanced to address the needs of DSP applications.
Most companies in the university’s service area are involved with DSP, and this correlates with the main focus and strength of the department in applied DSP. In addition to hardware topics such as digital signal processors, strong software development, such as real-time DSP algorithms, and programming skills are also required. It is important to southern Taiwan industrial activities that we oﬀer real- time DSP application courses. With this in mind, a real- time application course on DSP laboratory experiments was introduced into the CSIE undergraduate curriculum for night-school students. This course introduces TMS320C6x, TMS320C54x, and TMS320C55x digital signal processors for experiments. Through a sequence of lab experiments, students learn the concepts and skills of DSP programming to design and develop advanced DSP applications. This course is well received by undergraduate students because it emphasizes practical DSP aspects.
Sorin Zoican et.el.  illustrated the role of Digital Signal Processors for third generation mobile systems. They discussed global objectives and attributes that include worldwide roaming, universal connectivity, high data transmission rates, location service capability, and support for high-quality multimedia services. B.G.Evans et.el. discussed the limitations of 3G and drivers for 4G.Manoj Kumar Jain et.el  analyzed that the design and deployment of mobile processors over the years is affected by Communication, performance , low-power operation and the development in mobile processors is driven by factors such as low-power consumption, user interface performance, time to market, etc. R. Ramakrishna et. el  proposed a design of a variable point FFT processor using FPGA in which OFDMA Technology is applied. The FFT processor use Verilog HDL language to describe the circuit, use Quartus II 7.2 software to build the model, and use ModelSim SE 6.2b software to verify the timing function.
One possible straight forward power estimation approach on DSPs is the so-called Physical-Level Power Analysis methodology. This approach is based on the analysis of the switching activity of all transistors of the DSP architecture. The requirement of this methodology is the availability of a description of the processor architecture on the transistor level, which is rarely given for modern DSPs. But the main disadvantage is the extremely high computational effort that makes approaches like this inapplicable for digital signal processors. Architectural-Level approaches like (Brooks, D., et al.; 2000) reduce this computational effort by modelling typical architecture elements like registers, functional units or load/store queues. These models are not based on physical measurements and require still exact knowledge of the processors architecture. Therefore, these two methodologies can be mainly found in the field of microprocessor development.
As the demand of low power circuits increasing in the modern days,design of power efficient logic systems has became the most important areas of research in VLSI system design.The digital can perform many types of logical functions,the main among them is the addition operation.As addition is most extensively used operation in many general purpose processors to application specific DSP Processors.As this addition operation can be done by using various types of adders such as Ripple Carry Adder,Carry Look Ahead Adder,Carry Select Adder etc.
Multiplication is the basic building block for several DSP processors, Image processing and many other. Over the years the computational complexities of algorithms used in Digital Signal Processors (DSPs) have gradually increased. This requires a parallel array multiplier to achieve high execution speed or to meet the performance demands.
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In recent years, power consumption has become a critical design concern for many VLSI systems. It is an important parameter in portable battery- operated applications where the power consumption may be more important than speed and area. The multiplier is one of the main blocks, which is widely used in different applications digital signal processing applications. There are two general architectures for the multipliers, which are sequential and parallel. While sequential architectures are low power latency is very large. On the other hand, parallel architectures (such as
We will present the design and FPGA implementation of sequential digital 8-tap FIR filter using a novel micro programmed controller based design approach. In this paper, the FIR filter is designed for operation controls by micro programmed controller. The proposed FIR filter will be coded in VHDL using modular design approach, and implement in Spartan-3E FPGA. The performance evaluation and synthesis results obtained through Xilinx ISE synthesis tool and functionally checked in Model sim module.
The paper briefs about the method to verify appropriate program execution. In order to achieve the high speed and low power demand in DSP applications, parallel array multipliers are widely used. In DSP applications, most of the power is consumed by the multipliers. Hence, low power multipliers must be designed in order to reduce the power dissipation in DSP applications. Systolic algorithm is the form of pipelining, sometimes in more than one dimension. In this algorithm data flows from a memory in a rhythmic fashion, passing through many processing elements before it returns to memory. H. T. Kung and Charles Leiserson were the first to publish a paper on systolic arrays in 1978, and coined the name, which refers to the “pumping action of the heart’’. What can a systolic array do? This question is very important, and the answer is that every Sequential algorithm that can be transformed to a parallel version suitable for running on array processors that execute operations in the so-called systolic manner, and systolic array is one of solutions to the need for a highly parallel computational power. Due to the use of matrix-multiplication algorithm in wide fields such as Digital Signal Processing (DSP), image processing, solutions of differential comparison, non- numeric application, and complex arithmetic operations, we shall design an 8-bit systolic array that designed and implements. Verilog finds many applications because of its very high speed integrated circuit. It is a hardware description language and program can be loaded into the chip and can be used by tool user. As the language supports flexible design methodology, it can be used to define complex electronic systems. Common language can be used to describe the library components. Because of its unique feature, Verilog is used to design N-bit binary multiplier. The program in Verilog provides the scope for multiplication of two N-bit binary numbers by including the user defined package.
[B] Dinesh, V. Venkateshwaran, P. Kavinmalar and M. Kathirvelu, Multipliers are key parts of the many high performance systems like FIR filters, microprocessors, digital signal processors, etc. A system's performance is generally determined by the performance of the multiplier as the multiplier is generally the slowest element in the system. The analysis of performance parameters of different multiplier logics is essential for design of a system intended for a specific function with constraints on Power, Area and Delay. The work presents a detailed analysis of all the serial-parallel and parallel architectures. The multipliers are designed for 4 bit multiplication using DSCH tool and the corresponding layouts are obtained using Microwind 3.5 tool using 45nm technology. From the analysis it's
Abstract- This paper considers the design of wireless communications systems which are implemented as highly integrated embedded systems comprised of a mixture of hardware components and software. An introduction part presents digital communications systems, classification of processors, programmable digital signal processing (DSP) processors, and development and implementation of a flexible DSP processor architecture. This introduction is followed by a total of seven publications comprising the research work. In this paper the following topics have been considered. The processor core itself as a bare hardware circuit is not usable without various software tools, function libraries, a C- compiler, and a real-time operating system. The set of development tools was gradually refined, and several architectural enhancements were implemented during further development of the initial processor core. Furthermore, the modified Harvard memory architecture with one program memory bank was replaced with parallel program memory architecture. With this architecture the processor accesses several instructions in parallel to compensate for a potentially slow read access time, a characteristic which is typical of, for example, flash memory devices. The development flow for heterogeneous hardware/software systems is also studied. As a case study, a configurable hardware block performing two trigonometric transforms was embedded into a wireless LAN system described as a dataflow graph. Furthermore, implementation aspects of an emerging communications system were studied. A high-level feasibility study of a W-CDMA radio transceiver for a mobile terminal was carried out to serve as a justification for partitioning various baseband functions into application-specific hardware units and DSP software to be executed on a programmable DSP processor. Keywords – Wireless LAN system, W-CDMA radio transceiver, DSP processor
Adders are commonly used in the critical path of many building blocks of microprocessors and digital signal processing chips. Adders are critical component not only for addition, but also for subtraction, multiplication, and division. Addition is one of the fundamental arithmetic operations. A fast and accurate operation of a digital system is greatly influenced by the performance of the resident adders. The most important parameter for measuring the quality of adder designs is propagation delay, and area.
The block diagram of the closed-loop FOG is shown in Fig. 6. The detector detects the interference intensity signals of the optical fiber ring and converts it into a voltage signals. The analog / digital (A / D)converter acquires the signals and outputs the digital signal to the DSP. Demodulation, integration, ladder wave generation and square-wave modulation generation are completed by the DSP. While the DSP outputs digital velocity signals, closed-loop modulation signals are input into the E-O modulator. Thus, a closed-loop control is established.
This thesis investigates and implements the use of a microprocessor called Digital Signal Processors (DSP) as a controller in the design of a low power inverter used in Fuel Cell energy source. The fuel cell used in this research is a Heliocentris “Constructor”, a 50W proton exchange membrane (PEM) fuel cell. Fuel Cells are becoming popular and are likely to be used in applications such as a backup power, portable electronic devices, independent power source generator, promising alternative fuel for vehicles and a source generator to supply the electrical grid.
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The removal or filtering of noise in ECG signal has remained a classical problem and more worrisome is the fact that Powerline interference is a constituent part of the ECG waveform. From results, the magnitude response of fig 7 indicates that the filter is very stable, and therefore the coefficients of the filter cannot upset the filter stability. A condition of steady state output is therefore guaranteed. The phase response of fig 8 shows that the filter is of linear phase which is desirable in processing complex signals like ECG signals. This ensures that multiple frequency signals do not suffer differential phase shifts, and as well the filter does not make the required intelligent signal tow a wrong position which leads to erroneous clinical diagnosis of the patient. From fig. 9, the power of the ECG signal corrupt with 50Hz powerline interference before filtration is (3.438dB) and from fig. 10, the power of the corrupt ECG signal at 50hz after filtration is (-10.53dB). This implies that the fitter removes the Powerline Interference in the noisy ECG signal. The conclusion from the results therefore is that Power Line Interference has been successfully and efficiently removed by the Modified Triangular Window Based FIR filter.
HYSTERESIS BAND TECHNIQUE: - This control technique requires defining upper hysteresis band limit and lower hysteresis band limit. In open loop control strategy, the variation in output DC voltage is common problem if load is variable, but we can get steady output if close loop strategy is used. In close loop control, output current signal is compared with reference current signal which is given. Which decrease the error in output and gives desired output. The generated gate pulses can be controlled by PI or PID controllers. These signals are for power switching devices, when upper and lower limits of hysteresis bands are exceeded. In this technique, the power switching devices will not be switched if any major error is there. We can use Ziegler-Nichols method for tuning of PID controllers.
A Software Radio system is a transmitter and receiver system that uses digital signal processing for coding, decoding, modulating and demodulation the data. This paper focus on using the IEEE 802.11a specification to create a software radio. The feasibility of using Math works’ Simulink and Texas Instrument’s Code Composer Studio to design, test, and prototype an OFDM software radio system on a Texas Instruments CDSK6713 DSP development board was studied. Among the subjects examined were communication with the board through real time data exchange (RTDX), quadrature amplitude modulation (QAM), orthogonal frequency division multiplexing (OFDM), frame and carrier synchronization, and issues with Simulink DSP code generation for prototyping.
where A= , is the complex envelope of the two polarization components of the optical field, is the electric field component of a signal propagating in one polarization, is the electric field of the component propagating in the orthogonal polarization, α is the loss coefficient, γ is the nonlinear coefficient , is group velocity dispersion coefficient, z is distance of propagation.Chromatic dispersion effect is measured by dispersion parameter D where . In the above Manakov equation the term with the nonlinear parameter γ represents the nonlinear effects due to Kerr nonlinearity which arises due to power dependent refractive index of fiber and describes intra channel nonlinear effects .
ABSTRACT: Modifying any type digital based hardware architecture and reducing the hardware system power, it’s speed and the complexity level where VLSI technology is used . The process of filtering is mainly used in DSP and DIP real world applications as well and its work is to remove the noise in original signal or image. The filter architecture with an optimized process is used for reducing its processing time and to increase the performance of the system. In several digital signal processing (DSP) area adaptive digital filters find wide applications.Here a low- complexity filter design using the MCM scheme is presented with block implementation of fixed FIR filtersthe proposed structure involves significantly less energy per sample (EPS) and less area delay product (ADP) than the existing block implementation of direct-form structure for medium or large filter lengths, while for the short-length filters, the block implementation of direct-form FIR structure has less ADP and less EPS than the proposed structure. From the simulation results, we find that the proposed design offers large efficient output when compared to the existing outputs. Here the digital architecture based VLSI technology is used to modify the FIR filter architecture and this architecture uses a novel partial product generator which is generally used to alter the efficient architecture inorder to implement a delayed least mean square adaptive filter by using three co-efficient input.This algorithm is used to reduce the path delay and also to improve the speed when compare to proposed methodology.