dynamic voltage scaling (DVS)

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Dynamic Voltage Scaling with Feedback Scheduling for Real-time Embedded Systems

Dynamic Voltage Scaling with Feedback Scheduling for Real-time Embedded Systems

Prior research on DVS for hard real-time system was primarily concerned with guaranteeing the schedulability of the task sets while energy consumption is mini- mized. But in a dynamic real-time environment where the task execution time varies significantly from job to job, a DVS scheduler should be able to adapt to the ever- changing workloads as fast as possible. One important performance metric of such a system is how fast the DVS scheme can adjust the processor speed according to differ- ent workloads so that energy consumption is significantly reduced. To address this is- sue, we propose a framework called feedback dynamic voltage scaling (feedback-DVS). In this framework, we consider the scheduling problem in hard real-time systems with the earliest deadline first (EDF) policy. This framework is based on feedback control that incrementally corrects system behavior to achieve its energy objective, while the hard real-time timing requirements are still preserved. We assume that the processor can operate at several discrete voltage/frequency levels, which reflects contemporary processor technology with support for DVS. When there is no task running on the processor, the processor enters an idle state at a particular voltage/frequency level, usually the lowest voltage/frequency level on that processor.
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Dynamic Voltage Scaling Aware Delay Fault Testing

Dynamic Voltage Scaling Aware Delay Fault Testing

This paper presents a first approach to a testing strategy for delay faults in Dynamic Voltage Scaling systems. Our study shows that we do not need to use the lowest operating voltages to detect certain types of faults. From the transmission gate open simulation it is evident that low to mid-range voltages give sufficient fault coverage. In general testing at lower operating voltages is only required for certain types of faults such as transmission gate opens and bridging faults. On the other hand, weak resistive opens that cause delay faults are best tested at higher operating voltages. Simulation results both of a simple inverter chain circuit and a more complicated multiplier circuits support our conclusions. The overall conclusion is that in order to guarantee the quality of DVS systems, it will be necessary to select a number of voltage-specific delay fault tests, in addition to voltage-independent stuck- fault tests. Initial testing can be done at the highest operating voltage and this will reduce the time and cost of the test. The escaped defects can be detected at lower mid-range voltages without the need to go to the lowest voltages. Future work will aim to find an optimal set of voltage/fault test pairs.
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General Purpose Intra-Operation Dynamic Voltage Scaling.

General Purpose Intra-Operation Dynamic Voltage Scaling.

They are often powered from renewable sources or long term batteries, in some cases lasting over 10 years [17]. The responsibilities of a node on the network are minimized so as to achieve such a long lifespan. Dynamic voltage scaling techniques have been employed to decrease the energy consumption of these devices [18]. Due to the step-wise nature of their task sets, WSNs respond better to DPM schemes as the energy management technique, with DVFS employed during the active period. These systems are an excellent example of where IODVS would be ideal because of their typically short duty cycles.
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Feedback EDF scheduling exploiting hardware-assisted asynchronous dynamic voltage scaling

Feedback EDF scheduling exploiting hardware-assisted asynchronous dynamic voltage scaling

Feedback control was also proposed for energy-aware computing in previous work, such as those by Varma [23], Lu [17] and Minerick [18]. Varma et al. present a feedback-control algorithm where the previous work- load execution history is used to predict the future workload behavior by a discrete-time PID function. The combination of the proportional, integral and derivative part of the PID function provides good es- timation across different applications insensitive of the change of their parameters [23]. Lu et al. describe a formal feedback-control algorithm combined with dy- namic voltage/frequency scaling technologies. While Varma and Lu’s work targets soft real-time/multimedia systems, our feedback DVS scheme focuses on hard real-time system where timing constraints must not be violated. A general energy management scheme with feedback control is proposed by Minerick et al. [18]. Av- erage energy usage is achieved by continuously adjust- ing the voltage/frequency of a processor to meet the energy consumption goal. The objective of their work is to obtain low energy consumption for general pur- pose systems while our work targets hard real-time sys- tems with deadline requirements.
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Overhead Conscious Voltage Selection for Dynamic and Leakage Power Reduction of Time Constraint Systems

Overhead Conscious Voltage Selection for Dynamic and Leakage Power Reduction of Time Constraint Systems

Voltage selection approaches can be broadly classified into on-line and off-line techniques. In the following, we restrict ourselves to the off-line techniques since the presented approaches fall into this category, where the scaled supply voltages are calculated before design time and then applied at run-time according to the pre-calculated voltage schedule. There has been a considerable amount of work on dynamic voltage scaling. Yao et al. [16] proposed the first DVS approach for single pro- cessors systems which can dynamically change the supply voltage over a continuous range. Ishihara and Yasuura [9] modeled the discrete voltage selection problem using an integer linear programming (ILP) formula- tion. Kwon and Kim [11] proposed a linear programming (LP) solution for the discrete voltage selection problem with uniform and non-uniform switched capacitance. Although this gives the impression that this prob- lem can be solved optimally in polynomial time, we will show in this paper that the discrete voltage selection problem is indeed NP-hard and, hence, no optimal solution can be found in polynomial time, for example using LP. Dynamic voltage scaling has also been successfully applied to heterogeneous distributed systems, in which numerous processing ele- ments interact via a communication infrastructure, mostly using heuris- tics [7, 12, 19]. Zhang et al. [17] approached continuous supply voltage selection in distributed systems using an ILP formulation. They solved the discrete version through an approximation.
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Overhead Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time Constrained Systems

Overhead Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time Constrained Systems

Voltage selection approaches can be broadly classified into on-line and off-line techniques. In the following, we restrict ourselves to the off-line techniques since the presented approaches fall into this category, where the scaled supply voltages are calculated before design time and then applied at run-time according to the pre-calculated voltage schedule. There has been a considerable amount of work on dynamic voltage scaling. Yao et al. [16] proposed the first DVS approach for single pro- cessors systems which can dynamically change the supply voltage over a continuous range. Ishihara and Yasuura [9] modeled the discrete voltage selection problem using an integer linear programming (ILP) formula- tion. Kwon and Kim [11] proposed a linear programming (LP) solution for the discrete voltage selection problem with uniform and non-uniform switched capacitance. Although this gives the impression that this prob- lem can be solved optimally in polynomial time, we will show in this paper that the discrete voltage selection problem is indeed NP-hard and, hence, no optimal solution can be found in polynomial time, for example using LP. Dynamic voltage scaling has also been successfully applied to heterogeneous distributed systems, in which numerous processing ele- ments interact via a communication infrastructure, mostly using heuris- tics [7, 12, 19]. Zhang et al. [17] approached continuous supply voltage selection in distributed systems using an ILP formulation. They solved the discrete version through an approximation.
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Feedback dynamic voltage scaling DVS-EDF scheduling: Feedback dynamic voltage scaling DVS-EDF scheduling: Correctness and PID-feedback

Feedback dynamic voltage scaling DVS-EDF scheduling: Feedback dynamic voltage scaling DVS-EDF scheduling: Correctness and PID-feedback

the energy onsumption for task sets (with onstant atual. exeution times equal to 50% of the WCET under both the[r]

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Optimization of Power in C-MOS Circuit

Optimization of Power in C-MOS Circuit

DVS the supply voltage is adjusted to meet the target delay using an on-chip delay monitor in a hardware feedback loop. Performance degradation is a direct consequence of supply voltage reduction. In order to maintain the required throughout, dynamic voltage scaling (DVS) systems are used to adjust the supply voltage according to throughput requirements.

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Considering Power Variations of DVS Processing Elements for Energy Minimisation in Distributed Systems

Considering Power Variations of DVS Processing Elements for Energy Minimisation in Distributed Systems

Dynamic voltage scaling (DVS) is a powerful technique to re- duce power dissipation in embedded systems. Some efficient DVS algorithms have been recently proposed for the energy reduction in distributed system. However, they achieve the energy savings solely by scaling the system task with re- spect to the timing constraints, while neglecting that power varies among the tasks executed by DVS processing elements (DVS-PEs). In this paper we investigate the problem of considering DVS-PE power variations dependent on the ex- ecuted tasks, during the synthesis of distributed embedded systems and its impact on the energy savings. Unlike pre- vious approaches, which minimise the energy consumption by exploiting the available slack time without considering the PE power profiles, a new and fast heuristic for the volt- age scaling problem is proposed, which improves the voltage selection for each task dependent on the individual power dissipation caused by that task. Experimental results show that energy reductions with up to 80.7% are achieved by integrating the proposed DVS algorithm, which considers the PE power profiles, into the co-synthesis of distributed systems.
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EFFECTIVE ANALYSIS OF POWER TECHNIQUES FOR EMBEDDED SYSTEMS AND ITS APPLICATIONS

EFFECTIVE ANALYSIS OF POWER TECHNIQUES FOR EMBEDDED SYSTEMS AND ITS APPLICATIONS

Gate level power optimization, Multi VDD, clock gating Dynamic recurrence scaling (DFS), Dynamic voltage scaling, (DVS), Dynamic power management, Power gating, memory optimization techniques. Programming optimization techniques, for example, Low power transport encoding, Reconfigurable direction encoding, and Instruction pressure, Object code consolidating and decompression, Hardware programming dividing, Instruction level power optimization, Control information stream changes, are executed on processors, Memory, SoC, IPCORE, Interfaces. These techniques with applicable papers are talked about in this area.
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Dynamic and Leakage Power Composition Profile Driven Co Synthesis for Energy and Cost Reduction

Dynamic and Leakage Power Composition Profile Driven Co Synthesis for Energy and Cost Reduction

Energy reduction is an essential consideration in the design of embedded systems. Based on the fact that there are periods when applications do not require the maximum performance provided by the processing elements (PEs), a number of dynamic voltage scaling (DVS) [2-4] and adaptive body biasing (ABB) [5-8] techniques have been reported which enable a trade-off between energy and performance. DVS scales down the circuit supply voltage and operational frequency to reduce dynamic power, whilst ABB increases the circuit threshold voltage through body biasing to reduce leakage power. DVS is effective in reducing dynamic power, however, in deep sub-micron (DSM) designs, the leakage power contributes significantly to the total power consumption [9]. As an example, in [5] it was demonstrated that the overall leakage power of six benchmarks is only 9.8% of the total power for 0.35µm technology, but it is 56.2% for 0.07µm technology. In [10], it was shown that ABB would become comparable to DVS in achieving energy saving for future technologies. The energy reduction techniques reported in [2-8] employ either DVS or ABB to reduce energy dissipation.
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Synthesizing Energy Efficient Embedded Systems with LOPOCOS

Synthesizing Energy Efficient Embedded Systems with LOPOCOS

way to tackle the problem of reducing the energy dissipation is the usage of system level power management techniques to trade-off system performance against power dissipation. One of the most promising techniques is dynamic voltage scaling (DVS). By conjointly reducing supply voltage and operational frequency, DVS is able to reduce the energy consumption significantly. Since the reduction of the operational frequency is equivalent to the reduction of the system performance, this technique is applicable to applications where the system schedule shows periods of idleness or periods where a reduced performance can be tolerated. The field of DVS finds it roots in [41], where its usability was demonstrated considering a desktop computer environment. The dynamical and conjoint adjustment of supply voltage and operational frequency, to satisfy the application needs, was shown to lead to superior power savings compared to dynamic power management (switching off of idle components), when both techniques are applicable [20]. This fact explains why DVS is attracting considerable attention from both academia and industry. Most major digital processor vendors have recently introduced DVS enabled processor types [25, 3, 2]. Many research has focused on the scheduling aspects for DVS, however, often making the assumption of single processor systems [22, 20, 38, 27]. The trends towards co-design methodologies and dynamic voltage scalable processors indicate the need for co-design techniques which support the consideration of DVS processors to synthesise energy-efficient embedded systems. Such a co-design framework will be presented in this paper.
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Power efficient SRAM cell using T NBLV Technique

Power efficient SRAM cell using T NBLV Technique

An efficient 6T SRAM cell is developed using Transient Negative Bit line voltage (T-NBLV) technique. The design is implemented in tanner tool with 90nm technology. The evaluated simulation parameters are compared with the SRAM implemented using ultra Dynamic Voltage Scaling (UDVS) technique. The obtained results shows that the SRAM implemented using Tran- negative bit line voltage (T-NBLV) technique gives better results as compared to SRAM implemented using UDVS technique.

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PTMAC BASED ON RAZOR FOR ENERGY REDUCTION IN DSP

PTMAC BASED ON RAZOR FOR ENERGY REDUCTION IN DSP

The power optimization is achievable by dynamic voltage scaling using the fault tolerant technique by improving the accuracy and/or timing performance against power. Energy improvements have a strong dependency on the delay distribution of the circuit and the characteristics of the input signal. The fault tolerant technique is implemented using Razor approach. The target power is also obtain by using the programmable truncated multiplier (PTMAC) at the expense of degradation of the output signal to noise ratio. In the DSP architecture the combination of PTMAC and fault tolerant technique are used to reduce the supply voltage below the critical level. Truncated multiplication timing modulation properties are analysed and demonstrated using Xilinx 12.1. Finally the two techniques are upgrade the energy saving beyond that expected in the DSP architecture.
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Dynamic Voltage and Frequency Scaling for Wireless Network-on-Chip

Dynamic Voltage and Frequency Scaling for Wireless Network-on-Chip

This section accounts the bandwidth and latency penalty for implementing DVFS mechanism on NoC architectures. Fig. 14 shows the peak achievable bandwidth for NoC architectures with and without DVFS. It is clear that there is bandwidth penalty with the dynamic voltage scaling on wired and wireless system regardless. However, the penalty that is to be accounted for is only 3-4% of the peak bandwidth that was achieved without implementing DVFS. The difference in bandwidth is mainly due to the fact that the links and input buffers are switched between different voltages and frequency values. The bandwidth reduction is the penalty for frequent switching characteristics of the DVFS policy. Fig.16 clearly shows the voltage fluctuations that does not follow the predictions because of the smaller steps. Hence there is bandwidth and latency limitations for different traffic patterns.
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Leakage Power Reduction Techniques for
Nanoscale CMOS VLSI Systems and Effect of
Technology Scaling on Leakage Power

Leakage Power Reduction Techniques for Nanoscale CMOS VLSI Systems and Effect of Technology Scaling on Leakage Power

Abstract—The rise in technology has demanded the use of more and more components on chip. This rise has led to rise in power dissipation and a major challenge for circuit designers . Due to scaling, the reduction of threshold voltage in CMOS circuits increases the sub threshold leakage current which leads to the static power dissipation. It has been observed that leakage power is the major contributor for power dissipation and directly affecting the battery life of circuits.In order to restrain thisleakage power, a comprehensive study and analysis of various leakage power reduction techniques have been presented in this paper. Also the effect of technology scaling on the leakage power is analysed. MICROWIND tool is used for this approach to analyse the power dissipation at different technologies such as 50nm, 90nm, 120nm and 180nm at a given power supply.
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A Survey of Dynamic Power Saving Strategies in Real Systems Sai Kiran Talamudupula

A Survey of Dynamic Power Saving Strategies in Real Systems Sai Kiran Talamudupula

Adagio [21] discusses critical path analysis to identify the tasks to be slowed down as it does not provide the user with an option to choose a performance loss. The workload prediction mechanism used in Adagio is similar to the history predictor with some feedback added, such that the future behavior of a communication call is predicted based on its last invocation. Lim et al. [19] propose a scheme that applies DVFS during communication phases in MPI applications. Dynamic determination of communication phases and selection a suit- able processor frequency to minimize energy consumption are the key features of this scheme. This strategy does not apply DVFS in computation portions of an application and, therefore, may not save a significant amount of energy for an application that has a relatively low communication activity.
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Energy Saving Strategy Based on Profiling Milan, Kanak Khanna

Energy Saving Strategy Based on Profiling Milan, Kanak Khanna

The dynamic voltage and frequency scaling (DVFS) mechanism reduces the operating frequency and voltage of the processor on-the-fly during application execution, thereby reducing the dynamic power consumption. DVFS is applied by writing a specific value to the IA32_PERF _CTL [1][2] model specific register (MSR) in Intel processors and it is an architectural register which means it is present in different generations of Intel processors with the same address.

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Dynamic voltage and frequency scaling with multi-clock distribution systems on SPARC core

Dynamic voltage and frequency scaling with multi-clock distribution systems on SPARC core

Due to the improvements in die size and process technology, chip power density has increased drastically over the years [1] [7] [8]. On-chip thermal and power man- agement has been developed with adaptive designs that monitor temperature and power consumption, and dynamically optimize the operating point for maximal power effi- ciency in real time [4] [9]. This thesis provides an in depth look at the latest dynamic power management techniques implemented in different architectures. The objectives and contributions of this thesis are outlined as follows:

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Abstract-The trend of smaller, portable and more capable electronic devices gives rise to a number of significant design and implementation problems of which the limited energy supply is the most determining factors. All these issues are jointly present in the field of Wireless Sensor Networks which is consequently a suitable context for research opportunities. Radio communication has highest energy consumption. To reduce the energy and power parallel prefix technique is used. This base paper describes the design and implementation of newly proposed folded tree architecture. Folded tree architecture has two phases. They are trunk and twig phase. The power is reduced to compare to the existing methods. For further performance improvement Dynamic Voltage Frequency Scaling concept introduced along with Digital Signal processor architecture. This paper is on a low-power real-time scheduler integrated into a common Linux is operating system. The low power schedule aims at reducing energy consumption in a system and uses Dynamic Voltage and Frequency Scaling to achieve its goal. The major advantage of Dynamic Voltage and Frequency Scaling is the output frequency, phase and amplitude can be precise and also rapidly manipulated under the control of a DSP. These combined characteristics have made this technology popular in military, radar and communication systems. The digital circuits used to implement signal processing functions do not suffer the effects of thermal drifts aging and component variations associated with their analog counterpart.
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