FPGA implementations
High Throughput and Area Efficient FPGA Implementations of Data Encryption Standard (DES)
... high-throughput FPGA implementations of the DES which are developed using the Xilinx FPGA ISE design ...proposed implementations achieve high throughput-to-area ...matching FPGA devices ...
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SCA Resistance Analysis on FPGA Implementations of Sponge based MAC-PHOTON
... Abstract. PHOTON is a lightweight hash function which was proposed by Guo et al. in CRYPTO 2011. This is used in low-resource ubiquitous computing devices such as RFID tags, wireless sensor nodes, smart cards and mobile ...
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Efficient FPGA implementations of volterra DFES for optical systems
... high-throughput FPGA implementations of Volterra- based DFEs (VDFEs) are ...the FPGA-specific ...the FPGA technology can be used as a candidate platform to achieve high-speed ...
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Efficient FPGA Implementations of LowMC and Picnic
... first FPGA implementation of Picnic ...software implementations of Picnic and sim- ilar hardware ...our FPGA takes ...software implementations by a factor of ...
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FPGA Implementations of the Humming Bird Cryptographic Algorithm Ganam Thirumalesh & T Krishnarjuna Rao
... An implementation of less cost smart devices like positive RFID tags or smart cards takes low area and low power consumption while considering throughput as a secondary interest. Usually, an RFID reader device used to ...
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Title: IMPLEMENTATION OF LOEFFLER ALGORITHM FOR LENGTH 2N IDCT
... hardware implementations of 8x8 DCT and IDCT on different FPGA technologies using the modified Loeffler ...recent FPGA families of Xilinx, Altera, and ...DCT/IDCT implementations indicate ...
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High speed FPGA model implementation for ferroelectric and ferromagnetic transducers operating in hysteretic regimes
... (FPGA) implementations of the homogenized energy model for ferroelectric and ferromagnetic materials, and show that this approaches can yield up to over two orders of magnitude improvement in computation ...
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Characterizations of FPGA chip electromagnetic emissions based on GTEM cell measurements
... entire FPGA test board inside the GTEM cell instead of mounting it at the wall of the ...the FPGA board is properly shielded with metallic enclosure to avoid unintentional contribution from supporting ...
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Analog Implementations of Auditory Models
... ANALOG IMPLEMENTATIONS OF AUDITORY MODELS A N A L O G I M P L E M E N T A T I O N S OF A U D I T O R Y M O D E L S Richard F Lyon Apple Computer, Inc Cupertino, CA 95014 and California Institute of Te[.] ...
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Traditional Database Implementations in HyperCard
... STANDARD BUTTONS Four buttons on the data card perform conventional HyperCard functions: the help button in the top right corner provides on-line help through the system that is being us[r] ...
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Higher-Order Threshold Implementations
... Abstract. Higher-order differential power analysis attacks are a seri- ous threat for cryptographic hardware implementations. In particular, glitches in the circuit make it hard to protect the implementation with ...
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DEUCE : a test-bed for evaluating ESL competence criteria
... prototype implementations for four sample criteria are under ...The implementations for these criteria will provide three differing tests for each of the four ...
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Improved Lightweight Implementations of CAESAR Authenticated Ciphers
... Subsequent to the standardization of AES-GCM, there were early attempts to provide dedicated LW authenti- cated encryption schemes. One example is Hummingbird-2, which required 2.2 kGE (Kilo-Gate Equivalent) of area in ...
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RDA in Europe : Implementations and perceptions
... Once the case studies were sorted into the three groups, the US articles were analysed by thematically coding them in six themes based on the preliminary literature review and the resear[r] ...
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Side-Channel Analysis of MAC-Keccak Hardware Implementations
... In this paper we analyze the algorithm of Keccak and design a new attack method on the first round output of MAC-Keccak. We propose new side-channel leakage models specifically for hardware MAC- Keccak ...
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FPGA-Based Acceleration of Expectation Maximization Algorithm using High Level Synthesis
... 15 AOC automatically generates pipelines (if instruction is provided) and memory interaction between kernels and different memory regions. Depending on FPGAs and applications a full compilation takes 4-8 hours. In this ...
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Standby And Active Leakage Current Control And Insertion Power Network Synthesis
... transistor implementations because the P/G network consists of three components: a permanent power network, a virtual power network and an array of the sleep transistors that connect the permanent and virtual ...
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Smart Grid Technologies and Implementations
... Since 2010, papers and researches on smart grid have paid attention to intelligent system monitoring. Some of the last implementations of Power system frequency monitoring network (FNET) applications on wide-area ...
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Theoretic Basis and Technical Implementations of CT Perfusion in Acute Ischemic Stroke, Part 2: Technical Implementations
... Issues including radiation dose-reduction strategies, methods of correcting arterial input function AIF delay, the effect of the laterality of AIF choice, vascular pixel elimination, the[r] ...
Lack of a type-2 glycosyltransferase in the fish pathogen Flavobacterium psychrophilum determines pleiotropic changes and loss of virulence
... Under the assayed conditions, most of the extracellular proteolytic activity detected from the wild-type strain is caused by the metalloproteases Fpp1 and Fpp2 whose encoding genes fpp2-fpp1 form an operon [18]. As shown ...
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