Abstract— This paper presents the simulation of reentrant excitation-conduction of cardiac cells realized by coupling 80 active circuits in one dimensional (1D) ring-shaped based on FitzHugh-Nagumo (FHN) model. 1D ring-shaped cable model is designed using Simulink in order to simulate an action potential signal and its conduction for a hardware design by using HDL Coder to automate the model for Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) code generation. Then, the VHDL design is functionally verified on a Field Programmable Gate Array (FPGA) Xilinx Virtex-6 board using HDL Verifier proving the model through FPGA-in-the- Loop (FIL) co-simulation approach. It can then be downloaded into a target FPGA device for real-time simulations. This novel approach of prototyping cardiac reentrant excitation-conduction provides a fast and effective FPGA-based hardware implementation flow towards a stand-alone implementation to perform complex real-time simulations compared with manual HDL designs.
There is a rapid growth in the extreme increase in Industrial production, particularly in the domain of Automation process. This is due to the extensive involvement of Automation which is possible in the industries and the ease of maintenance. This leads to an efficient way of improving the production of the industrial process and reduces number of workers. Hence this paper brings out the flexibility of Field Programmable Gate Arrays which used to control two machines loop fixing machine, bottom sealing and cutting machine. Here we use the pneumatic functions instead of motor which controls the machine through FPGA and helps to reduce the power consumption. The design has been described using VHDL (VHSIC Hardware Description Language) and implemented in hardware using FPGA (Field Programmable Gate Array).
An All-digital closed-loop (ADCL) signal processor that could be used in the all fiber FOG was developed using PID controller. This technique possesses several potential advantages over the others, such as immunity to optical intensity, no requirement of expensive IO modulator, flexibility, and possibility of the highest resolution. From the series of experiments, we could conclude that the ADCL processor resolved 0.57- radians phase difference, but with a fairly big electronics-generated offset by open wires and optics generated drift with temperature change. However, we believe that the ADCL processor, properly packaged and equipped with an appropriate stabilization circuitry for the phase modulator, would be one of the competitive signal processors for an all-fiber FOG. The Digital Controller used in this system is a PID controller with the help of the PID Algorithm as it is also having some problems so those can be overcome by implementing the FOG in FPGA. It is used for reducing the analog components.PID controller results are to be calculated for Closed loop fiber optic gyroscope CLFOG by using LABVIEW.
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing—hence "field-programmable." An FPGA is a field programmable device suitable for switching application in power electronics. It can be easily programmed to design a pulse width modulator (PWM) for control applications. Further its fast switching capability and easy implementation of soft computing algorithms make it preferred choice for power control system application and power quality. In this proposed work, the BDC converter will be implemented on FPGA after the simulation in Matlab.
The above hardware model can be implemented on an FPGA by designing the static region housing a soft processor to run the software for the control loop alongside the required interfaces to the PRRs and external sensors, actuators, or peripherals. Modern FPGA SoCs such as the Xilinx Zynq  and Intel Arria 10 SoC offer a tightly coupled ARM Cortex- A9 embedded processor and flexible FPGA fabric that can be reconfigured from the processor. Newer devices such as the Xilinx Zynq UltraScale+ and Intel Stratix 10 SoC offer even more capable ARM Cortex-A53 cores alongside additional hardware cores for functions such as real-time processing, security features, and high bandwidth memory (HBM). These architectures hence offer an ideal platform for a wide range of adaptive systems, offering sufficient computational capacity in software, alongside the high performance processing ca- pabilities of the FPGA fabric. We consider these ideal for the implementation of autonomous adaptive systems as they allow the tight coupling necessary to implement the above model, with flexible hardware capabilities through partial reconfiguration.
II. F IELD C OUPLING M ECHANISM OF C URRENT L OOP IC current loops are the primary radiation sources behaving as magnetic and electric dipoles to radiate undesired EMEs of IC . The coupling mechanism of a current loop on the TEM cell septum is investigated in . The IC pulsed currents are the consequence of transistor simultaneous switching activities of silicon die which driven by a clock signal. These currents are commonly drawn from source terminal and return via ground terminal of IC. Generally, the pulsed currents flowing along a path consists of package leads, wire bonding and interconnections on silicon die as shown in Fig. 2 (a). Fig. 2 (b) illustrates decomposition of the current
The stability, reliability and miniaturization of fiber optic gyroscope (FOG) are always the research focuses and difficulties. This paper presented a hardware design method for the digital closed loop control system of FOG based on FPGA. Based on a large number of experiments, this paper summarized the parameter demands for each module of closed loop control circuit and designed a corresponding hardware circuit using FPGA. The proposed twice closed loop technique improved the zero offset stability of FOG. The using of FPGA brought the digital signal processing by software, the system reliability and agility enhancement as well as the system miniaturization. Particularly, we discussed the problems of component selection and the anti-jamming measures for PCB design to improve the performances of the system. We also developed some samples of FOG using this design method. The experiments and tests show that the proposed method is efficient and valuable. The zero-biases of all samples are all less than 0.075deg/h. Keywords: Fiber Optic Gyroscope, Hardware Design, Digital Closed Loop, Second Closed Loop, FPGA
Pipeline/Loop parallelism is known as Task in Intel FPGA SDK for OpenCL and the kernel is a single thread work-item. In GPUs, single thread work-item is used in data dependent sections and is inefficient. While processing single thread work-item, other processing units remain idle which is a waste of resources. Conversely, FPGA makes pipeline architecture by breaking down loop into multiple stages to resolves loop carried dependencies. Compiler pipelines each stage of a loop and launches next iterations as soon as loop carried dependencies have been resolved. The developer has no control over pipeline structure and scheduling. The only thing a developer can do is to reduce, remove or simplify loop carried dependencies.
In this work, wavelet based image fusion algorithm implemented on Xilinx platform studio EDK 11.1 FPGA Spartan 3E . It has been observed from the results that Handel-C performance for wavelet based image fusion in synthesis level is better than Verilog implementations. Besides, Handel-C language is introduced as a language for Software Engineers to quickly prototype software concepts in hardware using behavioral model. Our current efforts to efficiently implement image processing algorithms in both input image and output image taken from FPGA and synthesizing. proposed wavelet based image fusion processor on Xilinx Spartan3 FPGA chip demonstrated the efficiency of proposed architecture for wavelet based image fusion gray scale 256×256 images for real-time image processing applications.. However, the class of image processing algorithms considered in our work is limited to basic algorithm and further work on complex image processing algorithms need to be performed.
handcrafting to cover the conventional tools inadequacies. This paper introduces extensions to a previously reported CAD tool named DCSTech  which was created to automate the process of translating dynamic designs from VHDL into placed and routed circuits. The original version of the tool supported the Xilinx XC6200 family of FPGAs, and concentrated on the timing verification aspects of the problem. This paper reports on the extensions made to DCSTech to target the Xilinx Virtex family, and to enhance its capabilities. As a mainstream commercial FPGA, the design tool capabilities available with this family exceed those of the XC6200, allowing the designer to work more productively at a higher level of abstraction. By combining the Virtex platform’s capabilities with those of the extended DCSTech, the designer has the ability to specify designs in RTL/behavioural VHDL, place and route them and verify their timing. DCSTech’s back-annotation support has been extended to produce VITAL VHDL models suitable for DRL in addition to processing SDF timing information. This enables back-annotated timing analysis regardless of the level of abstraction at which the original design was produced.
Functionally speaking, logic devices can be divided into universal and specific devices. PLD (programmable logic device) is universal because it bears characters like self-defined logic functions, highly-integrated chips, excellent secrecy performance, etc. Therefore, it has been widely used in some complicated and fast-speed logic controlled circuits. At present, there are more than companies manufacturing programmable logic device CPLD/FPGA, among which, Altera, Xilinx and lattice are the three biggest companies. And Quartus II is the development software of Altera Company .
investigate the alternative FPGA LE architectures for improving the performance. We proposed the MUXs in FPGA logic blocks which increase the silicon area efficiency and logic density. In early commercial architectures, the MUX based logic blocks for FPGAs have succeeded. Consider 6-input LUT is essentially 64-to-1 MUX and 64 SRAM configuration cell but it can only realize a 4-to-1 MUX. In this paper we propose a six input LE based on a MUX4 which can realize a subset of six- input Boolean logic functions. A new hybrid complex logic block (CLB) contains a mixture of MUX4s and 6-LUTs. The proposed MUX4s can efficiently map all the input functions.
First connect supply to DE2-115 board & connect USB cable to laptop & to USB blaster of the board, compile code, assign pins, choose JTAG programming mode & download the program into target device. After design, compile & simulation done of complete PWM block, it is downloaded into FPGA device EP4CE115F29C7.We can give input word ‘din’ as different 8-bit input combination to see how the output of FPGA varies. This input can be given by 8 switches present on FPGA boardand the output can be seen by one LED whose pin number has been assigned to PWM output.The clock for the architecture was provided by clock present on FPGA board. As we change the “din” value on the FPGA board by different configuration of switches. The snapshot of FPGA board with different 8-bit input value is shown with different LED intensity, if the input value is large then the intensity of LED is more and if the input value is small then the intensity of LED is less.
As already discussed in the previous section, the tool flow starts with a plan- ning phase. This phase must be performed entirely manually by the designer. In Section 4.2.3, several suggestions and formulas are provided that might help the designer to complete the planning phase. After the planning phase, the floorplan of the static design and modules are created in GoAhead by using its GUI and scripting language. Based on these floorplans, GoAhead generates the corresponding VHDL templates and TCL scripts. These files are respectively merged into the existing VHDL files and included in Vivado. Then, we provide TCL scripts to automate the tool flow in Vivado. The final result is a full bitstream (static system) and a partial bitstream for each module. The partial bitstreams are generated by using the tool BitMan . Once the bitstreams for the static system and modules are generated, we can program the bitstreams into the FPGA. The full bitstream, which represents the static system, should be configured first. Later on, during run-time, the modules can be configured by using the partial bitstreams.
The biggest challenge with synthesizing an out-of-order superscalar processor to an FPGA is efficiently mapping its wide data paths and many multi-ported RAM and CAM structures to FPGA resources. An FPGA is comprised of large dual-ported SRAMs called Block RAMs, special function units such as for digital signal processing, and configurable logic blocks (CLB) which are further broken into slices. Figure 4.1 shows a CLB with two slices, each having an input and output for communicating to slices within neighboring CLBs, and access to a switch matrix for global communication. CLBs populate the majority of the FPGA and are arranged in a grid, as shown in Figure 4.2. Slices can communicate directly with the slice above and below through a 1-bit uni-directional path. All other communication must pass through one or more switch matrices. Communication within a slice is fastest but slows down as more hops are needed to reach the slice within another CLB. Figure 4.3 shows the number of hops that it takes to communicate between CLBs for a Virtex-4 and Virtex-5 FPGA. Virtex-5 provides a significant improvement to the number of CLBs within two and three hops but logic should be contained within a slice or one hop away for improved performance.
This chapter presents the details about literature review of Implementation of RISC Processor Architecture in Simulink and FPGA. It consist reviews on related paper. There are 12 papers involved, but in this project, I will focus on 3 main papers, which are Implementation of RISC Processor in FPGA, FPGA Prototyping of a RISC Processor Core for Embedded Application and Design of FPGA Controlled Power Electronics and Devices Using MATLAB Simulink. The main paper for reference is the Implementation of RISC Processor in FPGA. All the details about the paper will be explained later on.
However, both FPGA and ASIC have relatively limited computing resources, memory, and I/O bandwidths, therefore it is challenging to develop complex and massive DNNs using hardware accelerators. For ASIC, it has a longer development cycle and the flexibility is not satisfying. Chen et al.  presented a ubiquitous machine-learning hardware accelerator called DianNao, which initiated the field of deep learning processor. It opens a new paradigm to machine learning hardware accelerators focusing on neural networks. But DianNao is not implemented using reconfigurable hardware like FPGA, therefore it cannot adapt to different application demands.
The Centering Controller enables the three blocks in series using FSM. After the adder’s result is available, a 16-bit divider is used to compute the mean of the four results over 128 samples according to Equation (2.4). Moreover, the ROM that holds the input requires 128 cycles to load the 128 input samples to the Centering block. In addition, the adder, the divider and the subtractor require 3 clock cycles to complete their task. According to the simulation results, the Centering output is available after 131 clock cycles. Table 3.8 shows the Centering FPGA resources utilization report. Table 3.9 shows the maximum frequency when the input the CLK_cen frequency is 100 MHz. It is measured
The new evolution in reconfigurable multiprocessor systems is the run-time reconfigurable system. This type of systems adds the dynamic reconfigurability feature of FPGAs to the power of having multiple processors. It adds a new degree of freedom in the design of multiprocessor systems. This freedom allows designers to adjust system performance at run-time obtaining better eﬃciency in accordance with the application. Here, they propose a “meet-in-the-middle” design flow, which is to combine traditional top-down design with bottom-up approach. The bottom-up design is possible due to run-time reconfigurability. It allows hardware to be re designed at run-time in order to obtain better eﬃciency in terms of speed, area, and power for a specific application. Depending on the context, a diﬀerent algorithm will be re-configured. They utilize the Dynamic Partial reconfigurable FPGA feature.
Efficient hardware architecture for direct 2D DCT computation and its FPGA Implementation- In this paper, we propose a low complexity architecture for direct 2D-DCT computation. The architecture will transform the pixels from spatial to spectral domain with the required quality constraints of the compression standards. In our previous works we introduced a new fast 2D DCT with low computations: only 40 additions are used and no multiplications are needed. Based on that algorithm we developed in this work a new architecture to achieve the computations of the 2D DCT directly without using any transposition memory. We defined Sk functions blocks to build the 2D DCT architecture. The Sk block perform 8 function depending on the control signals of the system. The number of additions/subtractions used is 63, but no multiplication or memory transposition is needed. The architecture is suitable for usage with statistical rules to predict the zero quantized coefficients, which can considerably reduce the number of computation. We implemented the design using an FPGA Cyclone 3. The design can reach up to 244 MHz and uses 1188 logic elements, and it respect the real time video requirements, Anas Hatim, Said Belkouch, Tayeb Sadiki.