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hardware/VLSI implementation

AVOID SYNCHRONIZATION LATENCY USING VLSI IMPLEMENTATION

AVOID SYNCHRONIZATION LATENCY USING VLSI IMPLEMENTATION

... The growing number of asynchronously-clocked cores in modern systems means that the negative performance impact of clock domain crossing latency is likely to increase. Two novel architectural solutions (data path ...

6

VLSI Implementation of Pipelined Fast Fourier Transform

VLSI Implementation of Pipelined Fast Fourier Transform

... A novel ROM-less and low-power pipeline FFT/IFFT for OFDM applications have been described in this paper. Considering the symmetric property of twiddle factors in FFT, we have designed a reconfigurable complex constant ...

6

VLSI Implementation of Cryptography Hash Algorithms

VLSI Implementation of Cryptography Hash Algorithms

... This ensures that identical blocks at different locations in the input message will return different hash values. The BLAKE designers also chose to include a salt variable in the compression function, adding more ...

14

An Overview of the Decimation process and its VLSI implementation

An Overview of the Decimation process and its VLSI implementation

... Digital Decimation process plays an important task in communication system. It mostly is applied in transceiver when the frequency reduction is required. However, the decimation process for sigma delta modulator is ...

8

VLSI Implementation of LiCi Cipher

VLSI Implementation of LiCi Cipher

... Round-based structures lay emphasis on low-area and power with higher latency. Pipelined architectures focus on moderate area with better performance and increased maximum operating frequency. Serialized architectures ...

8

VLSI Implementation of Neural Network
                 

VLSI Implementation of Neural Network  

... - The floating point arithmetic scheme (IEEE 754- Single precision format (32 bit) or Double precision format (64 bit)) offers the greatest amount of dynamic range and eliminates the need of processing the weights ,and ...

10

VLSI Implementation of Impulse Noise
Suppression in Images

VLSI Implementation of Impulse Noise Suppression in Images

... In the field of digital image processing, two applications of great importance are noise filtering and image enhancement. They are an essential part of any image processor whether the final image is utilized for visual ...

6

Design and Analysis of a maximum length 5-Bit Parallel Linear Feedback Shift Register using VHDL Structural Modeling

Design and Analysis of a maximum length 5-Bit Parallel Linear Feedback Shift Register using VHDL Structural Modeling

... ABSTRACT: Very Large Scale Integration is the latest most popular technology that has reduced the size of almost all electronic circuits and devices to a large extent. Out of the two coding languages for VLSI ...

8

Elliptic-curve cryptographic architectures for system-on-chip based on field programmable gate arrays

Elliptic-curve cryptographic architectures for system-on-chip based on field programmable gate arrays

... specialized hardware unit that purposes as a coprocessor. The implementation of public key cryptography in embedded systems performs slowly in ...The hardware-based accelerators are often the ...

19

Coding Techniques For Recycling Circuits In Its

Coding Techniques For Recycling Circuits In Its

... individual hardware architecture having a poor HUR To normalize the procedure parameters because of different CMOS technologies, the CMOS process scaling from the constant field theorem is used ...the ...

8

Design & Implementation of DDFS Using VLSI Technology
V Ashok Kumar & A Mahipal

Design & Implementation of DDFS Using VLSI Technology V Ashok Kumar & A Mahipal

... CORDIC algorithms have long been used in digital signal processing for calculating trigonometric, hyperbolic, logarithmic and other transcendental functions. The algorithm requires only shift and add operations and this ...

7

High throughput VLSI architecture for Blackman windowing in real time spectral analysis

High throughput VLSI architecture for Blackman windowing in real time spectral analysis

... designing hardware efficient, flexible window length setting and high throughput VLSI architecture using CORDIC whose implementation is quite economic in terms of ...the implementation using ...

6

Survey on Implementation of Dedicated Hardware for Encryption

Survey on Implementation of Dedicated Hardware for Encryption

... S-Box for SubByte and InvSubByte operation is implement using two method - Conventional BRAM implementation or combinational logic. Conventional BRAM has all pre-computed 256 values are stored in a ROM based ...

8

Hardware Implementation Of Dew Point Measurement

Hardware Implementation Of Dew Point Measurement

... PSoC implementation of dual sensor system presents a new methodology to approach sensor solutions using silicon based ...The implementation takes the advantage of dynamically configuration changing for ...

7

A Study on the Impact of Ethical Behaviour of Firms on Global Competitiveness Ranking

A Study on the Impact of Ethical Behaviour of Firms on Global Competitiveness Ranking

... on hardware utilization of VLSI architecture ...on hardware utilization of FM0 and Manchester ...reused VLSI architecture using SOLS technique for both FM0 and Manchester encodings is ...on ...

13

Fully Reused VLSI Architecture for DSRC Applications Using SOLS Technique

Fully Reused VLSI Architecture for DSRC Applications Using SOLS Technique

... on hardware utilization of VLSI architecture ...reused VLSI architecture using SOLS technique for both FM0 and Manchester encodings are ...on hardware utilization by two core techniques: Area ...

13

VLSI IMPLEMENTATION OF NEURAL NETWORK

VLSI IMPLEMENTATION OF NEURAL NETWORK

... Intelligence is the computational part of the ability to achieve goals in the world. This intelligence though a biological word, is realized based on the mathematical equations, giving rise to the science of Artificial ...

6

VLSI Hardware Modelling Of Multifunction GF Architecture for Cryptographic Devices

VLSI Hardware Modelling Of Multifunction GF Architecture for Cryptographic Devices

... In general advanced and high speed digital system designs includes an application of cryptography, error correction coding, computer arithmetic and logic, DSP and many more which depends on the competent insight of ...

8

Development of novel BMIP algorithms for human eyes affected with glaucoma and hardware implementation using VLSI based embedded systems

Development of novel BMIP algorithms for human eyes affected with glaucoma and hardware implementation using VLSI based embedded systems

... using hardware (VLSI techniques) in FPGA, the problem finally, being defined as “Simulation, development of bio-medical image processing algorithms of eyes affected with glaucoma & hardware ...

5

VHDL Implementation of Built in Generation of Functional Broadside Tests Using Fixed Hardware Structure
B Saidulu & P V Vara Prsada Rao

VHDL Implementation of Built in Generation of Functional Broadside Tests Using Fixed Hardware Structure B Saidulu & P V Vara Prsada Rao

... The hardware used in this paper for generating the primary input sequence A consists of a linear-feedback shift-register (LFSR) as a random source and of a small number of gates to focus on reducing test pattern ...

8

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