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high-level algorithm specification

Automatic Derivation of Statistical Algorithms: The EM Family and Beyond

Automatic Derivation of Statistical Algorithms: The EM Family and Beyond

... a high-level statistical model specification, uses power- ful symbolic techniques based on schema-based program synthesis and computer algebra to derive an efficient specialized algorithm for ...

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The functional dendritic cell algorithm: a formal specification with Haskell

The functional dendritic cell algorithm: a formal specification with Haskell

... A good choice of safe signal is to have a real value which increases in proportion to the observation of normal behaviour in the monitored system. In the SCAN dataset, we use the burstiness or rate of change of tcp ...

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High Level Synthesis using Learning Automata Genetic Algorithm

High Level Synthesis using Learning Automata Genetic Algorithm

... (RT)- level description. Once an RT-level design of a circuit is obtained, it can be transformed into a logic gate level netlist through logic synthesis, then into a layout via layout synthesis, and ...

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High level synthesis FPGA implementation of the Jacobi algorithm to solve the Eigen problem

High level synthesis FPGA implementation of the Jacobi algorithm to solve the Eigen problem

... an algorithm with relevant mathematical work- load, such as the ones mentioned before, has to be imple- mented in an FPGA, a great part of the design process consist in the partition of the system in small units ...

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Closed frequent itemset mining with arbitrary side constraints

Closed frequent itemset mining with arbitrary side constraints

... Application-specific side constraints are often added to an itemset mining problem to provide focus for the results. Some of these constraints are simple: excluding a certain itemset altogether, insisting that a certain ...

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Vascular segmentation in hepatic CT images using adaptive threshold fuzzy connectedness method

Vascular segmentation in hepatic CT images using adaptive threshold fuzzy connectedness method

... Ostu algorithm to calculate the parameters for affinity relations and assigning the seed with the mean value, it is able to reduce the influence on the segmentation result caused by the location of the seed and ...

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Optimizing Data Placement and Threads Management for Heterogeneous Computing.

Optimizing Data Placement and Threads Management for Heterogeneous Computing.

... The second category focuses on implementation-level optimizations, trying to better leverage underlying computing systems for acceleration. The most prominent example is the recent efforts in speeding up KNN ...

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Intelligent Agent Based Mapping of Software Requirement Specification to Design Model

Intelligent Agent Based Mapping of Software Requirement Specification to Design Model

... The actual blocks for the analog to digital converter can have more than one block and also multi-level blocks as appropriate. But the whole thing can be labeled in the knowledge base as one block (e.g. A2D as ...

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High level timing specification of instruction-level parallel processors

High level timing specification of instruction-level parallel processors

... There are also a variety of formalisms for specifying asynchronous and/or synchronous concurrent systems [Mil89] including Petri Nets, CCS, SCCS, ACP, CIRCAL, and CSP [Mil89, Mil93, Hoa85, Mil85, BRR87, Dav90]. Process ...

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P5 3 2 Adaptive Workflow Technology

P5 3 2 Adaptive Workflow Technology

... In a commercial Grid environment, the execution of processes is likely to cost money, yet the results may be of no use if that final step could not be completed. It is also possible that the choice of services for early ...

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FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis

FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis

... Traditionally, the performance of a processor could be increased in two simple ways: either through instruction level parallelism (ILP), which requires more complex and longer pipelines or by increasing the clock ...

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Formal Verification of Usage Control Models:A Case Study of UseCON Using TLA+

Formal Verification of Usage Control Models:A Case Study of UseCON Using TLA+

... UseCON is a usage control model that is characterised by extended expressiveness when compared with existing usage-based models (e.g., UCON [11]). Specifically, it may support authorisations that have logical relations ...

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A Timing driven Binding Algorithm for High Level Synthesis of Three dimensional Integrated Circuits

A Timing driven Binding Algorithm for High Level Synthesis of Three dimensional Integrated Circuits

... delays. High-level synthesis engines must consider accurate estimates of path delays to ensure that the resulting designs satisfy timing constraints ...timing-driven high-level synthesis ...

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Model-based Testing in Cloud Brokerage Scenarios

Model-based Testing in Cloud Brokerage Scenarios

... service specification lan- guage. The XML specification language was able to model adequately the two case studies described, and is also fairly close in its syntax to other service description lan- guages, ...

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The Primordial Soup Algorithm A Systematic Approach to the Specification of Parallel Parsers

The Primordial Soup Algorithm A Systematic Approach to the Specification of Parallel Parsers

... The Primordial Soup Algorithm A Systematic Approach to the Specification of Parallel Parsers The Primordial Soup Algorithm A S y s t e m a t i c Approach to t h e S p e c i f i c a t i o n of Parallel[.] ...

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mrp beta slides

mrp beta slides

... Specification of interest rate process strongly influences plant-level and aggregate investment response to shocks Specification of aggregate shock process strongly influences the respon[r] ...

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FPGA-Based Acceleration of Expectation Maximization Algorithm using High Level Synthesis

FPGA-Based Acceleration of Expectation Maximization Algorithm using High Level Synthesis

... A sequential version of EM-GMM algorithm was implemented in CPU to ensure the accuracy of EM-GMM algorithm running on FPGA based accelerators. This implementation was done after FPGA implementation to ...

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The Algorithm Steering and Trigger Decision mechanism of the ATLAS High Level Trigger

The Algorithm Steering and Trigger Decision mechanism of the ATLAS High Level Trigger

... geometrical information provided by the LVL1 in terms of Regions of Interest (RoIs) where the first Trigger level has already found interesting physic signal. By limiting the reconstruction to the RoIs, when ...

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Introduction to a Requirements Engineering Framework for Aeronautics

Introduction to a Requirements Engineering Framework for Aeronautics

... This activity deals with the rise of V-model. It consists in evaluating the implementation of the supplier’s require- ments to determine, whether or not, they have been met. There are several means of verification: ...

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AsmL Specification and Verification of Lamport’s Bakery Algorithm

AsmL Specification and Verification of Lamport’s Bakery Algorithm

... AsmL specification of the Bakery Al- gorithm, and whose values will represent states of the AsmL ...The specification consists of two types of agents: customer agents and reader ...

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