• No results found

high-speed chip-to chip interconnection

A Novel Low Power Optimization for On-Chip Interconnection

A Novel Low Power Optimization for On-Chip Interconnection

... A design which takes advantage of the inductance- dominated high-frequency regime of on-chip interconnects is shown capable of transmitting data at velocities near the speed of light [8]. This ...

5

A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band

A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band

... cause high-energy consumption and degradation in ...for high speed and low power interconnects, THz Wireless NoC (WiNoC) enabled with high-speed direct links between distant cores is ...

73

An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links

An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links

... In this thesis, the CDMA based channel access mechanism is adopted, using Walsh codes to create the orthogonal code-channels, thus enabling multiple access of the wireless medium. Fig.5 depicts the mm-wave CDMA based ...

52

Test the S27 Benchmark Circuit by Using Built In Self Test and Test Pattern Generation

Test the S27 Benchmark Circuit by Using Built In Self Test and Test Pattern Generation

... The hardware used in this paper for generating the primary input sequence A consists of a linear-feedback shift-register (LFSR) as a random source [17], and of a small number of gates (almost six gates are needed for ...

9

Ovarian cancer plasticity and epigenomics in the acquisition of a stem-like phenotype

Ovarian cancer plasticity and epigenomics in the acquisition of a stem-like phenotype

... and ChIP-chip ...of ChIP technology with high- throughput DNA sequencing, yielding ChIP-sequencing (ChIP-seq) technology ...

11

A DSRC Transceiver with Multi Mode
Encoder using SOLS Technique

A DSRC Transceiver with Multi Mode Encoder using SOLS Technique

... The dedicated short-range communication (DSRC) is a protocol specially designed for the intelligent transportation system, in which the communication between each and every vehicles may be one way or two way ...

6

Coupled Chip-to-Chip Interconnect Design

Coupled Chip-to-Chip Interconnect Design

... for the I/O buffer. ACCI can tolerant lower supply voltage operation and thus save this dedicated high voltage power supply. This benefit of ACCI was demonstrated in Figure 3.5. The high edge rate provided ...

147

Profiling gene promoter occupancy of Sox2 in two phenotypically distinct breast cancer cell subsets using chromatin immunoprecipitation and genome wide promoter microarrays

Profiling gene promoter occupancy of Sox2 in two phenotypically distinct breast cancer cell subsets using chromatin immunoprecipitation and genome wide promoter microarrays

... and ChIP-PCR ChIP-chip was performed based on a previously de- scribed ChIP-PCR protocol ...[31]. ChIP-PCR was performed as previously described [18]. ChIP input DNA was run on ...

13

The Reflected-Shifted-Truncated-Gamma Distribution for Negatively Skewed Survival Data with Application to Pediatric Nephrotic Syndrome

The Reflected-Shifted-Truncated-Gamma Distribution for Negatively Skewed Survival Data with Application to Pediatric Nephrotic Syndrome

... Traditional chip pins were extended and converted to micro-antennas to achieve the wireless interconnection between chips for the purpose of solving the interconnection and signal integrity issues ...

150

The Transition from the Conventional to the High-Speed Cutting Region and a Chip-Formation Analysis

The Transition from the Conventional to the High-Speed Cutting Region and a Chip-Formation Analysis

... of chip, which was produced with a cutting speed of 1500 ...No chip segmentation appears as this steel passes through the plastic deformation region, even at high cutting ...the chip; ...

10

High Speed and Pipelined Analog to Digital Converter for Multiple Processor System on Chip

High Speed and Pipelined Analog to Digital Converter for Multiple Processor System on Chip

... the high speed and high resolution analog to digital conversion using successive approximation registers (SAR) with split DAC structure based on combining three ADC architectures namely split type ...

13

Design of High Performance Master/Slave Memory Controller with AHB Architecture
Pemma Ramya & Venkata Rao Param

Design of High Performance Master/Slave Memory Controller with AHB Architecture Pemma Ramya & Venkata Rao Param

... a high- performance system backbone bus called AMBA high- performance bus (AHB) or advanced system bus (ASB), able to sustain external memory bandwidth, on which the central processing unit (CPU), ...

5

Tip60 complex binds to active Pol II promoters and a subset of enhancers and co-regulates the c-Myc network in mouse embryonic stem cells

Tip60 complex binds to active Pol II promoters and a subset of enhancers and co-regulates the c-Myc network in mouse embryonic stem cells

... Tip60 ChIP was used for Solexa sequenc- ...detect ChIP-seq peaks the MACS14 peak-calling algorithm was applied using default parameters ...Tip60 ChIP-seq data were deposited in the Gene Expression ...

16

A 64 point Fourier transform chip for high speed wireless LAN application using OFDM

A 64 point Fourier transform chip for high speed wireless LAN application using OFDM

... packet-based high-data-rate communication suitable for video transmission and mobile Internet ...a high-data-rate communication system. Apart from the high speed of opera- tion, the system ...

10

Intra Chip and Inter Chip Wireless Communication Analysis for Millimeter Wave using Miniaturized On Chip Antenna

Intra Chip and Inter Chip Wireless Communication Analysis for Millimeter Wave using Miniaturized On Chip Antenna

... Deepa N P, obtained her Bachelor’s degree in Electronics and Communication Engineering from Kuvempu University, Karnataka, India and Masters in Digital Communication Engineering from Visvesvaraya Technological ...

9

Assessing quality and completeness of human transcriptional regulatory pathways on a genome-wide scale

Assessing quality and completeness of human transcriptional regulatory pathways on a genome-wide scale

... However our approach for building gold-standards of direct mechanistic knowledge has several limitations. First of all, these are limitations inherited by the assay- ing technology. Microarrays cannot reliably detect ...

13

Process Development for an Ultra High Density Chip-on-Chip Power Module.

Process Development for an Ultra High Density Chip-on-Chip Power Module.

... cost, high density and reliable chip attachment ...for interconnection and provide more current capability with lower parasitic inductance and ...

116

End Milling of Elastomers

End Milling of Elastomers

... between Chip Characteristics and Groove Appearance The two large ...the chip does not correlate well with the appearance of the groove and the complexity of the chip formation ...

71

A Survey on High Speed and Memory Efficient Regular Expression Pattern Matching

A Survey on High Speed and Memory Efficient Regular Expression Pattern Matching

... In addition to the aforementioned acceleration approaches, DFA-based compression methods also enhance the system performance because they result in smaller DFAs that can be put into the fast memory. Transition ...

8

Evaluation of chips formation of AISI 316L 
		SS using precision end milling

Evaluation of chips formation of AISI 316L SS using precision end milling

... Different cutting speeds produced different Lamella structures; these are formed due to the alternative layers of the material during chip formation in cutting process. The structures with respect to dimension are ...

5

Show all 10000 documents...

Related subjects