• No results found

high-speed digital test

Digital Design and High Speed Signal Propagation - Advanced Black Magic

Digital Design and High Speed Signal Propagation - Advanced Black Magic

... EMC test site) (Doug Smith) This course covers techniques for finding design issues that may cause EMC compliance problems early in the design cycle, long before an official EMC ...

8

Cosine-Modulated Multitone for Very-High-Speed Digital Subscriber Lines

Cosine-Modulated Multitone for Very-High-Speed Digital Subscriber Lines

... So far, the simulated subscriber loops were homogeneous lengths of TP1 cables. Previous reports, [30], as well as our simulation studies have shown that the group delay distor- tion of such lines is very minimal and ...

16

Flexible embedded test solution for high speed analogue front end architectures

Flexible embedded test solution for high speed analogue front end architectures

... production test. Two A/D converter test methodologies are widely in use today which measure code transition levels, namely feedback loop testing [7, 8] and histogram testing ...converter test meth- ...

11

Experimental investigation of high speed digital circuit’s return current on electromagnetic emission

Experimental investigation of high speed digital circuit’s return current on electromagnetic emission

... a high speed printed circuit board (PCB). In high-speed digital circuit, the high-frequency return current signal will find its way back to the source by flowing along the path ...

5

Effective Design of an High speed Digital Fault Tolerant Architecture

Effective Design of an High speed Digital Fault Tolerant Architecture

... Here, of course the data being voted may not be exactly the same and a criterion must be used to identify and reject faulty versions and to determine a consistent value that all good versions can use. An alternative ...

5

Design an High speed Digital Fault Tolerant Architecture

Design an High speed Digital Fault Tolerant Architecture

... versions can use. An alternative dynamic approach is based on the concept of recovery blocks. Programs are partitioned into blocks and acceptance tests are executed after each block. If an acceptance test fails, a ...

7

Towards high velocity deformation characterisation of metals and composites using Digital Image Correlation

Towards high velocity deformation characterisation of metals and composites using Digital Image Correlation

... of Digital Image Correlation (DIC) to images obtained from high speed cameras provides full-field strain ...from high speed imaging of specimens of different materials loaded in a ...

8

IMPLEMENTATION AND COMPARATIVE STUDY OF A HIGH SPEED MULTIMO DE DIGITAL MODULATOR FOR POWER CONSTRAINED DIGITAL COMM UNICATION

IMPLEMENTATION AND COMPARATIVE STUDY OF A HIGH SPEED MULTIMO DE DIGITAL MODULATOR FOR POWER CONSTRAINED DIGITAL COMM UNICATION

... A prototype of the proposed architecture was developed for implementation on FPGAs. The Xilinx Virtex-5 and Spartan 3E FPGAs were selected as targets for the prototype. The architecture was described in VHDL and the code ...

8

VLSI design of high-speed adders for digital signal processing applications.

VLSI design of high-speed adders for digital signal processing applications.

... 4 .2.8 DIFFERENTIAL CASCODE VOLTAGE SWI TC H LOGIC (DCVSL) The Differential Cascode Voltage Switch Logic (DCVSL) C20] is a complete logic family because it pr ovides complementary outputs. This pr operty of having the ...

180

INTERACTING THROUGH DISCLOSING: PEER INTERACTION PATTERNS BASED ON 
SELF DISCLOSURE LEVELS VIA FACEBOOK

INTERACTING THROUGH DISCLOSING: PEER INTERACTION PATTERNS BASED ON SELF DISCLOSURE LEVELS VIA FACEBOOK

... Frequency domain is an important domain for image processing. Images can be transformed from the time domain to frequency domain using discrete Fourier transform or discrete wavelet transformation . Discrete wavelet ...

13

An experimental test on a cryogenic high-speed hydrodynamic non-contact mechanical seal

An experimental test on a cryogenic high-speed hydrodynamic non-contact mechanical seal

... From Fig. 10, the temperatures in the stable stage also change indefinitely. When the speed is in the range from 13,000 to 15,000 r/min, the temperature (T3) has three sig- nificant troughs in 24th, 58th, and 78th ...

11

High Speed and Pipelined Analog to Digital Converter for Multiple Processor System on Chip

High Speed and Pipelined Analog to Digital Converter for Multiple Processor System on Chip

... The conventional pipeline topology uses op-amps and switched capacitor structures to generate residual. Moreover, the internal flash uses comparators (n is the number of bits of the stage). All these blocks burn up ...

13

Design and Performance Analysis of Asynchronous GRO based Time to Digital Converter

Design and Performance Analysis of Asynchronous GRO based Time to Digital Converter

... point at which the stop signal and delayed start signal synchronizes. The delay that causes the two signals in phase reflects the measurement time interval. The core structure of delay-line-based TDC is shown in Fig. 4. ...

6

196307 pdf

196307 pdf

... 3- 7 In a real time digital computer solution, a high speed random access core memory functions as the high speed buffer, with magnetic tape, disk file or drum memory being used for buff[r] ...

78

OPTIMIZATION OF COMPARATOR FOR HIGH SPEED FLASH ADC

OPTIMIZATION OF COMPARATOR FOR HIGH SPEED FLASH ADC

... In high speed analog to digital converters, comparator design has a crucial influence on the overall performance that can be ...a high throughput rate impose stringent constraint on delay, ...

6

Study And  Preliminary Design Of High Speed Impact Test Machine Using Hopkinson Bar Test Principle

Study And Preliminary Design Of High Speed Impact Test Machine Using Hopkinson Bar Test Principle

... c) Kolsky an Investigation of the Mechanical Properties of Materials at Very High Rates of Loading, Proc. Phys. Soc. London (1949). adds a second bar to Hopkinson’s original apparatus and he name it as split ...

24

Low Power Analysis of Double Tail Comparator for ADC by Using Hspice
A Murali, E Mahesh & N  Vijaya Babu

Low Power Analysis of Double Tail Comparator for ADC by Using Hspice A Murali, E Mahesh & N Vijaya Babu

... and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maxi- mize speed and power ...

10

A Practical implementation of high-speed communication using digital subscriber line technology

A Practical implementation of high-speed communication using digital subscriber line technology

... VDSL data Very rates 1000 feet high bit rate Digital Subscriber Line: Modem for twisted-pair from 12.9 to 52.8 Mbps of 24 gauge twisted with but increasingly available Competitive Access[r] ...

67

High Speed Digital Oscillator Implementations Based on Advanced Arithmetic and Architecture Techniques

High Speed Digital Oscillator Implementations Based on Advanced Arithmetic and Architecture Techniques

... Pipelining is an advanced hardware technique that, in most cases, significantly improves the performance of digital arithmetic units. The cost of pipelining is usually embedded in the inter-stage buffers ...

12

Performance improvement in FIR filter using Residue Number System with modulo adders and multipliers

Performance improvement in FIR filter using Residue Number System with modulo adders and multipliers

... and high speed real-time digital filters will be necessary to find applications in radar, communications and image processing ...the speed of the system will be increased ...

6

Show all 10000 documents...

Related subjects