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high-voltage CMOS IC

CMOS-Electromechanical Systems Microsensor Resonator with High Q-Factor at Low Voltage

CMOS-Electromechanical Systems Microsensor Resonator with High Q-Factor at Low Voltage

... 3-poly-7-metal CMOS process, featuring low cost, batch production, fast turnaround time, easy prototyping, and MEMS/IC ...by CMOS back-end-of-line materials and 5) fully differential measurement ...

5

Low voltage CMOS Schmitt Trigger in 0.18 m technology

Low voltage CMOS Schmitt Trigger in 0.18 m technology

... the IC Station® Tool Suite, a complete IC design flow, from schematic capture to physical layout and ...performance, high performance, fast, and scalable interconnect models is necessary at all ...

8

Pin Out for HDJD-S722-QR999 Pin Pin Name Normal Operation

Pin Out for HDJD-S722-QR999 Pin Pin Name Normal Operation

... a high performance, small in size, cost effective light to voltage converting ...monolithic CMOS IC ...analog voltage outputs, denoted by VR OUT , VG OUT and VB OUT , ...

10

Designing a new high gain CMOS amplifier towards a 17 22 MHz MEMS based Si oscillator for a cost effective clock generator IC

Designing a new high gain CMOS amplifier towards a 17 22 MHz MEMS based Si oscillator for a cost effective clock generator IC

... The designed integrated operational ampli fi er, has three different ‘ single ended ’ ampli fi cation blocks, cascaded together. The initiating block is a high gain transimpedance ampli fi er (TIA) which tasked to ...

8

Analysis of Various Low-Voltage High Impedance Gate Driven CMOS Current Mirrors

Analysis of Various Low-Voltage High Impedance Gate Driven CMOS Current Mirrors

... In the early 1980s many experts predicted the demise of analog circuits. Many functions that had been traditionally realized in analog form were now easily implemented in the digital domain, suggesting that with enough ...

8

A Power Efficient CMOS PLC Receiver Design-Dual Use of Power Lines for Design for Testability

A Power Efficient CMOS PLC Receiver Design-Dual Use of Power Lines for Design for Testability

... an IC needs to couple the test data signals to each and every ...very high power. So, in this paper a power efficient CMOS PLC receiver for the same purpose in 180 nm CMOS technology under a ...

8

Digital MPPT Interface for PV Module

Digital MPPT Interface for PV Module

... low-voltage, high-performance CMOS 8-bit microcomputer with 2K bytes of Flash programmable and erasable read-only memory ...has high-density non-volatile memory technology and is compatible ...

6

A Low-Power, High Performance MEMS-based Switch Fabric

A Low-Power, High Performance MEMS-based Switch Fabric

... The primary concern regarding device throw that the greater the device throw, the better the “off ” state of a device can be. It is beneficial however to understand how this design parameter relates to bistability as ...

188

NP Domino, Ultra Low Voltage, High Speed, Dual Rail, CMOS NOR Gates

NP Domino, Ultra Low Voltage, High Speed, Dual Rail, CMOS NOR Gates

... become high (1) and consequently a high to low transition happens in Q ...a high to low transition will happen in the output voltage of the NOR gate (Q), and both KN1 and KN2 transistors ...

11

Design of Three Stage CMOS Comparator in 90nm Technology

Design of Three Stage CMOS Comparator in 90nm Technology

... In this paper, a three stage CMOS comparator topology for low power and high speed applications is presented. A single comparator circuit has been built and tested. The circuit is designed and simulated in ...

5

A New Low-Voltage, Low-Power and High-Slew Rate CMOS Unity-Gain Buffer

A New Low-Voltage, Low-Power and High-Slew Rate CMOS Unity-Gain Buffer

... which increases the power consumption of the circuit. In this paper a very simple, low-voltage class-AB structure is proposed which is able to take current from supply sources only when the load requires it, so ...

7

Implementation of Efficient Adder Using  Multi Value Logic Technique

Implementation of Efficient Adder Using Multi Value Logic Technique

... The digital logic circuits are restricted for the requirement of interconnections. This difficulty overcomes by using a big set of signals over the same chip area. Multiple-valued logic (MVL) designs contain more ...

5

A Linear CMOS Low Drop-Out Voltage Regulator in a 0.6μm CMOS Technology

A Linear CMOS Low Drop-Out Voltage Regulator in a 0.6μm CMOS Technology

... The gain, phase and output swing of the designed opamp were obtained using some simulations. For AC simulation a 2pF load capacitor was used. The gain and phase response of the opamp have been shown in Fig. 3. The gain ...

6

A Resistorless CMOS Non-Bandgap Voltage Reference

A Resistorless CMOS Non-Bandgap Voltage Reference

... resistorless CMOS nonbandgap voltage reference, which is compatible with 180nm CMOS Technology is presented in this ...proposed voltage reference, threshold voltage and a proportional ...

8

An Improved Low Power, High Speed CMOS Adder Design for Multiplier

An Improved Low Power, High Speed CMOS Adder Design for Multiplier

... improved CMOS full adder circuit for high speed and low power applications is proposed in this paper at 90 nm technology node with supply voltage ...

5

Power and Area Efficient FLASH ADC Design using 65nm CMOS Technology

Power and Area Efficient FLASH ADC Design using 65nm CMOS Technology

... the CMOS technology is continuously scaling down, the design of ultra-high speed wired or wireless communication system is becoming ...digital CMOS technology a challenging aspect for analog ...

8

High Voltage Impulse Voltage Test On High Voltage Insulation Glove

High Voltage Impulse Voltage Test On High Voltage Insulation Glove

... Normally, for generations of over 100kV DC voltages, electronic valve rectifiers are used and the current output is about 100mA. The rectifier valves require special cathode and filaments construction since a high ...

24

A Combined Approach of IVC and GR for Leakage Power Reduction in CMOS VLSI Digital Circuit

A Combined Approach of IVC and GR for Leakage Power Reduction in CMOS VLSI Digital Circuit

... All of the mentioned techniques require a lot of processing. There are several leakage mechanisms contributing to the OFF current of a MOS transistor in short channel devices. Out of which Sub-threshold leakage and gate ...

5

Multithreshold CMOS sleep stack and logic stack technique for digital 
		circuit design

Multithreshold CMOS sleep stack and logic stack technique for digital circuit design

... threshold CMOS sleep and logic stack technique provides a considerably less power dissipation and ...threshold voltage of the ...gate voltage to the ...

7

A 0 8 V 0 23 nW 1 5 ns full swing pass transistor XOR gate in 130 nm CMOS

A 0 8 V 0 23 nW 1 5 ns full swing pass transistor XOR gate in 130 nm CMOS

... A power efficient circuit topology is proposed to implement a low-voltage CMOS 2-input pass-transistor XOR gate. This design aims to minimize power dissipation and reduce transistor count while at the same ...

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