With this goal of flexibility in mind, the processor is designed in such a way that it can be configured to perform several useful functions. Since multiplication, subtraction and addition are three of the most commonly used **arithmetic** operations, these operations are included in the Floating Point **Arithmetic** and **Logic** **Unit**, both in **integer** and floating- point mode. Along with this, **logic** operations on integers are also included in the proposed floating point processor. This processor has separate data memory and program memory, 32 number of 32 bit register file, 32 bit A and B registers, 32 bit program counter (PC) and 32 bit instruction register (IR). For the effective implementation of the **arithmetic** operations on floating point and **integer** numbers, a residue number system (RNS) based floating point ALU is proposed for the processor. The design is coded using verilog HDL and synthesized for Xilinx virtex-4 device. The design is synthesized using Xilinx ISE tool.

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have enabled industry to reduce interconnect resistance in narrow lines and at the same time changes in interlayer dielectric (ILD) material have lowered the line to line capacitance resulting in Resistor-Capacitor (RC) delay improvement and thus interconnect power utilization, however, deep submicron technology introduces formidable integration and reliability challenges such as higher narrow Cu line resistivity, higher current density and inferior thermo-mechanical properties which must be overcome. It is well known that the binary number system is the leading choice for conventional voltage-mode design of digital systems. However, in a emblematic binary number system based VLSI circuit about 70 percent of chip area is occupied by interconnections which occupy a large portion of physical area even when it is not in use. Therefore the interconnections will be more efficient if several levels of **logic** are injected into a only wire, as in multiple valued logics. Dissimilar to binary **logic**, multiple valued logics require more than two discrete levels of **logic** signals and allow more than two logical concepts to exist in a **logic** system. Thus, the direct benefit of such logics is the improved overall information efficiency. It is because each r- valued signal can carry times more information than a binary signal does. As a result the routing area is compact on a logarithmic scale- -as r increases. As can be seen, the routing area of a 4-valued **logic** design is two times smaller than the corresponding binary **logic** system. 2 log r log r 2. The choice of the most favorable **logic** radix in term of implementation cost has been also studied by some researchers. the circuit implementation cost is decreasing with increasing **logic** radix and according to C.M. Allen and D. Given, the optimal radix is greater than Euler constant, . Since in practice the radix r is an **integer**, it comprehends that the more advantageous radix must be at least 3 or in other words ternary **logic**. On the other hand alteration with binary is most efficient if special radices are chosen in such a way that no information is lost or left unused.

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Significand and q the exponent. The exponent q is obtained as a function of biased non-negative **integer** exponent E. The mantissa is encoded in densely packed decimal [3], the exponent must be in the range [emin, emax], when biased by bias. Representations for infinity and not-a-number (NaN) are also provided. Representations of floating-point numbers in the decimal interchange formats are encoded in k bits in the following three fields (Fig1):

Applications which cannot tolerate errors generating from BFP **arithmetic**, these application use software platforms to perform DFP **arithmetic** [1]. There are many software packages which are available for example: the java BigDecimal library [5] and IBM‟s decNumber library [4]. Also Intel published results for a decimal **arithmetic** library which uses Binary **integer**

A reversible **logic** gate is said to be reversible if the number of inputs is equal to the number of outputs. In order to achieve a synthesized low power circuits, the reversible **logic** gate circuits should have the following specifications which are minimum number of reversible gate or gate count, minimum number of garbage outputs, minimum propagation delay and minimum quantum cost [11]. In the proposed ALU designs, R-I, Feynman, Fredkin and Peres reversible gates are used. The quantum implementations of the three gates are described in the following subsections.

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ALU is a data processing component, which is an important part in centre process **unit** (CPU). Different kinds of computers have different ALUs. But all of the ALUs contain **arithmetic** **unit** and **logic** **unit**, which are the basic structures. In **arithmetic** operations there are add, minus, while in logical operations there are NOT, OR, AND, XOR and so on. The above operations can be realized by using reversible **logic** gates, through which can avoid the energy consumption. In this thesis, the multi-function ALU based on reversible **logic** gates has been designed which contains the reversible control **unit** and the reversible full adder. The reversible control **unit** and the reversible full adder are cascaded and arbitrary bit reversible ALU modules can be realized by this way. Here 1bit ALU has been designed. The A and B inputs of the reversible control **unit** are altered depending on the S0, S1and S2 values and applied as input to reversible full adder using DPG gates. By controlling one of the inputs to adder, various **arithmetic** and **logic** operations can be realized. The designed circuit has three control signals with a provision for realizing eight **arithmetic** operations and four **logic** operations.

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Abstract: This project describes the techniques for fabricating a high speed ALU using pass transistor **logic**. Double pass transistor **logic** is shown to improve the circuit performance at reduced supply voltage. Using DPL technique a 16 bit ALU is designed with the help of multiplexers and full adder. In the existing method full adders and multiplexers were designed using PTL method. The main component in the ALU is full adder. In CMOS method eight transistor full adder and CMOS based multiplexers are used. By reducing area and by using DPL based multiplexers low power ALU is attained. In the implementation of ALU using DPL method, the power and area are reduced compared to PTL method. With the increase in the bit size there are a number of uses, Speed of the processor increases as it can accommodate large bit size and number of applications increases. Results are observed using Microwind and Digital Schematic.

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Abstract - In this project we are designing a 8 bit **arithmetic** and logical **unit** with the help of reversible **logic**. This ALU consists of 10 operations, 4 logical and 6 **arithmetic** operations. The logical operation include and, or, ex-or and ex-nor. The **arithmetic** operation performed by this gate includes set, clear, increment, 1’s complement, 2’s complement and transfer of input. Reversible **logic** is gaining interest in the recent years due to its less power consuming and less heat dissipating characteristics. Unlike the irreversible gates that dissipates energy, the reversible computation reduce heat dissipation. The loss of information is associated with loss in physics is requiring that one bit information lost dissipates “KT ln2 of energy”. In order to overcome the loss of information we go for reversible computation. The parameters that define an optimum reversible **logic** based ALU are low quantum cost, reduced garbage outputs and minimum number of reversible gates used. Based on the above constraints of the reversible **logic** we have designed a ALU with single reversible **logic** gate namely RC-1 gate. This design is developed using Xilinx 13.4suite, verilog software. It is designed so as to perform 8 bit inputs for both logical and **arithmetic** operations.

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Using conventional gates like AND& OR gates the digital system is implemented which dissipates a major amount of energy in the form of bits which gets erased during logical operation.by using reversible **logic** circuits in place of conventional **logic** circuits the problem of energy loss can be solved in digital circuit designing the reversibility has become the most promising technology. In today’s world ALU is one of the very important of any system having many applications in computers, cell phones, calculators etc.In this paper the design of one bit reversible ALU using reversible **logic** gate is proposed. The proposed ALU is analysed on FPGA SPARTAN6 device. The proposed design is compared in terms of propagation delay, quantum cost and garbage outputs. In this paper the 4-bit reversible ALU is also design on proposed 1- bit reversible ALU architecture.

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We can conclude that the fundamentals of reversible computing are based on the relationship entropy, heat transfer between molecules in a system, the prospect of a quantum particle occupying a particular state at any given time, and the quantum electrodynamics between electrons when they are in close proximity.. In future we can have some other combination of reversible **logic** gates that is MRG and HNG gates that provides more **arithmetic** and logical operations and hence delay can be reduced to some more extent. Apart from that if the delay reduces power also is reduced.

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Chetan Kumar et.al. [4] Present paper “Implementation of 16 bit **Arithmetic** **Logic** **Unit** using Toffoli Reversible **logic** gate (2014)” in International Journal of Innovative Science, Engineering & Technology (JISET). In this paper a traditional ALU is realized using AND, OR reversible **logic** gates. The power dissipation in terms of loss of information bits is reduced significantly when **logic** gates were replaced by reversible gates. The proposed reversible 16-bit ALU reduces the loss of power reusing the bits. Simulation of these circuits is done by Mentor graphics tools and language used for programming is very high speed hardware integrated circuit hardware descriptive language, Verilog. This ALU is made up of Toffoli Gate only and observed low power consumption on simulation.

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circuits. CMOS technology is used in microcontroller, microprocessor, static RAM and other digital **logic** circuits. CMOS technology is also used for several analog circuits such as image sensors (CMOS sensors), data converters, and highly integrated transceivers for many types of communication. Two CMOS is also sometimes referred to as complementary-symmetry metal– oxide–semiconductor (or COS-MOS). The words "complementary-symmetry" refer to the fact that the typical digital design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide field effect transistors (MOSFETs) for **logic** functions. Important characteristics of CMOS devices are high noise immunity and low static power consumption. CMOS circuits are constructed in such a way that all PMOS transistors should have either an input from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors should have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor provides low resistance between its source and drain contacts when a low gate voltage is applied and high resistance when a high gate voltage is applied. But on the other hand, the composition of an NMOS transistor provides high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied. CMOS achieves current reduction by complementing every NMOSFET with a PMOSFET and connecting both gates and both drains together. A high voltage on the gates will result to the condition that NMOSFET will conduct and the PMOSFET will not conduct while a low voltage on the gates causes the reverse. This technique greatly reduces power consumption and heat production. However, during the switching time both MOSFETs conduct briefly as the gate voltage goes from one state to another. GDI resembles standard CMOS inverter cell with the only difference is that CMOS inverter has only one input and two supply voltages VDD and VSS. But GDI cell can have three inputs G (common gate input of NMOS and PMOS), VDD supply is replaced by P (input to the source/drain of PMOS), VSS supply is replaced by N (input to the source/drain of NMOS).

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In this paper, we investigate the infinitary analogues of such familiar number theoretic functions as the divisor sum function, Euler’s phi function and the Mbbius function... KEY WORDS [r]

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The Arm processor has large uniform register file, load/store architecture, where data-processing operations only operate on register contents, not directly on memory contents. Simple addressing modes, with all load/store addresses being determined from register contents and instruction fields only Uniform and fixed-length instruction fields to simplify instruction decode [5]. The ARM processor has been specifically designed to be small to reduce power consumption and extend battery operation.The ARM architecture gives Control over both **Arithmetic** **Logic** **Unit** (ALU) and shifter in every data-processing instruction to maximize the use of an ALU and a shifter Load and Store multiple to maximize data throughput. These enhancements to a basic RISC architecture allow ARM processors to achieve a good balance of high performance, small code size and low power consumption. [4] The FPGA based design reduces time to market & adds design flexibility and adaptability with optimal device utilization and conserving both less board space and system power, which is often not the possible in every case of ASIC chips. [3] In following this line of thought, this paper summarizes our recent progress in developing VHDL soft-core of ARM processor on Xilinx’s Spartan III based FPGA. An advantage of implementing a full-featured ARM processor soft-core on FPGA is complete hardware customization while implementing various applications.

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III. GATE DIFUSSION INPUT TECHNIQUE Morgenshtein has proposed basic GDI cell shown in Fig.1 [8]. This is a new approach for designing low power digital combinational circuit.GDI technique is basically two transistor implementation of complex **logic** functions which provides in-cell swing restoration under certain operating condition. This approach leads to reduction in power consumption, propagation delay and area of digital circuits is obtained while having low complexity of **logic** design. An important feature of GDI cell is that the source of the PMOS in a GDI cell is not connected to VDD and the source of the NMOS is not connected to GND.

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A’C2+AC3 is given as the input to RG1 with the additional input of 0. The obtained output fromRG1 is A’BC2+ABC3 with the two garbage outputs. At the next stage the outputs from RG3 and RG1A’B’C2+AB’C1 and A’BC2+ABC3 respectively given asthe input to RG4 gate with an additional constant input of0.The additional output from the RG4 includes additional two garbage’s. Hence the total reversible gate required to design the logical **unit** will be 9. The total garbage outputs obtained is 14. The number of constant inputs employed in the logical **unit** design is 2 as the constant inputs are getting propagated to the various reversible gates in the circuitry. C0, C1, C2, C3 are the control inputs in the design corresponding to the control inputs the logical functions can be preceded. The control inputs should be increased to perform more logical operations. For example, for the control input combination 0001, from the gates RG3, RG2, RG1 only the garbage values will be generated. From the gate RG4 the output will beAC3, this output is further given

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Reconfigurable systems offer a solution to solve complex problems by combining the speed of hardware with the flexibility of software to improve performance and system performance. Past three decades have seen the introduction of the technology that has radically changed the way one analyses and controls the world around them. Exploiting computational precision can improve performance significantly without losing accuracy in many applications. To enable this, we propose an innovative **arithmetic** **logic** **unit** (ALU) architecture that supports true dynamic precision operations on the fly. As the operations become more complex the ALU also become more complex, more expensive and takes up more space in the CPU hence power consumption is a major issue. The VHDL coded synthesizable RTL code of the Fixed Point **Arithmetic** core has a complexity. We verified the functions of the Fixed Point **Arithmetic** by a simulation with a single instruction test as the first step and then implemented the Fixed Point **Arithmetic** with the FPGA. Nowadays to handle the more challenges and complex task the demand of improving ability of a processor is increasing day by day which resulted in the more numbers of components fabricated on a single chip according to the Moore Law.

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As FPGA has an application that it can incorporates much **logic** on a single FPGA. So as floating point ALU has many operations to be performed in the computer we are using an FPGA IC to implement it. The operations performed by the FPU are addition, subtraction, multiplication, division and logical operations as AND, OR, NOT etc. FPU mainly work on Real as well as integers value.FPGA is an integrated circuit designed to be configured by the customers or designer after manufacturing- hence “Field Programmable”. The FPGA configuration is generally specified using a hardware description language, similar to that used for an application specific integrated circuit (ASIC).

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perform 16 operations which include both logical and **arithmetic** operations. Data retention and leakage current are among the major area of concern in today’s CMOS technology. In the paper [9] 6T SRAM cell has been analyzed on the basis of read noise margin (RNM), write noise margin (WNM), read delay, write delay, and data retention voltage (DRV). Implementation and simulations are carried out using VHDL. Paper [10] discusses the FPGA implementation about DDR3 SDRAM controller for high performance. Work by Vikas Gupta et. al. [11] explains a method for designing and implementing multiplierless digital PID controller based on Field Programmable Gate Array (FPGA) device. Paper [12] explains design of full architecture of an embedded processor for realizing **arithmetic**, logical, shifting and branching operations.

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