This work describes electroplating as a robust material deposition technique with wide applications ranging from surface protection to large-areaelectronics and nano-technology while focusing on semiconductor deposition. The manuscript also reviews the pros and cons of electroplating techniques. The effect of growth parameters such as temperature, pH, stirring rate, precursor, solvent and cathodic voltage, and post-growth heat treatments of the deposited were iterated. The capability of electroplated material to be comparable and possibly superior to semiconductor materials grown using other cash intensive techniques are also highlighted with experimental evidence. Electroplated materials can be applicable in large-area devices such as photovoltaic solar panels and large-area display panels in which intricate shapes are required. Bandgap grading, alteration of elemental composition, and different conductivity type are also possible intrinsically with a change in the cathodic voltage. Other advantages such as columnar growth of nanorods which are tightly packed and normal to the substrate could trigger many new applications in the nanotechnology area.
more suitable CdS layers required to give the highest performing devices. This can only be achieved by comprehensive experimental work on growth and characterisation of CdS layers from the above mentioned sulphur sources. This paper presents the results observed on CdS layers grown by electrodepositing using two electrode configuration and thiourea as the sulphur precursor. X-ray diffraction (XRD), Raman spectroscopy, optical absorption, scanning electron microscopy (SEM), energy-dispersive X-ray analysis (EDX) and photoelectrochemical (PEC) cell methods have been used to characterise the material properties. In order to test and study the electronic device quality of the layers, ohmic and rectifying contacts were fabricated on the electroplated layers. Schottky barriers, formed on the layers were also compared with previously reported work on Chemical Bath Deposited CBD-CdS layers and bulk single crystals of CdS. Comparatively, Schottky diodes fabricated on electroplated CdS layers using two-electrode system and thiourea precursor exhibit excellent electronic properties suitable for electronic devices such as thin film solar panels and largearea display devices.
For high quality solar cell applications, materials with high optical absorption, high carrier mobility and low fabrication cost are demanded. Crystalline silicon (C-Si), the most popular electronic material, has an indirect bandgap and, hence, poor optical absorption. On the other hand, hydrogenated amorphous silicon (a-Si:H) has high optical absorption, but it suffers from low carrier mobility, photo-induced degradation also named Stabler- Wronski effect [1,2] and, hence, poor optoelectronic properties. Recently, thin film hydrogenated nanocry- stalline silicon (nc-Si:H) deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD) emerged as a ma- terial for large-areaelectronics applications [3-6]. The fabrication cost for nc-Si:H optoelectronic applications is expected to be low, since thin films of nc-Si:H can be deposited directly over large-area substrates using the same fabrication facilities well established for a-Si:H devices. Plasma deposited hydrogenated nanocrystalline silicon (nc-Si:H) offers the possibilities of high carrier
mostrato in Fig. 4) che ci permettono di volta in volta di conﬁ gurare le caratteristiche della nostra CPU e delle periferiche ad essa associa- te. È possibile abilitare, ad esempio, la cache del processore o la generazione della FPU; possiamo aggiungere al nostro SoC ﬁ no a due porte di comunicazione UART, un controller ethernet o una porta SPI per l’accesso alla memoria ﬂ ash seriale presente sulla scheda di sviluppo. Nel caso del nostro semplice esempio, basterà in realtà lasciare inalterate le selezioni predeﬁ nite che ci vengono proposte. Dopo un po’, dovremmo ﬁ nalmente ritro- varci all’interno dell’ambiente XPS (Xilinx Platform Studio) come mostrato nella Fig. 5, con il nostro progetto correttamente creato e conﬁ gurato. Nell’area System Assemby View, sulla destra del pannello, appare la lista dei moduli e delle periferiche che sono presenti nel nostro SoC; l’area immediatamente alla sua sinistra, indicata come Connectivity Panel, mostra invece i bus di connessione che sono stati previsti. Si noti, ad esempio, la connessio- ne delle porte UART indicate come RS232DCE ed RS232DTE al bus PLB del processore. Cliccando sulla tab Addresses della System Assemby View, il contenuto cambia; viene mostrato lo spazio di indirizzamento associa- to ad ogni periferica. Nella Project Informa- tion Area presente sulla sinistra del pannello di XPS, sono invece riportate le informazioni di progetto. Cliccando ad esempio sulla tab IP catalog, comparirà la lista di tutti i core IP
E-government describes the use of technologies to facilitate the operation of government and the dispersement of government information and services. E-government, short for electronic government, deals heavily with Internet and non-internet applications to aid in governments. E-government includes the use of electronics in government as large-scale as the use of telephones and fax machines, as well as surveillance systems, tracking systems such as RFID tags, and even the use of television and radios to provide government- related information and services to the citizens.
This paper focuses on modeling the characteristics of four 5-MW PMSG-based WTGs fed to an SG-based power system to examine the effect of large power penetration to the SG. For improving the damping of the SG of the OMIB system, a STATCOM joined with the designed PID controller connected to the common ac bus of the studied system is proposed.
ne anche di un connettore ethernet che consente di connettere l’LPC1768 alla rete LAN (Local Area Network) e WAN (Wide Area Network); perciò vi proponiamo un semplice esempio di utilizzo della libreria ETHERNET che permette di determinare l’ora esatta tramite un server NTP (Net- work Time Protocol) qualora abbiate con- nesso il vostro mbed alla rete INTERNET e vogliate sfruttare l’altissima precisione fornita dagli orologi atomici (il codice è illustrato nel Listato 3). Per i nostri test ci siamo serviti del primo dei due server NTP primari installati nel Laboratorio di Tempo e Frequenza Campione dell’IN- RIM, accessibili liberamente. Ulteriori informazioni sono disponibili alla pagina http://www.inrim.it/ntp/index_i.shtml. La libreria ed il relativo codice sono disponibili nella pagina http://mbed.org/users/donatien/ code/NTPClient_HelloWorld/.
The network is now ready to be analyzed. To expedite the process, click on Analy- sis and choose Probe Setup. By selecting Do not auto-run Probe you save inter- mediary steps that are inappropriate for this analysis; it is an option that will be dis- cussed later in this chapter. After OK, go to Analysis and choose Simulation. If the network was installed properly, a PSpiceAD dialog box will appear and reveal that the bias (dc) points have been calculated. If we now exit the box by clicking on the small x in the top right corner, you will obtain the results appearing in Fig. 2.126. Note that the program has automatically provided four dc voltages of the network (in addition to the VIEWPOINT voltages). This occurred because an option under analysis was enabled. For future analysis we will want control over what is displayed so follow the path through Analysis-Display Results on Schematic and slide over to the adjoining Enable box. Clicking the Enable box will remove the check, and the dc voltages will not automatically appear. They will only appear where VIEW- POINTS have been inserted. A more direct path toward controlling the appearance of the dc voltages is to use the icon on the menu bar with the large capital V. By click- ing it on and off, you can control whether the dc levels of the network will appear. The icon with the large capital I will permit all the dc currents of the network to be shown if desired. For practice, click it on and off and note the effect on the schematic. If you want to remove selected dc voltages on the schematic, simply click the nodal voltage of interest, then click the icon with the smaller capital V in the same group- ing. Clicking it once will remove the selected dc voltage. The same can be done for selected currents with the remaining icon of the group. For the future, it should be noted that an analysis can also be initiated by simply clicking the Simulation icon having the yellow background and the two waveforms (square wave