Low power digital circuit design
MODIFIED GDI TECHNIQUE - A POWER EFFICIENT METHOD FOR DIGITAL CIRCUIT DESIGN
22
Advanced Low Power CMOS Design to Reduce Power Consumption in CMOS Circuit for VLSI Design
10
Performance Analysis of CMOS and GDI Comparators
5
Subthreshold Circuit Design Techniques for Ultra Low-Power Applications
7
Ultra-Low Power Design of Digital CMOS Logic Circuits
5
A Review on Design and Analysis of Low Power PLL for Digital Applications
8
Minimization Leakage Current of Full Adder Using Deep Sub-Micron CMOS Technique
7
Design of Digital Circuit for Low Power Communication Centric RF Transceiver in Wireless Sensor Node using VHDL
10
Circuit Design of Low area 8 bit magnitude Comparator With Low Power by Static CMOS
5
Design of a Low Power Adiabatic Logic Circuit Based on FinFET
5
Low-Power High Speed 1-bit Full Adder Circuit Design
6
BASICS OF ENERGY-EFFICIENT DIGITAL DESIGN
9
Variation of Power and Delay in Digital CMOS Circuit Design in DSM Technology
5
An Efficient Adiabatic CMOS Circuit Design Approach for Low Power Applications
7
Investigation of Low Power Sample and Hold Circuit for Analog to Digital Converter
7
Implementation on Low Power Design Using Comparator for VLSI Design Circuit
5
A Novel Design of Hybrid 2 Bit Magnitude Comparator
6
A study on ultra low power and large scale design of digital circuit for wireless communications
35
Design and Comparative Analysis of EEAL Sequential Circuit for Low Power VLSI Application
5
Design of Low Power CMOS Based PTAT/R Circuit for TDC (Temperature-to-Digital Converter) Applications
9