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Low power digital circuit design

MODIFIED GDI TECHNIQUE - A POWER EFFICIENT METHOD FOR DIGITAL CIRCUIT DESIGN

MODIFIED GDI TECHNIQUE - A POWER EFFICIENT METHOD FOR DIGITAL CIRCUIT DESIGN

... more power-efficient than Gate Diffusion Input logic (GDI) and complementary CMOS logic ...(Mod-GDI) circuit realizations and a wider range of different logic cells, as well as the use of practical ...

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Advanced Low Power CMOS Design to Reduce Power Consumption in CMOS Circuit for VLSI Design

Advanced Low Power CMOS Design to Reduce Power Consumption in CMOS Circuit for VLSI Design

... Abstract: Low power has emerged as a principal theme in today's electronic ...of power consumption makes a device more reliable and ...of power consumption was a major driving force behind the ...

10

Performance Analysis of CMOS and GDI Comparators

Performance Analysis of CMOS and GDI Comparators

... of power dissipation comes into ...area, power consumption and switching ...in Digital Signal Processing ...technique digital circuit ...

5

Subthreshold Circuit Design Techniques for Ultra Low-Power Applications

Subthreshold Circuit Design Techniques for Ultra Low-Power Applications

... performance digital circuits which has less area and negligible static power ...complex digital systems CMOS technology has been continuously scaled down which lead to some adverse secondary effects ...

7

Ultra-Low Power Design of Digital CMOS Logic Circuits

Ultra-Low Power Design of Digital CMOS Logic Circuits

... the power supply voltage( vdd) is less than the transistor threshold voltage (Vt), this ensures that all the transistors are operating in subthreshold ...analog design, where this characteristic is used ...

5

A Review on Design and Analysis of Low Power PLL for Digital Applications

A Review on Design and Analysis of Low Power PLL for Digital Applications

... fully-integrated low power PLL on 180nm CMOS process. Nearly 24mW power has consumed, with output frequency of ...control circuit of VCO and modulus frequency ...having low power ...

8

Minimization Leakage Current of Full Adder
Using Deep Sub-Micron CMOS Technique

Minimization Leakage Current of Full Adder Using Deep Sub-Micron CMOS Technique

... of low power ICs for digital Circuits, use in like palmtop computers, cellular mobile, etc design choices which take into consideration low power features along with other ...

7

Design of Digital Circuit for Low Power
Communication Centric RF Transceiver in
Wireless Sensor Node using VHDL

Design of Digital Circuit for Low Power Communication Centric RF Transceiver in Wireless Sensor Node using VHDL

... less power without affecting the functionality like speed, range and standard ...The power breakdown of wireless sensor node shows that the hungriest part is RF transceiver ...total power consumed by ...

10

Circuit Design of Low area 8 bit magnitude Comparator With Low Power by Static CMOS

Circuit Design of Low area 8 bit magnitude Comparator With Low Power by Static CMOS

... new low power, low area solution for designers at transistor ...can design the circuits based on finding equivalent Boolean expressions and then converting that Boolean expressions to a ...

5

Design of a Low Power Adiabatic Logic Circuit Based on FinFET

Design of a Low Power Adiabatic Logic Circuit Based on FinFET

... increasing power has become the primary barrie r against further develop ment of VLSI (Very large scale integration) circu it ...devices power dissipation is becoming a major concern. For dig ital IC’s ...

5

Low-Power High Speed 1-bit Full Adder Circuit Design

Low-Power High Speed 1-bit Full Adder Circuit Design

... and digital signal processors depend largely upon the efficient implementation of arithmetic circuits in executing the dedicated algorithms such as correlation, convolution and digital ...in power ...

6

BASICS OF ENERGY-EFFICIENT DIGITAL DESIGN

BASICS OF ENERGY-EFFICIENT DIGITAL DESIGN

... in power being the major concern for digital system ...and power no longer scale proportionally leading to increasing power ...less power dissipation. The less the power ...

9

Variation of Power and Delay in Digital CMOS Circuit Design in DSM Technology

Variation of Power and Delay in Digital CMOS Circuit Design in DSM Technology

... this power densities and total power are rapidly increasing. Design of low power circuits has become important in a variety of ...reducing power consumption involves a tradeoff ...

5

An Efficient Adiabatic CMOS Circuit Design Approach for Low Power Applications

An Efficient Adiabatic CMOS Circuit Design Approach for Low Power Applications

... VLSI circuit design is an attractive method in designing low power dissipating digital ...the design of low power high speed CMOS cell ...Analog Design ...

7

Investigation of Low Power Sample and Hold Circuit for Analog to Digital Converter

Investigation of Low Power Sample and Hold Circuit for Analog to Digital Converter

... S/H circuit depends mainly on the on-resistance of the sampling switch which will affect the ...S/H circuit keeps the gate-source voltage of the sampling transistor fixed at the supply ...modified ...

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Implementation on Low Power Design Using Comparator for VLSI Design Circuit

Implementation on Low Power Design Using Comparator for VLSI Design Circuit

... about low power is used to produce ...to digital converter) is used to convert comparator for low power using and producing desired ...

5

A Novel Design of Hybrid 2 Bit Magnitude Comparator

A Novel Design of Hybrid 2 Bit Magnitude Comparator

... comparator circuit is designed using different logic styles such as GDI, PTL, CMOS and ...the power analysis of the circuits have been ...efficient design with minimum power ...hybrid ...

6

A study on ultra low power and large scale design of digital circuit for wireless communications

A study on ultra low power and large scale design of digital circuit for wireless communications

... In the proposed method, each CMOS logic cell operating in the subthreshold region in circuit delays and power dissipation are analyzed and scaled factors are obtained by mapping from typ[r] ...

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Design and Comparative Analysis of EEAL Sequential Circuit for Low Power VLSI Application

Design and Comparative Analysis of EEAL Sequential Circuit for Low Power VLSI Application

... give low power dissipation at low frequencies ...proposed circuit with other traditional methodologies has proved that power consumption with the proposed logic is for less as compared ...

5

Design of Low Power CMOS Based PTAT/R Circuit for TDC (Temperature-to-Digital Converter) Applications

Design of Low Power CMOS Based PTAT/R Circuit for TDC (Temperature-to-Digital Converter) Applications

... a low power CMOS based PTAT/R circuit design for TDC (Temperature-to-Digital Converter) ...reference) circuit is a temperature independent voltage reference circuit ...

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