Massively parallel processing with CUDA

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Massively parallel non-stationary EEG data processing on GPGPU platforms with Morlet continuous wavelet transform

Massively parallel non-stationary EEG data processing on GPGPU platforms with Morlet continuous wavelet transform

Recent research has focused on using many-core platform such as GPU to improve wavelet transform, and nearly all works along this direction are targeted at DWT. For instance, Wong et al implement a two-dimension DWT with Cg and OpenGL on a GeForce GTX 7800 [31]. Similarly, in [28] authors also explore the implementation of a fast 2D-DWT with Filter Bank Scheme (FBS) and Lifting Scheme (LS) using Cg on the same GPU. With NVIDIA’s CUDA library [6], people have implemented 2D-DWT variants [10,18] and a 3D-DWT on GPUs [11]. In contrast to these methods, we aimed to significantly promote a CWT approach with the latest GPGPU technologies to better cater for the needs of processing massive non-stationary EEG data.
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Airborne radar clutter simulation using GPU
(CUDA)

Airborne radar clutter simulation using GPU (CUDA)

A graphics processing unit (GPU) offers a very impressive architecture for scientific computing on a single chip.GPU is a specialized electronic circuit designed to rapidly manipulate and alter memory to accelerate the creation of images in a frame buffer intended for output to a display. GPU’s are more effective than general-purpose CPUs for algorithms [3]. GPU has evolved into a highly parallel, multithreaded, many core processor and very high memory bandwidth. The most commonly used accelerator is the graphics processing unit (GPU) because of its low cost and massively parallel performance. The two most common programming environments for GPU accelerators are CUDA and OpenCL. Modern GPUs are very efficient at manipulating computer graphics, and their highly parallel structure makes them more effective than general-purpose CPUs for algorithms where processing of large blocks of data is done in parallel.
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An MPI-CUDA Implementation for Massively Parallel Incompressible Flow Computations on Multi-GPU Clusters

An MPI-CUDA Implementation for Massively Parallel Incompressible Flow Computations on Multi-GPU Clusters

Modern graphics processing units (GPUs) with many-core architectures have emerged as general-purpose parallel computing platforms that can accelerate simulation science applications tremendously. While multi- GPU workstations with several TeraFLOPS of peak computing power are available to accelerate computa- tional problems, larger problems require even more resources. Conventional clusters of central processing units (CPU) are now being augmented with multiple GPUs in each compute-node to tackle large problems. The heterogeneous architecture of a multi-GPU cluster with a deep memory hierarchy creates unique chal- lenges in developing scalable and efficient simulation codes. In this study, we pursue mixed MPI-CUDA im- plementations and investigate three strategies to probe the efficiency and scalability of incompressible flow computations on the Lincoln Tesla cluster at the National Center for Supercomputing Applications (NCSA). We exploit some of the advanced features of MPI and CUDA programming to overlap both GPU data transfer and MPI communications with computations on the GPU. We sustain approximately 2.4 TeraFLOPS on the 64 nodes of the NCSA Lincoln Tesla cluster using 128 GPUs with a total of 30,720 processing elements. Our results demonstrate that multi-GPU clusters can substantially accelerate computational fluid dynamics (CFD) simulations.
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Interactive parallel fluid solver using the Lattice-Boltzmann method and CUDA

Interactive parallel fluid solver using the Lattice-Boltzmann method and CUDA

One big advantage of the Particle Methods is the inherent parallelism. This is due that in most cases each particle or packet of particles can be computed inde- pendently. This makes convenient the use of massively parallel architectures such as Graphic Processing Units (GPUs) to implement these numerical methods. The speed–up achieved but such architectures can be impressive in most application as shown in the Figure 1.4. The figure shows how the raw power of GPUs has helped to get dramatical improvements in performance, but it also shows how the efficiency, has been dropping which means that hardware architectures are not been exploited to their fullest.
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Bayesian Word Alignment for Massively Parallel Texts

Bayesian Word Alignment for Massively Parallel Texts

Massively parallel texts, in the sense used by Cysouw and W¨alchli (2007), are essentially the same as bitexts, only with hundreds or thousands of languages rather than just two. Parallel corpora used in SMT, for instance the Europarl Corpus (Koehn, 2005), tend to contain few (up to tens of) languages, but many (up to billions of) words in each language. Massively parallel corpora, on the other hand, contain many (hundreds of) languages, but usually fewer (less than a million) words in each language.

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APPLICATIONS OF LINUX-BASED QT-CUDA PARALLEL ARCHITECTURE

APPLICATIONS OF LINUX-BASED QT-CUDA PARALLEL ARCHITECTURE

B. GPU Parallel Principle [4]. In 1999, NIVDIA released the first GPU graphic processors, GPU hardware maintains a rapid development by now, GPU performance can double every year, much higher than CPU (Central Processing Unit), which follows Moore's Law of every 18 to 24 months to double the performance. However, the GPU parallel computing can not be carried out until the official release of CUDA by NIVDIA in 2008. GPU-based parallel techniques can be simply described as following: CPU does data preparation, and executes serial initialization code; GPU carries out parallel computing. GPU-based graphic processor directly connects to CPU by AGP or PCI-E bus, which owns independent high-speed memory and lightweight threads. GPU can achieve zero-overhead fast thread switching. At present, NIVDIA's GPU contains more than 1 to 30 SMs (Stream Processors), which is equivalent to 1 to 30 CPUs. Each SM has eight SIMDs (Single Instruction Multiple Data), which is equivalent to 8 CPUs cores. And a SIMD has a thread block of up to 512 threads. Therefore, the performance of GPU can be 10 times faster than performance of CPU at the same period. Besides, a host (computer) can install multiple GPU graphic cards; therefore, the performance of GPU parallel computing on PC can reach high performance of the cluster computing. CUDA parallel programming model is shown in Figure 1[1], which comes from the NVIDIA CUDA programming guide. In Figure 1, CPU is on behalf of Host executes Serial Code (serial code program); Device is on behalf of GPU executes parallel kernel functions (parallel kernel code); Grid is on behalf of abstract stream processors grid and Block is on behalf of an abstract grid of threads.
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Accuracy and quality of massively parallel DNA pyrosequencing

Accuracy and quality of massively parallel DNA pyrosequencing

falls below a threshold length. The software identifies as ambiguous flow cycles in which no flowgram value was greater than 0.5. If 5% or more of the flow cycles for a read are ambiguous, the read is removed. The assembly of many overlapping pyrosequencing reads can produce highly accurate consensus sequences [3,4]. Wicker et al. [5] compared assemblies of the barley genome produced by reads from GS20 pyrosequencing and from ABI dideoxy sequencing. Both methods produced consensus sequences with error rates of approximately 0.07% at each consensus position. Gharizadeh et al. [6] compared pyrosequences with Sanger dideoxy methods for 4,747 templates. Comparisons of the traditional capillary sequences with the 25-30 nucleotide pyrosequence reads demonstrated similar levels of read accu- racy. Assemblies of massively parallel pyrosequencing reads of plastid genomes from Nandina and Platanus exhibited overall error rates of 0.043% and 0.031%, respectively, in the consensus sequence [4]. The generation of consensus sequences to improve accuracy, however, is generally not appropriate for studies that seek information about natural variation from every read. For example, in metagenomic [7] or PCR amplicon [8] libraries from environmental DNA sam-
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Lightweight Massively Parallel Suffix Array Construction

Lightweight Massively Parallel Suffix Array Construction

In this thesis, we design and implement a lightweight massively parallel SACA on the GPU using the prefix-doubling technique. Our prefix-doubling implementa- tion is memory-efficient and can successfully construct the suffix array for input strings as large as 640 megabytes (MB) on Tesla P100 GPU. On large datasets, our implementation achieves a speedup of 7-16x over the fastest, highly opti- mized, OpenMP-accelerated suffix array constructor, libdivsufsort, that leverages the CPU shared memory parallelism. The performance of our algorithm relies on several high-performance parallel primitives such as radix sort, conditional filtering, inclusive prefix sum, random memory scattering, and segmented sort. We evaluate the performance of our implementation over a variety of real-world datasets with respect to its runtime, throughput, memory usage, and scalability. We compare our results against libdivsufsort that we run on a Haswell compute node equipped with 24 cores. Our GPU SACA is simple and compact, consisting of less than 300 lines of readable and effective source code. Additionally, we de- sign and implement a fast and lightweight algorithm for checking the correctness of the suffix array.
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Data Dissemination and Parallel Processing Techniques Research Based on Massively Parallel Processing

Data Dissemination and Parallel Processing Techniques Research Based on Massively Parallel Processing

As a primary distributed memory model, MPP technology has multiple nodes, more processors into a system memory. Due to the non-shared memory and hardware problems, MPP can achieve a large-scale CPU connection, but it is precisely because no shared characteristics, making the data consistency there is a certain degree of difficulty. This paper proposes a distributed MPP data distribution and parallel processing technology based on relational SQL query resolution. The goal is to maintain the consistency of distributed data and improve query speed. First, in the SQL query resolution part, in accordance with the syntax analysis, semantic analysis and statement parsing and other steps in the order; in the data distribution phase using the work distribution node / data node form, issued from the work distribution node, all tasks need to be processed The results are returned to the node; in parallel processing, each node needs to store a copy of the query table, and execute SQL statements concurrently on each node for each query statement. The experimental results show that the proposed MPP data distribution and parallel processing scheme can support large amount of data processing, and improve the query processing speed under the premise of ensuring data consistency. The next step is to investigate how to further improve the efficiency of query and result merging in parallel processing.
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A Review on Image Compression in Parallel using CUDA

A Review on Image Compression in Parallel using CUDA

Abstract:- Now a days images are prodigiously and sizably voluminous in size. So, this size is not facilely fits in applications. For that image compression is require. Image Compression algorithms are more resource conserving. It takes more time to consummate the task of compression. Utilizing Parallel implementation of the compression algorithm this quandary can be overcome. CUDA (Compute Unified Device Architecture) Provides parallel execution for algorithm utilizing the multi-threading. CUDA is NVIDIA`s parallel computing platform. CUDA uses GPU (Graphical Processing Unit) for the parallel execution. GPU have the number of the cores for parallel execution support. Image compression can additionally implemented in parallel utilizing CUDA. There are number of algorithms for image compression. Among them DWT (Discrete Wavelet Transform) is best suited for parallel implementation due to its more mathematical calculation and good compression result compare to other methods. In this paper included different parallel techniques for image compression. With the actualizing this image compression algorithm over the GPU utilizing CUDA it will perform the operations in parallel. In this way, vast diminish in processing time is conceivable. Furthermore it is conceivable to enhance the execution of image compression algorithms.
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Fast parallel volume visualization on CUDA technology

Fast parallel volume visualization on CUDA technology

unsupervised strategy performs brain MRI segmentation with no prior knowledge or information. The supervised methods are listed to include Bayes classifiers with labeled maximum likelihood estimators, the k-nearest neighbour rule (kNN) and artificial neural networks (ANN) while the unsupervised methods include Bayes classifiers with unlabelled maximum likelihood estimators or the fuzzy C-means (FCM) algorithms. Though segmentation is usually performed at the pre-processing stage of volume visualization, being a key and a large research area, some studies separated the usual pre-processing stages distinctly from segmentation. Clarke et al. (1995) reviewed both pre-processing and segmentation methods of soft brain tissue. In the same vein, Styner et al. (2008) reviewed semi-automated and automated multiple sclerosis (MS) lesion segmentation approaches, analyzing MS lesions, pre-processing steps and segmentation approaches. More recently, Lladó et al. (2012) presented a review of brain MRI with the goal of helping diagnosis and follow-up of multiple sclerosis lesions in brain MRI. In order to enhance the visual appearance of the brain MRI images, any possible artefacts will need to be removed. Removal of the contained artefacts could be done at this stage, done partly or delayed until the final entry point of the dataset into volume visualization phase, this depends on the design of the volume visualization framework. Whichever of the approach being adopted in the framework design, there must be adequate provision set aside in case of unexpected introduction of certain level of artefacts during the pre-processing phase.
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GPU-Based Data Processing for 2-D Microwave Imaging on MAST

GPU-Based Data Processing for 2-D Microwave Imaging on MAST

The raw data is stored in binary files where the frequency channels are multiplexed in time. The read bin raw gpu.cu function reads in the data. The different frequency com- ponents are demultiplexed by looping over each frequency channel, nf, and sweep, nSweeps, reading nInt*nAnt points from the two data files (one for channels 0-7, one for channels 8- 15) and placing it in the correct location in the data array for efficient processing. Since the switching period and frequency order may vary from shot to shot a bootconfig.rfctrl.ini file is consulted which informs where to start reading the binary file from on each iteration. The data is then copied to the GPU and the necessary signal processing tasks and data conditioning are performed. The noise of the local oscillator switch is removed, a smoothing box-car average is performed on each set of nInt points, the middle of each set of nInt points is taken to avoid any residual switching noise and unsmoothed subtraction and the data corresponding to channel 0, channel 1, channel 8 and channel 9 is shifted to correct for ADC timing errors. The data is then filtered with a bandpass and notch filter to remove some unwanted signals from each block of nInt and the IF dispersion between I and Q components caused by cable lengths is corrected. Performing sideband separation converts 16 real signals into 8 complex signals and another filter is performed for upper and lower sideband with calibration data correcting for phase offsets and balancing amplitudes be- tween the I and Q components. Calibration of the RF phase is also performed to correct the phase drifts in the RF channels after sideband suppression. Finally, once these corrections have been made, the cross-correlations between the signals for each antenna pair, frequency sweep and upper and lower sideband are calculated. This process is illustrated in FIG. 6. In total, 14 CUDA kernels were constructed to process the data and the CUFFT library was used to perform Fourier transforms.
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A Review Of Cuda, Mapreduce, And Pthreads Parallel Computing Models

A Review Of Cuda, Mapreduce, And Pthreads Parallel Computing Models

In this paper, we have endeavored to present a succinct overview of three parallel programming models, CUDA, MapReduce, and Pthreads. The goal is to assist high performance users with a concise understanding of parallel programming concepts and thus faster implementation of big data projects using high performance computing. Although there are many parallel, distributed, scalable programming that currently in existence, there was no model whose main goal through development was to create a high performance, distributed, parallel, and scalable programming environment that was easy to use. The innate ability of MapReduce to do it’s parallel and distributed computation across large commodity clusters at run-time allowed developers to express simple computations while hiding the messy details of communication, parallelization, fault tolerance, and load balancing. Furthermore, the use of job distribution through map and reduce phases, while using a distributed file system architecture for data storage and retrieval to produce a framework for easily writing applications which process vast amounts of data in parallel on large clusters using commodity hardware in a fault tolerant manner. Future works will focus on how MapReduce could be implemented in both CUDA and Pthreads.
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SICTIN: Rapid footprinting of massively parallel sequencing data

SICTIN: Rapid footprinting of massively parallel sequencing data

The advent of massively parallel sequencing technologies has opened a field for hypothesis-free investigation of e.g. protein-DNA interaction. In order to facilitate truly exploratory biological data mining we have designed and implemented a system where footprints over genomic features ranging in the order of hundreds of thousands can be rapidly constructed once the binary representation of the signals has been built. Such investigations could include signal over microsatellite repeats, ultra conserved regions or exons. Since the program suite also parses for instance the WIG-format, the analysis can easily be extended to footprinting GC-content or analysing any annotation track from the UCSC repositories [13].
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Pond: A Robust, scalable, massively parallel computer architecture

Pond: A Robust, scalable, massively parallel computer architecture

Having covered the architectures organization, communications, operation, and perfor- mance evaluation, we continue in this section to highlight and discuss its most relevant features and benefits. Provided there are sufficient atomic processors available, any num- ber of programs can execute in parallel without being impeded by structural dependencies. These, and implicitly structural hazards are practically eliminated. Any number of instruc- tions can execute concurrently, if there are no data and/or control dependencies. Also for example, if there are no data dependencies between the iterations of a loop, several or all iterations may execute concurrently. Current architectures employ loop unrolling, but the number of unrolled iterations is severely limited by the number of available registers and functional units, and the number of memory accesses. In the proposed architecture these structural bottlenecks are eliminated. As pointed out in the introduction, future technolo- gies will continue to offer an increasing number of components on a chip. However, some of these will fail prematurely or during the lifetime of the system. Therefore, for the design of any architecture the implication is that it must be robust, i.e. it must be able to tolerate component failures while continuing to operate nominally.
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Massively parallel sequencing and analysis of the Necator americanus transcriptome

Massively parallel sequencing and analysis of the Necator americanus transcriptome

Methodology/Principal Findings: A total of 19,997 contigs were assembled from the sequence data; 6,771 of these contigs had known orthologues in the free-living nematode Caenorhabditis elegans, and most of them encoded proteins with WD40 repeats (10.6%), proteinase inhibitors (7.8%) or calcium-binding EF-hand proteins (6.7%). Bioinformatic analyses inferred that the C. elegans homologues are involved mainly in biological pathways linked to ribosome biogenesis (70%), oxidative phosphorylation (63%) and/or proteases (60%); most of these molecules were predicted to be involved in more than one biological pathway. Comparative analyses of the transcriptomes of N. americanus and the canine hookworm, Ancylostoma caninum, revealed qualitative and quantitative differences. For instance, proteinase inhibitors were inferred to be highly represented in the former species, whereas SCP/Tpx-1/Ag5/PR-1/Sc7 proteins ( = SCP/TAPS or Ancylostoma-secreted proteins) were predominant in the latter. In N. americanus, essential molecules were predicted using a combination of orthology mapping and functional data available for C. elegans. Further analyses allowed the prioritization of 18 predicted drug targets which did not have homologues in the human host. These candidate targets were inferred to be linked to mitochondrial (e.g., processing proteins) or amino acid metabolism (e.g., asparagine t-RNA synthetase).
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Performance Analysis of a 3D Wireless Massively Parallel Computer

Performance Analysis of a 3D Wireless Massively Parallel Computer

One of the paths for future work is to abandon the principle of having static nodes and let them have freedom of movement (at least to some extent). The self-autonomy given to the nodes turns them into an agent or robot rather than just processing nodes. This touches on the idea of swarm robotics /swarm computing. The wide range of possibilities in this path is very convincing. Agents (formerly referred to as nodes) can organise themselves to fit a given task. They can collaborate and coordinate based on the assigned task and even the geography and geometry they operate in. This also touches on areas like distributed control. The applications of such a system range from modelling biological systems to social systems, robust control systems, monitoring, rescue missions, urban life management and many more.
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Programming GPUs with CUDA

Programming GPUs with CUDA

CUDA = Compute Unified Device Architecture • Software platform for parallel computing on Nvidia GPUs.. —introduced in 2006.[r]

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MPRAnalyze: statistical framework for massively parallel reporter assays

MPRAnalyze: statistical framework for massively parallel reporter assays

MPRA data is produced from two parallel procedures: RNA-sequencing is used to measure the number of transcripts produced from each barcode, and DNA- sequencing is used to measure the number of construct copies of each barcode. Thus for each barcode the ratio of RNA to DNA can serve as a conceptual proxy for the transcription rate [7]. However, both DNA and RNA mea- surement procedures provide an approximate and noisy estimation, an issue exacerbated by the unstable nature of a ratio: minor differences in the counts themselves can result in major shifts in the ratio, especially when deal- ing with small numbers. This problem can be handled by associating multiple barcodes with each sequence, pro- viding multiple replicates within a single experiment and a single sequencing library. This approach introduces an additional problem of summarizing counts from multi- ple barcodes to get a single transcription rate estimate for a candidate regulatory sequence, which is made diffi- cult since the efficiency of incorporation inside cells, while theoretically uniform across the different constructs, has a significant degree of variability in practice (Fig. 1a). Two commonly used techniques of addressing this issue are based on summary statistics: the aggregated ratio, which is the ratio of the sum of RNA counts across
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Massively parallel quantization implementation using simulated annealing

Massively parallel quantization implementation using simulated annealing

Currently, functionality of parallel image processing systems is designed in C us- ing a common framework with multiple flavors. Each employee has the freedom to some degree to use his own methods of supporting his or her development. In the case of image processing, some people choose to model their algorithm in Matlab. When they have finished this implementation and have a working model, they implement the algorithm from scratch in Very-High-Speed Inte- grated Circuit Hardware Description Language (VHDL) or some other target language.

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