nanoscale devices

Top PDF nanoscale devices:

Reliable integration of terascale systems with nanoscale devices

Reliable integration of terascale systems with nanoscale devices

The other successful fabrication technique is imprint lithography. Nanowires with sub-10 nm feature size can be made using imprint lithography [40]. This new tech- nique has high throughput and low cost. Imprint lithography includes little damages to sensitive circuit components, including active molecules, which are used in making programmable cross-points (section 2.2.3). Chen et al. have developed an inexpen- sive process to fabricate nanoscale devices and circuits utilizing imprint lithography, shown in [16]. This technique for fabricating aligned metal nanowires through a one- step deposition process without subsequent etching or lift-off is demonstrated in [41]. Their technique uses Molecular Beam Epitaxy (MBE) to create physical template for nanowire patterning. The template is a selectively etched GaAs/AlGaAs superlat- tice. The wires are defined by evaporating metal directly onto the GaAs layers of the superlattice after selective removal of the AlGaAs to create voids between the GaAs layers. By depositing the metal solely on the GaAs layers, the wire width is defined by the thickness of the GaAs layers and the separation width by AlGaAs layers. Transfer of the metal nanowires to a silicon wafer is performed by contacting the metal-coated template to a silicon oxide surface with subsequent heating process. Wires deposited with this technique were uniform and continuous over 2 to 3mm length, with very few defects.

181 Read more

Design Of Shallow Source / Drain Extension (SDE) Profiles In Improving Short Channel Effect (SCES) In Nanoscale Devices

Design Of Shallow Source / Drain Extension (SDE) Profiles In Improving Short Channel Effect (SCES) In Nanoscale Devices

In this era globalization, the technology of world is growth fast especially in electronic revolution. The companies compete with each other to invent the new devices that can be multitasking and many applications. The engineers become smart to design the chip with small sizes. Besides, the architecture of the chip must be concern for the better performance of the electronic devices. One of the solutions is to design of shallow source/drain extension (SDE) alternative to the conventional devices so that the performance are improved. In order to increase the mobility and the speed of the electronic devices, semiconductor technology researchers face the limitations such as short channel effect in MOSFET device as it is unavoidable in scaling. The aim of this project is to improve the short channel effect in nanoscale devices. Technology Computer Aided Design (TCAD) tool from Silvaco’s International® was used to design and simulate the structure designed in this project. Silvaco’s DEVEDIT software was used to design the structure of MOSFET according to the steps, while Silvaco’s ATLAS software was used to simulate the structure to obtain the output graph. The output graph and result analysis such as graph for transfer curves (I D –V GS ) and graph for

24 Read more

Performance Analysis of Gate All Around Field Effect Transistor for CMOS Nanoscale Devices

Performance Analysis of Gate All Around Field Effect Transistor for CMOS Nanoscale Devices

GAA inverter developed by 45 nm technology using Cadence tool is compared with 180 nm channel length. Low DIBL and high subthreshold slope is observed in 45 nm. Table 1 shows the comparison of different output parameters in respect of channel length. Inverter configuration has a reduction of delay (30%) and static power decrease is observed when comparison is done with 180 nm channel length.GAA inverter provide 85% lower power consumption than same configuration in 180 nm. High voltage gain ~10.1 and high noise margin (NMH = 0.82 V and NML = 0.41 V), therefore overall performance enhanced. GAA NW devices have excellent performance in respect of scaling of channel length. Short channel effect moderately reduced compared to planar one.GAA observed better improved performance result where scaling of channel is done.

5 Read more

ICP Etching of Silicon for Micro and Nanoscale Devices

ICP Etching of Silicon for Micro and Nanoscale Devices

imply hundreds of microamps. Other experiments conducted, similar to these, yielded similar results, with currents ranging from hundreds of picoamps to nanoamps. Before conducting a detailed analysis on the device physics of the nanoscale, it was obvious that this contacting problem required correction. Contacting a 400 nm diameter highly doped silicon pillar should have a very low resistance. Aside from the physics, which modified the shape of the curve from the ideal Ohmic to ‘s’ shaped, being the possible culprit for low conduction, three other potential contributions were considered. First, if the tungsten to silicon connection was actually a Schottky diode, vice an Ohmic tunnel contact, then as the resistances of the pillars increased it would adversely affect the conduction. When a diode is placed in series with a large resistor, increasing voltage causes an increase in current from the diode. This current increase also causes an increase in voltage dropped by the resistor. The result is that the voltage increase across the resistor reduces the voltage across the diode; a negative feedback which shuts the diode off. Second, parallel conduction paths or incorrect wiring from outside the Agilent SPA to inside the SEM would cause an erroneous measurement (which could be compounded with the Schottky diode). To eliminate this possibility, probe tip to probe tip measurements were made inside the SEM to ensure low series resistances; typical values were under 50 Ω. Further, open

219 Read more

Biomimetic patterned surfaces for controllable friction in micro- and nanoscale devices

Biomimetic patterned surfaces for controllable friction in micro- and nanoscale devices

Arvind Singh received his doctoral degree from the Indian Institute of Science (IISc), India in 2003. In his doctoral research work, he consolidated a new approach to understand metallic wear based on dynamically evolved microstructure. As a Materials Scientist at the John F. Welch Technology Center (GE India), he investigated tribological systems in aircraft engines and on super-abrasives. During his tenure as a Visiting Scientist at the Korea Institute of Science and Technology (KIST), South Korea, he proposed micro/ nano-patterns as biomimetic surfaces for tribological application in MEMS/ NEMS. He continued his research on biomimetics at the National University of Singapore (NUS), where he formulated novel surface modification methods to functionalize SU-8 polymer for tribological applications in MEMS/Bio-MEMS and for indwelling biomedical devices. At Vestas Global R&D, he investigated tribology of wind energy systems. Currently, at the Energy Research Institute (ERIAN), Singapore, he is leading tribology and surface engineering R&D projects related to wind & marine renewables. Kahp-Yang Suh received his doctoral degree from the Seoul National University (SNU), Korea in 2002. He specialized in micro/nano-patterning of polymeric surfaces using capillary force lithography/nanoimprint lithography, and made significant contributions to the field. He was a postdoctoral researcher at the Massachusetts Institute of Technology (MIT), USA. In 2004 he joined as an Assistant Professor at SNU. He was an outstanding faculty and researcher in the field of fabrication of micro/nano-polymeric patterns, whose applications ranged from tribology to lab-on-chip devices. He won a number of awards, including TR100 Young Innovator Award by MIT Technology Review, Best Graduate Student Award by the Brain Korea (BK) 21 Program of the Korean Government, Korea Presidential Young Scientist Award and Young Professor Award by College of Engineering of SNU. Arvind Singh and Kahp-Yang Suh, shared the ‘ First Surface Engineering Best Paper Award ’ , given by the Society of Tribologists & Lubrication Engineers (STLE), USA (2007), for their pioneering work on biomimetic approach as a robust solution for tribological issues in micro/nano-scale devices.

11 Read more

inSense: A Variation and Fault Tolerant Architecture for Nanoscale Devices

inSense: A Variation and Fault Tolerant Architecture for Nanoscale Devices

Future technology nodes, new devices, and novel materials present unfamiliar challenges due to their complexity and increased sensitivity to process and environmental variations. Consequently, the development of reliable systems from unreliable components and mate- rials is becoming a topic of increasing significance. The inSense Architecture is envisioned such that new designs can be realized with new technologies despite issues with reliabil- ity and device variation. The future of computing and electronics will require fundamental changes in the way that information is encoded and processed. While in the short-term this will entail new device structures and new materials, in the long term this may mean new information paradigms (e.g. spintronics or quantum computing) and novel logic system. Imbuing low-level hardware with sensory capabilities in order to regulate performance and enhance stability appears to be in line with these upcoming paradigm shifts.

90 Read more

Improvement of photon extraction efficiency of GaN based LED using micro and nano complex polymer structures

Improvement of photon extraction efficiency of GaN based LED using micro and nano complex polymer structures

In this study, micro- and nanoscale complex structures made of high refractive index polymer were formed to enhance the LED light extraction efficiency. The micro- and nanoscale structures were obtained from the photo- electro chemical (PEC)-etched surface of the N-faced GaN. The GaN epilayer of a vertical LED was detached from the sapphire substrate and placed over metallic heat sink; thus, the N-faced GaN surface was exposed. In order to improve the photon extraction efficiency of the vertical LED, the N-faced GaN surface was etched using the PEC process to form micro- and nanoscale structure [17]. Micro- and nanoscale patterns of N-faced GaN was repli- cated using a polydimethylsiloxane (PDMS) molding pro- cess and transferred to the ITO electrode surface of conventional edge emitting type GaN blue LED devices using nanoimprint lithography. Due to the micro- and

6 Read more

Wideband Optically transparent Coatings Based on Composite Nanoscale Materials for the Optoelectronic Devices

Wideband Optically transparent Coatings Based on Composite Nanoscale Materials for the Optoelectronic Devices

The second type of match in thick (up to 100 microns) polymer composite coating based on silver nanoparticles in the matrix of polymethylmethacrylate. Silver nanoparticles as the nanoantenna array with the absorption of optical radiation at a wavelength of 380-400 nm (surface plasmon resonance), and amplified reemission at higher wavelengths (more 500 nm). This phenomenon allows the use of such coatings as active coatings for glass and a number of optoelectronic devices, including photovoltaic cells.

6 Read more

Nanoscale surface modifications to control capillary flow characteristics in PMMA microfluidic devices

Nanoscale surface modifications to control capillary flow characteristics in PMMA microfluidic devices

Polymethylmethacrylate (PMMA) microfluidic devices have been fabricated using a hot embossing technique to incorporate micro-pillar features on the bottom wall of the device which when combined with either a plasma treatment or the coating of a diamond-like carbon (DLC) film presents a range of surface modification profiles. Experimental results presented in detail the surface modifications in the form of distinct changes in the static water contact angle across a range from 44.3 to 81.2 when compared to pristine PMMA surfaces. Additionally, capillary flow of water (dyed to aid visualization) through the microfluidic devices was recorded and analyzed to provide comparison data between filling time of a microfluidic chamber and surface modification characteristics, including the effects of surface energy and surface roughness on the microfluidic flow. We have experimentally

12 Read more

Interface traps and quantum size effects on the retention time in nanoscale memory devices

Interface traps and quantum size effects on the retention time in nanoscale memory devices

interface defect is amphoteric that is a donor level below mid gap and an acceptor level above mid gap. Memory structures based on nanocrystalline (NC) semiconductor have received much attention for next- generation nonvolatile memory devices due to their ex- tended scalability and improved memory performance [4-6]. Recently, the quantum size effects caused by the channel material NC Si neglecting the interface charge on the threshold voltage of thin-film transistors with- out float gate [7] and on charging the dynamics of NC memory devices [8] have been studied. Here, both the

5 Read more

Physical IC debug – backside approach and nanoscale challenge

Physical IC debug – backside approach and nanoscale challenge

Photon Emission is the standard functional analysis tech- nique of semiconductor devices as it occurs in a MOS Tran- sistor without any further stimulus when a considerable num- ber of carriers gain kinetic energy high enough to relax by emitting photons (Boit, 2004). This is happening in CMOS digital circuits mainly during rise and fall time of the signal pattern (Fig. 3). Although this dynamic light signal is faint, TRE is a very powerful, reliable and easy to interpret tech- nique with low risk of artifacts and time resolution in 10 ps regime (Vallett, 2004). Due to the low signal level, sampling of the signal is necessary. As the waveform is not repro- duced in full but the signal only represents the short switch-

8 Read more

Electronic Properties of Nanoscale Structures/Devices Atomically Engineered on Metal Surfaces

Electronic Properties of Nanoscale Structures/Devices Atomically Engineered on Metal Surfaces

Moore’s law epitomizes the technological revolution we currently enjoy, but it is also a warning of things to come – as current devices/technology shrink down further, quantum effects must be taken into account.[5] For transistors, quantum tunneling poses the most severe problem. Tunneling is a purely quantum phenomenon exhibited by particles when faced with an energy barrier – classically, a particle cannot overcome an energy barrier unless provided with sufficient additional energy; however, quantum mechanics gives a finite probability that the particle will be found on the opposite side of the barrier (Fig. 1.2). Fundamentally, transistors work on the assumption that we control the flow of current through them; hence, with the present design, tunneling gives an uncontrollable contribution to the current.

93 Read more

Simulating nanoscale semiconductor devices

Simulating nanoscale semiconductor devices

The next generation of electronic devices will be developed at the nanoscale and molecular level, where quantum mechanical effects are observed. These effects must be accounted for in the design process for such small devices. One prototypical nanoscale semiconductor device under investigation is a resonant tunneling diode (RTD). Scientists are hopeful the quantum tunneling effects present in an RTD can be exploited to induce and sustain THz frequency current oscillations. To simulate the electron transport within the RTD, the Wigner-Poisson equations are used. These equations describe the time evolution of the electrons’ distribution within the device. In this paper, this model and a parameter study using this model will be presented. The parameter study involves calculating the steady-state current output from the RTD as a function of an applied voltage drop across the RTD and also calculating the stability of that solution. To implement the parameter study, the computational model was connected to LOCA (Library of Continuation Algorithms), a part of Sandia National Laboratories parallel solver project, Trilinos. Numerical results will be presented.

14 Read more

Graphene as a Platform for Novel Nanoelectronic Devices

Graphene as a Platform for Novel Nanoelectronic Devices

current as measured by a DL Instruments 1211 current preamplifier. 3 Figure 3.1 demonstrates the process for a single, representative device (identified by the red markers in part a). The baseline I-V (Figure 3.1b, inset) demonstrates a before-breakdown conductance of 250 µS. The breakdown I - V is shown in Figure 3.1b. Starting from 0 V, the voltage is ramped up at a uniform rate of 50 mV/s. At a critical sheet current density of approximately 1.6 mA/µm, the measured current drops precip- itously, indicating breakdown of the graphene sheet. Interestingly, the conductance I { V increases before breakdown, possibly due to current-driven annealing [53]. Figure 3.1c shows an electron mi- crograph of the device after breakdown, containing an distinct break across the graphene channel. Atomic force microscopy (AFM) confirms that a physical gap forms in the graphene. In the most narrow segments the gap’s width is typically less than 10 nm, although the precise location of the closest approach is difficult to determine due to the finite resolution of AFM. Thus, the device after breakdown includes a nanoscale junction between two physically separated sheets of graphene.

135 Read more

STUDY  OF FRICTION  AT NANO SCALE

STUDY OF FRICTION AT NANO SCALE

Behaviors of friction at macroscale are not valid at nanoscale all the time. The friction force presents numerous behaviors at the nanoscale when the sliding velocity is changed. Thus, the study of the friction phenomenon has to be done at scales relevant for its applications. we study the dependence of the nanofriction on the velocity, while taking into account the normal force and the humidity. The complete understanding of the velocity dependence of the friction at the nanoscale is still under current reflection.Since no real consensus has been found until now, we propose here a look back to the Tomlinson model and reviewed the main experimental results on the velocity dependence of the friction, having a look at the same time at the evolutions of the basic Tomlinson model to interpret the results. The two basic experimental observations about the friction phenomenon at the nanoscopoic level are 1) The static and dynamic friction might be seen as two distinct frictional phenomena.The static force depends on the atomic structure of the sliding surfaces and the adhesion forces and can be related to the breaking of bonds.The dynamic friction is the force necessary to balance the energy losses due to the motion of one body against the other one. It is directly related to energy dissipation. 2)We observed a saw-tooth shape of the friction loop while scanning flat surfaces like mica. This shape is due to the atomic stick and slip of the tip sliding on the surface. It allows us to introduce the Tomlinson model explaining the experimental observations .

10 Read more

Light-based Rapid Prototyping of Micro- and Nanoscale Medical Devices for Drug Delivery and Regenerative Medicine.

Light-based Rapid Prototyping of Micro- and Nanoscale Medical Devices for Drug Delivery and Regenerative Medicine.

Although SLS/SLM is compatible with a wide range of materials, the use of SLS/SLM in biomedical application is limited by several factors. When performing SLS/SLM, it is necessary that the precursor materials are in powder form [29]. Also, these processes involve high temperatures, eliminating the possibility of structuring with materials containing heat- sensitive components, such as proteins or cells. On the other hand, several studies have demonstrated that cells can be seeded onto materials after SLS/SLM processing is completed [136-138]. Materials processed by SLS generally exhibit high porosities and significant surface roughness, and, therefore, often have mechanical properties inferior to the bulk material [25, 112]. Since SLM involves complete melting of the feedstock material, materials processed using SLM exhibit lower porosities and exhibit mechanical properties that are more similar to those of the bulk material than structures produced by SLS [25]. It is important to note that SLS/SLM is currently the only laser direct write process that is capable of producing metallic medical devices.

535 Read more

Design sram using finfet

Design sram using finfet

As CMOS technology shows certain limitations on the devices, also as such the device is reduced more and more in the nanometer regime out of which power dissipation, current leakages, doping, and channel length is an important issue. FinFET is evolving to be a promising technology in this regard. In this the designing, modeling and optimizing the 6-T SRAM cell device is done. Intrinsic variations and leakage control in today’s world, is very difficult to achieve, So bulk-Si MOSFETs limit the scaling of SRAM.

5 Read more

Design, Synthesis, and Characterization of Nanoscale Optical Devices Using DNA Directed Self-Assembly

Design, Synthesis, and Characterization of Nanoscale Optical Devices Using DNA Directed Self-Assembly

Self-assembled DNA photonic wires are a potential candidate to be used in nanoscale communications, biosensing, and in light harvesting applications. Molecular photonic wires exploit F ¨orster Resonance Energy Transfer (FRET) to transfer energy through nonradiative dipole-dipole interactions. Recently, homogeneous FRET (homoFRET) has emerged as a potential way of increasing photonic wire energy transfer efficiency. However, little is known about the basic design principles needed to construct synthetic multistep photonic devices that incorporate homoFRET despite its well-known occurrence in natural photosynthesis. In this work, we attempt to address this knowledge gap by designing, constructing, and characterizing a DNA photonic wire with a 10-dye reconfigurable homoFRET center. The DNA labeled fluorophores were attached inside a six-helix bundle nanotube to form a 30 nm long photonic wire. Over 50 wire configurations were characterized using steady-state and time-resolved fluorescence measurements. Several wire configurations were shown to have increased the end-to-end efficiencies. A ∼ 200% increase in the end-to-end to efficiency was observed when the first fluorophore was removed from the full wire, as compare to the full functionalized wire.

227 Read more

Forward Look on Nanoelectronics and nanotechnologies

Forward Look on Nanoelectronics and nanotechnologies

Current nanoscale research efforts on interconnects provide a number of promising ideas, which require further development and especially integration into system-wide interconnect concepts. Molecular interconnects using nucleic acid (RNA, DNA)- assembled wires, molecular templating and molecular recognition could be a route to automate on-chip wiring. Diverse templating has been achieved for 15nm Au particles assembled between Au contacts, but so far only activated, non-ohmic conduction has been demonstrated. Chemical or biochemical (DNA) templates for assembling functional carbon nanotubes devices are also being developed, including a recently- demonstrated "lithography free" nanotube FET assembled onto DNA strands. The challenges here are to prepare individual devices, assemble a large number of them in a dynamic and (re)configurable way and ensure good electrical properties of the interconnects based, for example, on metallised nucleic acids. Other routes to self- assembly involves the growth of nanowires or nanotubes at pre-defined locations.

18 Read more

Bismuth and Germanium Nanoscale Cluster Devices

Bismuth and Germanium Nanoscale Cluster Devices

Immediately after deposition, the gate effect was small and any changes in re- sistance or carrier concentration were due to oxidation and capacitive effects from ramping the gate bias. As the samples slowly oxidized in vacuum, an increase in the gate effect was observed as a decrease in the overall carrier concentration was observed. Therefore, the gate bias was able to more effectively enhance the current. The germanium devices in this project show a maximum gate effect when the sample had been able to oxidize for a few days in vacuum, just prior to venting, with a 12% change in resistance observed for a 50 V gate bias. The magnitude of the gate effect increased with time when the sample was in vacuum because the overall carrier concentration was decreasing so the gate bias was able to more effectively enhance the current. The opposite effect was observed when the films were vented to air; the carrier concentration increase resulted in a less effective current enhancement. The gate effect observed in germanium devices was small compared to germanium transistors from the literature, where a 5 V gate bias would affect the source drain current by a factor of 10 5 .

159 Read more

Show all 6572 documents...