Network on Chip

As indicated by several researchers and the International Technology Roadmap for semiconductors (ITRS), nanometre System-on-Chip (SOCs) will most likely not have an economic yield if all transistors must be functional. Besides, it is expected that Moore’s law will continue to hold for another five to fifteen years where billion gates can be integrated in a chip. This capacity will allow integration of several tens to hundred resources like processor cores, DSP cores, Interface circuits, FPGA blocks and Memory blocks. Thereby, it is possible to integrate more than one processing element (PE) in a SOC, being known as Multi-processor System-on-chip (MPSoC). MPSoCs have been widely used in high performance embedded systems, such as web servers, network processors, and parallel media processors. They combine the advantages of data processing parallelism of multi-processors, and parallel media processors. The Network-on-chip (NoC) architecture paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication design issues such as performance limitations of long interconnects, and integration of high number of PE on a chip. A tiled-based 2D-mesh NoC based system, where one or more cores and other resources are encapsulated into a tile. It consists of Routers (R), PE and Network interfaces (NI). PEs may be intellectual property (IP) blocks or embedded memories. Each PE is connected to the corresponding router port using the network interface. This enables to use packets for transferring information between PEs without requiring

Abstract— Networks-on-chip (NoCs) have emerged as a promising on-chip interconnect for future multi/many-core architectures as NoCs are able to scale communication links with the growing number of cores. In this paper, we present an adaptive route allocation algorithm which provides a required level of QoS (guaranteed bandwidth) coupled with an adaptive buffer assignment scheme which reassigns buffer blocks up-demand.Inaddition, the adaptivity requires a comprehensive, hardly invasive, runtime discernibility infrastructure, i.e., using supervising components, in order to collect data on the system put forward. The area overhead brought in by the adaptive scheme can be traded off against the tractability acquired. furthermore, the area operating cost is also reduced by resource manifolding due to the on-demand buffer assignment at each output port (we achieved on an average 42% buffer saving in our experiments).The proposed network-On-Chip can be modelled using Verilog HDL and simulated using Modelsim software.

Network on chip or network on a chip (NoC or NOC) is a communication subsystem on an integrated circuit (commonly called a “chip” ),typically between intellectual property (IP) cores in a system on a chip (SoC). NoCs can span synchronous and synchronous clock domains or use uncloked synchronous logic. NoC technology applies networkingtheory and methods to on-chip communication and brings notable improvements over conventional bus and crossbar interconnections. NoC improves the scalability of SoCs, and the power efficiency of complex SoCs compared to other designs. This integrated microprocessor has been a landmark in the evolution of computing technology. Whereas it took monstrous efforts to be completed, it appears now as a simple object to us. Indeed, the microprocessor involved the connection of a computational engine to a layered memory system, and this was achieved using busses. Complex application-specific integrated circuits (ASICs) were designed to address-specific applications. These systems required multiprocessing over heterogeneous functional units, thus requiring efficient on-chip communication. On the other side, multiprocessing platforms were developed to address high- performance computation—such as image rendering. Furthermore, the chapter explains variability and design methodologies of NoCs. Dealing with variability is an important matter affecting many aspects of systems-on-chips (SoC) design. The first important issue deals with malfunction containment. Traditionally, malfunctions are avoided by putting stringent rules on physical design and by applying stringent tests on signal integrity before tape out. This approach is conservative in nature and leads to a perfect physical layout of circuits.

As the era of a billion transistors on a one chip approaches, a lot of Processing Elements (PEs) could be located on a System-on Chip (SoC). Most Processing elements within the SoC communicate with each other via buses and memory. Because the number of bus masters will increase in a single chip, the significance of fast and powerful arbiters commands additional consideration. Especially, a fast arbiter is one of the greatest main factors for high performance network switches. Also fast and efficient switch arbiters are required to switch packets in a Network-on-Chip (NoC) [1] [2]. But, fairness in arbitrations could be a very tedious and error-prone task for designers, to design with high performance. Network- on-Chip may be an advanced interconnection of several functional elements. It is the essential demand to deal with complexity of recent systems which is a general purpose on-chip communication idea that gives high throughput [3- 5]. It iterates communication bottleneck within the gigabit communication because of its bus based architecture. So there was a necessity of systems that express modularity and parallelism. Network-on-Chip possesses several such attractive properties and solves the problem of communication bottleneck [6]. It essentially works on the concept of interconnection of cores using on chip network. The communication on NoC is carried out by means of router, so for implementing better NoC, the router should be efficiently designed. The switching mechanism used here is packet switching that is usually used on Network- on-Chip [7-9]. The information transfers in the form of packets between cooperating routers. In packet switching routing decision is taken independently. The store and forward flow mechanism is the most excellent method because it does not reserve channels and does not lead to idle physical channels. Due to simplicity and low overhead

Number of processing elements are increased continuously on bus base system on chip, they face design challenges and complexity increases. This system on chip is not scalable for a complex system , In system on chip data flow limited by resourses, results in slow communication occur.This bus base design needs to be replace with latest network architecture called network on chip. Network on Chip (NoC) is a new paradigm to make the interconnections inside a System on Chip (SoC) system. It reduces complexity of designing wires and also increases speed and reliability [1]. It is able to address the increasing interconnect complexity challenges[5]. It improves scalability of SoC and power efficiency of complex SoC. To carry on chip communication router play important role, it is use to route the incoming data towards the destination , and design of router is one of the the most important factor that impact on network performance.

A number of research studies have demonstrated the feasibility and advantages of Network-on-Chip (NoC) over traditional bus- based architectures. This whitepaper summarizes the limitations of traditional bus- based approaches, introduces the advantages of the generic concept of NoC, and provides specific data about Arteris‟ NoC, the first commercial implementation of such architectures. Using a generic design example we provide detailed comparisons of scalability, performance and area of traditional busses or crossbars vs. Arteris‟ NoC.

Abstract: The Network-on-Chip (NOC) concept has recently become a widely discussed technique for handling the large on -chip communication requirements of complex System-on- Chip (SOC) designs. A traditional bus-based interconnection scheme does not scale well to very large SOCs because many Intellectual Property (IP) blocks must contend with each other to communicate over the shared bus. In contrast, an on-chip network uses the packet-switching paradigm to route information between IP blocks and it can be scaled up to achieve a very lar ge total aggregate bandwidth within the chip. The issues of applying the Code-Division Multiple Access (CDMA) technique to an on-chip packet switched communication network are discussed in this paper. A packet switched Network-on-Chip (NOC) that applies the CDMA technique is realized in Register-Transfer Level (RTL) using VHDL. The realized CDMA NOC supports the Globally-Asynchronous Locally-Synchronous (GALS) communication scheme by applying both synchronous and asynchronous designs. In a packet switched NOC, which applies a point-to-point connection scheme, e.g., a ring topology NOC, data transfer latency varies largely if the packets are transferred to different destinations or to the same destination through different routes in the network. The CDMA NOC can eliminate the data transfer latency variations by sharing the data communication media among multiple users concurrently. A six- node GALS CDMA on-chip network is modeled and simulated. The characteristics of the CDMA NOC are examined by comparing them with the characteristics of an on-chip bidirectional ring topology network. The simulation results reveal that the data transfer latency in the CDMA NOC is a constant value for a certain length of packet and is equivalent to the best case data transfer lat ency in the bidirectional ring network when data path width is set to 32 bits.

Number of processing elements on single chip called system on chip (SoC). System on chip having very complicated structure it supports bus base communication. Network on Chip (NoC) has been proposed and has replaced the System-on- Chip of bus structure. It reduces complexity of designing wires and also increases speed and reliability.Topology shows the connectivity and distribution of nodes. The performance of a NoC is extremely sensitive to its topology because topology determines the system cost, as well as performance bounds for the network by setting the average message hop count and network bisection bandwidth. Finding a proper topology for an application in which the number of intermediate routers between communicating cores with heavy Communication demand is minimized [8].

Abstract: Basically, the denser integration capabilities will enable silicon technology scaling continuously. But in silicon technology higher variability and susceptibility will obtain. In this paper an effective network interfaces architecture if introduced for fault tolerant mechanism network on chip. A chip multi processor is introduced on chip components but this processor will not give effective output. Hence, the introduced system gives high throughput in modern network on chips. This system will exploit the speed of appropriate wire engineering which will transfer the long distance in single clock cycle. The data will be transferred between NOC routers by using Network interface (NI) and IP cores. Hence the proposed architecture will save the life time and overcome the issues of previous system.

Abstract. In this paper, we present an idea for perform- ing matrix-vector multiplication by using Network-on-Chip (NoC) architecture. In traditional IC design on-chip commu- nications have been designed with dedicated point-to-point interconnections. Therefore, regular local data transfer is the major concept of many parallel implementations. How- ever, when dealing with the parallel implementation of sparse matrix-vector multiplication (SMVM), which is the main step of all iterative algorithms for solving systems of linear equation, the required data transfers depend on the sparsity structure of the matrix and can be extremely irregular. Using the NoC architecture makes it possible to deal with arbitrary structure of the data transfers; i.e. with the irregular struc- ture of the sparse matrices. So far, we have already imple- mented the proposed SMVM-NoC architecture with the size 4 × 4 and 5 × 5 in IEEE 754 single float point precision using FPGA.

ABSTRACT: The processor designing and development was designed to perform various complex logical information exchange and processing operations in a variety of resolutions. They mainly rely on concurrent and sync, both that of the software and hardware to enhance the productivity and performance. With the high speed growth approaching multi-billion transistor integration era, some of the main problems which are symbolized by all gate lengths in the range of 60-90 nm, will be from non-scalable delays generated by wire. All similar problems may be solved by using Network on Chip (NOC) systems. In the presented paper, we have summarized research papers and contributions in NOC area. With advancement in the technology in the on chip communication, faster interaction between devices is becoming vital. Network on Chip (NOC) can be one of the solutions for faster on chip communication. For efficient link between devices of NOC, routers are needed. This paper also reviews implementation of routing techniques. The use of routing gives higher throughput as required for dealing with complexity of modern systems. It is mainly focused on the routing design parameters on both system level including traffic pattern, network topology and routing algorithm, and architecture level including arbitration algorithm.

ON a chip with billion transistors, sending a global signal across the chip maintaining a real – time bound may not be possible. To mitigate this problem, one can think of designing an asynchronous system. However, designing an asynchronous system is way more complex than designing a synchronous system [1]. Thus, a viable solution that researchers have taken up is to combine synchronous and asynchronous designs. One such technique at hand is GALS (Globally synchronous and locally asynchronous). GALS solution divides a system into locally decoupled synchronous systems and bring together few of them to form a localized subsystem. These subsystems can then be easily integrated together to form a global solution. The synchronous sub – systems shall be communicating asynchronously at the system level. Thus, decomposing the overall problem of system synchronization to just synchronizing the local subsystems. One of these GALS solutions is Network – On – Chip (NoC). NoC can greatly improve design time by supporting modularity and reuse of complex cores, which enables to attain higher level abstraction in architectural modelling [2]. On – Chip network or Network – On – Chip (NoC) is a communication subsystem embedded on an IC (integrated Circuits) commonly known as ―Chip‖. The micro network embedded on the chip enables communication flow between IPs (Intellectual properties: - So called because of their development by third party companies) cores. A NoC can span synchronous and asynchronous clock domains and can also use unclocked asynchronous logic. Incorporation of a network on the chip brings notable advantages, such as, improved communication between IPs as compared to conventional bus and crossbar interconnection, scalability, and power efficiency of complex SoCs as compared to other design paradigms [3]. Factors that governing NoC includes topology, routing algorithm, flow control etc. Topology which is defined as the placement or arrangement of the above mentioned components to make a structure of the network. A topology can be loosely referred to as the road map, where channels carry messages (data

The immense capacity of integration offered by the semiconductors technology makes it possible from now to conceive integrated systems on chip (SoC). The realization of these systems is subjected to several performance constraints such as cost, production time and marketing. Therefore the interconnection between electronic components is a major concern of research. Thus, Networks on Chips (NoCs) have been introduced as an efficient solution for the growing problems of current interconnects in VLSI chips [1] [2]. In fact NoC is becoming a field of research which still requires a lot of intervention. The difficulty of the NoC design lies in compromise between optimal quality of service (QoS), high use of band-width and flexibility, while optimizing metric design (limitation of the consumption of energy, minimization of plugs’ size and silicon surface). Majority of current works are focused on switches in the networks on chip [3] [4] [5] [6] and [7], considering it is the key element in architectures. Switches occupy almost 90 percent of the space allotted to the network on chip. So NoC switches should be small, energy efficient, and fast. The complexity of the switch design mainly depends on the size of the buffer and the processing time of a flit. The evaluation of these proposed solutions and the NoC architecture, most researches uses directly simulation [7] [9] [10] or hardware implementation [3]. However, other researchers treat the analytical prediction. Authors in [27]

NoC (Network on Chip) is a promising technology for the interconnection network. Performance of an interconnection network depends on the routing logic. We explore the state of art of the existing routing algorithms for mesh connected network. In this paper we have tried to model the distance routing for mesh connect NoC network. The performance of the distance routing is compared with that of the dimension order and odd-even routing algorithms. Experimental analysis on synthetic traffic shows that our proposed distance routing outperforms the state of the art of routing algorithms by increased link utilization fairness.

Abstract—A generic analytical performance model of single- channel wormhole routers is presented using the M/D/1/B queuing theory. Compared with previous work, the flow- control feedback mechanism is studied in detail, and a computing method bases on Markov chain for the flow- control feedback probability is proposed. Compared with BookSim, a well-known cycle-accurate Network-on-Chip (NoC) simulator, this model presents accurate results on key metrics: the average relative error of flow-control feedback probability is about 7.87%. In addition, based on the model of single-channel routers, the asymmetric multi-channel and symmetric multi-channel structured routers are both modeled respectively.

A Network on Chip is one of the important block in many multi-core systems. Designing and implementation of NoC’s are very important as they describe system performance. Throughput and latency are the important parameters that describe the quality of the NoC. This paper gives an overview of traditional bus based architecture and its disadvantages. NoC’s offer much less delay by providing multiple paths to communicate. Arbiter and Router are the important blocks of NoC. Dimension order Routing is considered with X-Y routing algorithm and this algorithm is used to define paths in the traffic patterns.

A variety of interconnection schemes are currently in use, including crossbar, buses and NOCs. Of these, later two are dominant in research community. However buses suffers from poor scalability because as the number of processing elements increases, performance degrades dramatically. Hence they are not considered where processing elements are more. To overcome this limitation attention has shifted to packet-based on-chip communication networks, known as Network-On-Chip (NOC).

Low power network on chip design has become a vital paradigm in the CMOS technology. Since network on chips are likely to consume a considerable part of the total chip power, the design of low power on chip proces- sor offers a general approach for overall performance improvement. NoC consumes a significant portion of total chip power in multicore systems. Some recent researches in a low power network on chip design [26]-[28] ar- chitectures are validated to be 10% - 36%. Therefore, necessities of latency and power-aware NoC lead to a se- rious issue in designing low power multicore systems. In order to provide those provisions, designers introduced several dynamic voltage and frequency scaling algorithms with application and traffic aware system. There is a single way to hold the power concern using conventional scaling algorithm. Conventional researchers have pro- posed DFS for general purpose [29] [30] and multimedia applications [31]. However, the results of conventional works focus on either processor or cache power reduction. Recently, frequency scaling algorithms on NoCs are proposed to further reduce the additional components in NoC like interconnect and core power dissipation. Some past work offers similar methods of NoCs [27] [28] [32] by scaling the voltage/frequency of individual routers, links, or the whole networks. However, these results still focus on general-purpose domain, whereas in multimedia application the traffic aware systems are the emerging research area. The conventional designs are examined under heavy traffic mode, the major problem in performance degradation. Those works are specifi- cally focused on either power or latency, even both performances of NoC. In order to bring better solutions in terms of an end to end delay and other performance parameters, we introduce an FSM-DFS for NoC.

A Network-on-Chip (NoC) is a new paradigm in complex System-on-Chip (SoC) designs that provides efficient on-chip communication architecture. It offers scalable communication to SoC and allows decoupling of communication and computation. In NoC, design space exploration is critical due to trade-offs among latency, area, and power consumption. Hence, analytical modeling is an important step for early NoC design. This paper presents a novel top-down approach router model, and utilizes this model for analysis mesh NoC performance measured in terms of throughput, average of queue size, efficiency, and loss and wait time. As case study, the proposed model is used to map a MPEG4 video core to a 4x4 mesh NoC with deterministic routing to measure the overall NoC quality of service, The model is used also to present how much occupancy of average queue size for each router that reduces resources (hardware) area and cost. The accuracy of this approach and its practical use is illustrated through extensive simulation results.

Abstract — Complex homogeneous network-on-chip or heterogeneous network-on-chip increases the need of determining and developing simulation tools for designer to evaluate and comparison network performance. Towards this end, ARTEMIS tool, a matlab based simulator environment is developed. This simulator offers some collections of network configuration regarding to the topology graph, routing algorithm and switching strategy, including allocation scheme for a target application. Consequently, designers can choose the number and depth of virtual channels and the capacity of each link by applying an efficient allocation scheme, which is provided by this tool. Average latency and throughput are evaluation performance metrics that are measured with proposed simulator tool.