Network-on-Chip Design
A Monitoring-Aware Network-on-Chip Design Flow
26
Performance Improvement of Application Specific Network on Chip Design using Genetic Algorithm
6
Thermal Uniformity Aware Application Mapping for Network on Chip Design
15
Application-Specific 3D Network-on-Chip Design Using Simulated Allocation
6
Design and Verification of Asynchronous Five Port Router for Network on Chip
5
Design and Implementation of an Efficient Router for 3D Network-On- Chip
8
Design and Verification Eight Port Router for Network on Chip
5
DESIGN AND PERFORMANCE ANALYSIS OF FAULT SECURE NETWORK ON CHIP USING FPGA
6
Design of low power network on chip using data encoding techniques
8
Efficient Router Architecture design on FPGA for Torus based Network on Chip
6
Design and Implementation of Smart Error Detecting Network on Chip Based Router Architecture
8
Design and Analysis of On-Chip Router for Network on Chip
5
An FPGA-Based Design of an Intelligent On-Chip Sensor Network Monitoring and Control
7
Design of Low Power and Low Latency Novel Scheme for Network on Chip
5
Design of Efficient Router with Low Power and Low Latency for Network on Chip
11
Design of Network Router for System on Chip Applications Palaparthy Adam & M Ramakrishna
6
System-on-Chip Design and Implementation
11
Design of On-Chip Permutation Network with Programmable Arbiter for application level selection of arbitration scheme
9
An Enhanced Inter/Intra-Chip Optical Network for Chip Multiprocessors
6
ON-CHIP PERMUTATION NETWORK IN MULTIPROCESSOR SYSTEM ON-CHIP FOR ADDRESSING PERMANENT ERRORS
7