On-chip Interconnection Networks
Design of Router Micro Architecture Based on Runtime Adaptive Selection Strategies for On-Chip Communication Interconnection Network
... The first method is called algorithmic routing and is suitable for on-chip and off-chip networks with regular topologies. In this method, a finite-state machine (FSM) is used for computing the routing ...
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A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band
... and chip area ...on-chip networks have been proposed to improve the communication efficiency of multicore ...a chip increases, the performance is limited by the communication among and within ...
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Relaiblity and Fault Analysis in On Chip Network
... on chip cache/processor-to-cache networks where network utilization is ...low. Interconnection networks are commonly used to connect different computing ...on chip cache-to- cache and ...
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A Novel Low Power Optimization for On-Chip Interconnection
... Abstract- This paper presents a low power design methodology for the Quasi Resonant Interconnection networks (QRN). This focuses mainly on reducing the power utilized at the receiver by replacing the ...
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Strong Matching Preclusion for Augmented Butterfly Networks
... of interconnection networks is very difficult as strong matching preclusion that additionally permits more destructive vertex faults in a graph is a more extensive form of the original matching preclusion ...
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An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links
... per chip, and the number of chips in the system is varied from one to a maximum of four for this work’s experiments, yielding different systems of sizes 64, 128, 192 and 256 ...independent chip are ...
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Carbon nanotube bumps for the flip chip packaging system
... CNT bumps had been demonstrated by several groups as potential off-chip interconnects [4-6]. Soga et al. have shown the bumps’ good mechanical flexibility and low bundle resistance of 2.3 Ω (for a 100-μm diameter ...
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Process Development for an Ultra High Density Chip-on-Chip Power Module.
... 3D chip-on-chip power modules for the NCSU-PREES ...flex-circuit-based chip-on-chip approach has been selected to demonstrate fabrication processes to produce very high power density ...
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Wirelength of Circulant Networks into Wheel Related Graphs
... telecommunication networks due to their optimal fault tolerance and routing ...alignment networks for complex memory systems. Undirected circulant networks arise in the context of Mesh Connected ...
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Live Weather Report Using IOT with Graphical Display
... the interconnection of devices and people through the traditional internet and social networks for various day-to-day applications like weather monitoring, healthcare systems, smart cities, irrigation ...
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Control of the interconnection between the decentralized electricity networks of the Adrar region (Southern Algeria) and the network of Algeria with optimal location of SVC devices for the improvement of stability
... The optimal proposal, after several variants of interconnection between the two zones, is presented in Figure-1. It represents the Algerian geographical map with a presentation of the lines and substations and ...
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Modular Neural Networks Chronicles in Biological Aspects
... sub networks able to manages a subsets of the data and depending on its Modularizing learning ,the relevance task is decomposed and distributed over sub-task separated in modules deals with determination of the ...
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A High performance Interconnection Networks for Middle Scale Data Center
... In this paper we propose a novel structure of interconnection networks for middle size of data center, called TDNode. TDNode is a recursively defined using transversal design theory as its underlying ...
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Dense edge disjoint embedding of complete binary trees in interconnection networks
... We have described dense edge-disjoint embeddings of the completebinary tree with n leaves in the following n-node intercommunication networks: the hypercube, the de Bruijn and shue-exchange graphs and the ...
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An Efficient Monarchic Reconfiguration Protocol with Deadlock Freedom on Interconnection Networks
... CONCLUSION This paper proposed Monarchic Reconfiguration Protocol MRP that enables to autonomously recover from link failures during reconfiguration.MRP will generate an effective reconf[r] ...
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Interconnection of Cable Networks: A Regulation Proposal for Broadband Internet Services
... For modelling a scenario of asymmetric networks, we consider, as starting point, the formalization presented in Carter and Wright (1999, 2003). Firstly, it is considered that a consumer of the broadband internet ...
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Communication-centric debug of systems-on-chip using networks-on-chip
... The prediction of Gordon Moore in 1965 that the transistor density of semiconductor chips would double every 18 months still holds true. Designers can not keep pace with the increas- ing design complexity which results ...
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Research on Topology Structure Analysis of Several Interconnection Networks
... some networks have very good fault tolerance ability, but the vertex degree is too high, it will lead to the cost of the construction of the network greatly ...symmetrical interconnection network ...
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Progress report on the European electronic communications market 2008 (14th report). Commission staff working document accompanying the report. SEC (2009) 376 final/2/Vol. 1 part 2, 30 July 2009
... mobile networks, both the incumbent operator and the second MNO are faced with considerable delays 62 and difficulties in obtaining all the necessary permits for the roll- out of their mobile ...
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02_ComputerEvolutionandPerformance.ppt
... • Reduce frequency of memory access — More complex cache and cache on chip • Increase interconnection bandwidth. — High speed buses[r] ...
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