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shared-memory architecture

A scalable and reconfigurable shared memory architecture for large scale graphics applications

A scalable and reconfigurable shared memory architecture for large scale graphics applications

... DDR memory and other mo- therboard resources ...DDR memory and any adjacent Opteron pro- cessors at full HyperTransport [Con03] bandwidth with ...Access Memory (SRAM) at ...the shared system ...

191

Current Trends in Parallel Computing

Current Trends in Parallel Computing

... Shared Memory Parallel Computing Models In shared memory architecture a number of processors are connected to a common central memory.. Since all processors are sharing a single address [r] ...

7

Survey on Pure Parallel Programming Models: OpenMP and MPI

Survey on Pure Parallel Programming Models: OpenMP and MPI

... a shared memory Application Programming Interface (API) whose aim is to ease Shared Memory parallel ...across Shared Memory ...

5

WRL 95 9 pdf

WRL 95 9 pdf

... relaxed memory models by ensuring sequentially consistent results for certain programming ...strong memory operations roughly corresponding to synchroniza- tion operations and weak operations roughly ...

398

IN-MEMORY BIG DATA MANAGEMENT

IN-MEMORY BIG DATA MANAGEMENT

... Abstract: In this innovative world, organizations like amazon, Google, Facebook etc. are facing tremendous increase in data. This leads to the problem of storing, analyzing processing and managing terabytes or petabytes ...

6

Architecture, heritage, history, memory

Architecture, heritage, history, memory

... post-modern architecture in South Africa represents a desire to erase, to dismiss local senses of ...European architecture, one which is ...an architecture which abolishes local memories in the name ...

17

GPU Memory Architecture Optimization.

GPU Memory Architecture Optimization.

... the memory subsystem, implying a longer latency for a request to be served by L2 cache or ...lengthened memory access latency and performance degradation for the three ...shorter memory access ...

108

Wait free shared memory irradiance caching

Wait free shared memory irradiance caching

... bounded shared IC, without using any locks or critical sec- ...a shared memory ...the shared IC every time a thread ac- cesses it, both for reading and ...

15

Implementing Shared Memory Parallelism in MCBEND

Implementing Shared Memory Parallelism in MCBEND

... Since each ‘sample history’ within stage 2 of a MCBEND shielding calculation is statistically independent from all the others, implementing multi- threading to the simple model presented in figure 1 is conceptually a ...

6

Shared Architecture for Encryption/Decryption of AES

Shared Architecture for Encryption/Decryption of AES

... As the cryptography is playing the major role in today‟s world. So the frequency is the main concern so that the time period can be minimized. Here the basic of AES algorithm is explained in brief and the implementation ...

6

Structures of experience: media, phenomenology, architecture

Structures of experience: media, phenomenology, architecture

... In his formulation of critical regionalism Frampton argues for a method of incorporating advanced building techniques, while simultaneously placing limits on their tendencies of standardization. His approach to design ...

20

Essential Traffic Parameters for Shared Memory Switch
Performance

Essential Traffic Parameters for Shared Memory Switch Performance

... workloads. Shared memory switches represent the best candidate architecture to exploit buffer capacity; we analyze the performance of this ...target architecture than pre- vious work and ...

15

An Update to the iLab Shared Architecture for Mobile Device Support

An Update to the iLab Shared Architecture for Mobile Device Support

... The platform chosen for this work is the iLab Shared Architecture (ISA) developed as the Massachusetts Institute of Technology [34, 22, 23]. This platform was chosen due to the fact that it is one of the ...

15

98629A SRM Firmware ERS Feb83 pdf

98629A SRM Firmware ERS Feb83 pdf

... Other' features of the interface are: -- shared memory with the mainframe, using the same scheme as the 98628 for sharing the memory -- half-duplex communications to other mainframes -- [r] ...

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ARCHITECTURAL CLASSIFICATIONS

ARCHITECTURAL CLASSIFICATIONS

... Uniform memory access parallel computers (UMC): in a shared memory computer system all processors share a common global address ...in memory is constant for all ...Uniform Memory Access ...

35

SPIDAL Java: High Performance Data Analytics with Java on Large Multicore HPC Clusters

SPIDAL Java: High Performance Data Analytics with Java on Large Multicore HPC Clusters

... Solution is to use processes with shared memory communications as in SPIDAL Java. process[r] ...

18

Testing of a Novel Distributed Shared Memory Framework

Testing of a Novel Distributed Shared Memory Framework

... a shared memory. By having a single bus and a single shared memory that contains only one copy of each data item and the semaphore that controls access to that data, it provides a system whose ...

98

Optimizing Memory Efficiency for Many-Core Architecture.

Optimizing Memory Efficiency for Many-Core Architecture.

... for memory-intensive ...the memory access streams to L1 D-caches for many applications contains a significant of requests with low reuse, which greatly reduce the cache ...GPU architecture. With the ...

158

A 10-Gbps Energy Efficient On-Chip Wireless Communication Network for Multicore Processing

A 10-Gbps Energy Efficient On-Chip Wireless Communication Network for Multicore Processing

... At the transmitter, the output of each CDMA spreading operation must be summed together to allow simultaneous transmission. There is a maximum of 16 spreading codes to be summed, and because of the randomness of the ...

8

A Systemc Cache Simulator for a Multiprocessor Shared Memory System

A Systemc Cache Simulator for a Multiprocessor Shared Memory System

... a shared cache line and the status of the cache line remains the ...multiprocessor architecture implies more cache programming complexity and cache coherency is a major concern in the performance of the ...

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