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Si/oxynitride gate interface

Characterization of High-k Gate Stacks in Metal-Oxide-Semiconductor Capacitors

Characterization of High-k Gate Stacks in Metal-Oxide-Semiconductor Capacitors

... alternative gate dielectrics for future generations of ...κ gate stacks using physical and electrical characterization techniques, to gain a better understanding of some important factors associated with ...

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Characterization of Hf Si Oxynitride Pseudo-ternary Gate Dielectrics for the Application of Ge MOSFETs.

Characterization of Hf Si Oxynitride Pseudo-ternary Gate Dielectrics for the Application of Ge MOSFETs.

... slow- interface traps deep in the band gap because nitrided samples show a significant dispersion in the inversion region as the frequency is reduced, indicating the presence of slow-interface states ...of ...

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Breakdown and Reliability of CMOS Devices with Stacked Oxide/Nitride and Oxynitride Gate Dielectrics Prepared by RPECVD

Breakdown and Reliability of CMOS Devices with Stacked Oxide/Nitride and Oxynitride Gate Dielectrics Prepared by RPECVD

... of interface traps and hole trapping by the interfacial nitridation ...at gate/drain interface for shorter channel devices, causing an enhancement of a positive off-state leakage ...the gate ...

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Electronic hardware design for ultrasound Transient Elastography

Electronic hardware design for ultrasound Transient Elastography

... The hardware design has been altered and made flexible enough to work at very high frame rates. This helps to program the FPGA or alter the frequency, timing etc so that it is useful in distinguishing malignant and ...

5

Heterointerface dipoles: Applications to (a) Si-SiO2, (b) nitrided Si-N-SiO2, and (c) SiC-SiO2 interfaces

Heterointerface dipoles: Applications to (a) Si-SiO2, (b) nitrided Si-N-SiO2, and (c) SiC-SiO2 interfaces

... of gate dielectrics must be reduced pro- portionally to less than 3 nm, a thickness regime in which direct tunneling can play a significant role in the off-state leakage ...with interface nitridation at the ...

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Charge Storage Characteristics of Pi-Gate Poly-Si Nanowires TaN-Al2O3-Si3N4-SiO2-Si Flash Memory

Charge Storage Characteristics of Pi-Gate Poly-Si Nanowires TaN-Al2O3-Si3N4-SiO2-Si Flash Memory

... gate TaN structure enhances the program/erase efficiency and reliability. This NVM device has a high fast program/erase (P/E) speed; A 3 V memory window can be achieved by applying 18 V for only in 10 μs. With ...

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Investigation of postoxidation thermal treatments of Si/SiO2 interface in relationship to the kinetics of amorphous Si suboxide decomposition

Investigation of postoxidation thermal treatments of Si/SiO2 interface in relationship to the kinetics of amorphous Si suboxide decomposition

... Observations in conductivity measurements also support an amorphous state segregation mechanism. Figure 6 shows both the dark- and photocurrent of films of various compo- sition before and after annealing at 650 °C. For ...

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Reduced 1/f noise in p Si0 3Ge0 7 metamorphic metal–oxide–semiconductor field effect transistor

Reduced 1/f noise in p Si0 3Ge0 7 metamorphic metal–oxide–semiconductor field effect transistor

... 300 nm p-type (5 ⫻ 10 19 cm ⫺ 3 ) polycrystalline silicon gate. The LF noise was measured using an HP 35670A dy- namic signal analyzer and custom-made preamplifier con- taining OPA637 共 Texas Instruments 兲 and ...

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Construction of TiO2/Si Heterostructure by Nanoepitaxial Growth of Anatase-type TiO2

Construction of TiO2/Si Heterostructure by Nanoepitaxial Growth of Anatase-type TiO2

... Monocrystalline Si belongs to face-centered cubic ...monocrystalline Si, square is formed by four Si atoms. In each square, two Si atoms are on the face n of o j n uni n h o h o Si om h ...

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Design and Implementation of a Brain Computer Interface using Brain Gate

Design and Implementation of a Brain Computer Interface using Brain Gate

... 3) The limits between the useful parts ought to adjust however much as could reasonably be expected with existing interface innovation to encourage examinations between BCI advances and non-BCI UI advances. The ...

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Measurement and Control of In-plane Surface Chemistry at the Si/SiO2 Interface.

Measurement and Control of In-plane Surface Chemistry at the Si/SiO2 Interface.

... a Si-Si bond with a Si-O-Si combination, which is somewhat ...both Si atoms were same and the bond linear, then the SHG response of the configuration would ...terminating Si ...

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													Highly sensitive compact isfet electro-chemical sensor in avalanche region of operation

1. Highly sensitive compact isfet electro-chemical sensor in avalanche region of operation

... The sensitivity of an ISFET is proportional to ΔIds/ΔVT, where ΔIds is the change in the drain source current and ΔVT is change of interface potential at gate, due to the capture or adsorption of analytes. ...

6

A Study on Copper-Gate Integration with Titanium Interface Layers for IGZO TFTs

A Study on Copper-Gate Integration with Titanium Interface Layers for IGZO TFTs

... process. These defects may have been apparent after the passivation TEOS deposi- tion done at 390 o C, but the devices are typically not inspected using a microscope between the passivation dielectric deposition and the ...

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Flexible carbon nanotube/mono crystalline Si thin film solar cells

Flexible carbon nanotube/mono crystalline Si thin film solar cells

... mono-crystalline Si thin films were prepared by chemical etching of n-type (100) Si wafers (4 ...etched Si thin films were rinsed in deionized water several times to remove the residual ...the ...

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The impact of self heating and SiGe strain relaxed buffer thickness on the analog performance of strained Si nMOSFETs

The impact of self heating and SiGe strain relaxed buffer thickness on the analog performance of strained Si nMOSFETs

... strained Si technology on SiGe SRBs must be careful to ensure that the bias terminals of the MOSFET are such that the drain conductance is not ...of gate and drain voltages caused by the possibility of ...

35

Linearity and mobility degradation in strained Si MOSFETs with thin gate dielectrics

Linearity and mobility degradation in strained Si MOSFETs with thin gate dielectrics

... splitting) can explain mobility enhancement at medium vertical fields (where phonon scattering is the dominant mobility limiting mechanism) but not at high vertical fields (where surface roughness scattering is the ...

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Integration of HfO2 on Si/SiC heterojunctions for the gate architecture of SiC power devices

Integration of HfO2 on Si/SiC heterojunctions for the gate architecture of SiC power devices

... The physical and electrical properties of silicon car- bide (SiC), including its wide band gap (3.26 eV ), high critical electric field (3 M V /cm) and thermal conduc- tivity (3.7 W/cmK), make it an attractive material ...

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Electronic properties of the Zr-ZrO2-SiO2-Si(100) gate stack structure

Electronic properties of the Zr-ZrO2-SiO2-Si(100) gate stack structure

... The interface electronic structure of a layered Zr– ZrO 2 – SiO 2 – Si 共 100 兲 system was studied with x-ray 共h ␯ = 1254 eV兲 and ultraviolet 共h ␯ = ...the Si, and internal fields in a layered high- ␬ ...

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Development of a fully-depleted thin-body FinFET process

Development of a fully-depleted thin-body FinFET process

... the gate length for optimal device ...the gate length to effectively suppress SCE, while more aggressive estimates place the maximum fin width at ½ to ⅔ of gate ...the gate length is usually ...

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Brain Gate Neural Interface  System

Brain Gate Neural Interface System

... brain gate technology, she is able to guide a robotic arm towards a bottle of water, grab it up, and drink ...brain gate interface consists of a sensor implanted in Cathy's brain, which is used to ...

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