silicon oxynitride gate dielectrics

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Electron mobility in MOSFETs with ultrathin RTCVD silicon nitride/oxynitride stacked gate dielectrics

Electron mobility in MOSFETs with ultrathin RTCVD silicon nitride/oxynitride stacked gate dielectrics

The effective electron mobility for oxynitride/nitride stacked gate dielectrics has been examined. The mobility is shown to be degraded by coulombic scattering from interface charges and bulk dielectric charges probably located at the silicon oxynitride/nitride interface. In this study, those samples which had their interfacial oxynit- ride layers grown at 100 Torr in nitric oxide yielded thinner effective stack thicknesses and higher mobility than those whose interfacial layers were grown at 1 Torr. It is suggested that these benefits are due to the forma- tion of an interfacial dielectric with a more SiO 2 -like
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Characterization of Hf Si Oxynitride Pseudo-ternary Gate Dielectrics for the Application of Ge MOSFETs.

Characterization of Hf Si Oxynitride Pseudo-ternary Gate Dielectrics for the Application of Ge MOSFETs.

The properties of HfSiON on Ge as a function of surface treatment are investigated in this chapter. To investigate the effect of surface passivation treatment on germanium, four types of surface passivation were employed: (1) 1nm of Si + RPAN (15 sec.), (2) 0.6nm of Si + RPAN (50 sec.), (3) 0.6 nm of Si + RPAN (15 sec.), and (4) RPAN (90 sec.). AES using a 3 keV electron beam was performed in the on-line analysis chamber to investigate wet chemical cleaning and the initial stage of formation of a thin “pseudomorphic” silicon layer (an order of 1nm) on the Ge surface. To investigate the chemical structure of the Si passivation layer after HfSiON deposition, high-resolution ex situ X-ray photoelectron spectroscopy (XPS) was performed with 260 and 650 eV soft X-ray excitation to provide some depth resolution. The elemental Si interlayer (Si 0+ oxidation state, BE ~99.3 eV) is still present after oxide deposition. It is noteworthy that the combination of a pseudomorphic Si layer followed by nitridation yields a high quality passivation layer on Ge. A maximum hysteresis of 16 mV corresponding to a slow trap density of 7 x 10 10 cm 2 , a fixed oxide charge density of 2.2 x 10 11 cm 2 , and a D it of 7 x 10 11 cm -2 eV -1 were obtained for a Ge MOS
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Transition from thermally grown gate dielectrics to deposited gate dielectrics for advanced silicon devices: A classification scheme based on bond ionicity

Transition from thermally grown gate dielectrics to deposited gate dielectrics for advanced silicon devices: A classification scheme based on bond ionicity

There are several significant issues that impact on the per- formance of devices with deposited transition gate dielec- trics. The first group relates to process integration issues. The second group derives from inherent relationships between 共 a 兲 chemical bonding and physical properties, and 共 b 兲 device operation. These include 共 i 兲 reduced interfacial band offset energies, 共 ii 兲 interfacial fixed charge, 共 iii 兲 interfacial trapping of electrons, and 共 iv 兲 coordination dependent dielectric con- stants. These are illustrated with respect to studies in which the gate dielectrics stacks were prepared by RPECVD. Simi- lar results have been obtained by other deposition ap- proaches, including physical vapor deposition followed by postdeposition oxidation 共 See Ref. 2 and references therein 兲 . One of the paramount issues in the integration of depos- ited metal–oxide and metal–oxide alloy dielectrics in Si CMOS devices is the formation of the Si–dielectric inter- face. As in the case of Si nitride and the Si oxynitride alloys, the interface can be formed 共 i 兲 during deposition of the al- ternative dielectric 共 ii 兲 in a separate and distinct predeposi- tion step, or 共 iii 兲 during a postdeposition anneal in an oxygen containing ambient. Since there are significant differences in the reaction kinetics for different approaches to film deposi-
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Manuscript Title & Authors

Manuscript Title & Authors

With the rapid development of the semiconductor industry, the feature size of the devices always follows Moore's law. That means the feature size of the devices is gradually decreasing, and the quality and function of IC(Integrated circuit) is improving greatly. At present, improving system performance of the integrated circuit mainly by reducing the size of devices, and it is related to the physical thickness of CMOS gate dielectrics. Once the thickness of the equivalent SiO 2 gate dielectrics is less than 1nm, the edge value of
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Surface reactions during plasma enhanced chemical vapor deposition of silicon and silicon based dielectrics

Surface reactions during plasma enhanced chemical vapor deposition of silicon and silicon based dielectrics

For the IV analysis, substrates were moderately-doped silicon, and aluminum dots (~2000Å thick) were evaporated onto the oxide film through a shadow-mask to form metal-oxide-semiconductor capacitors. Dynamic I-V characteristics were made with a programmable Keithley 4145 with a ramp rate of 1 V/s. Most low temperature dielectrics can have significant densities of charge trap states, and careful IV analysis is required for repeatable characterization. Therefore, the IV measurement sequence was as follows. For each wafer analyzed, a test capacitor was ramped to breakdown to determine the approximate breakdown voltage. A new capacitor was chosen, and the first IV trace was collected as the voltage was ramped from zero to close to the breakdown field. On the same capacitor, the voltage was ramped again from zero, and a second IV trace was collected up to the breakdown voltage. When a significant density of charge traps are present, the second trace will result in a significantly reduced measured current. The charges trapped during the first trace result in a built-in field that opposes the applied field, reducing the net field across the insulator, therefore leading to a lower measured current. The difference in the two traces can therefore be used characterize the density of charge traps in the material. If the leakage is sufficiently small, charge trap information can of course be directly obtained from flatband shift and hysteresis in capacitance voltage measurements.
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Electrical Characteristics Of High-K Dielectrics For The 19NM Gate Length NMOS Device

Electrical Characteristics Of High-K Dielectrics For The 19NM Gate Length NMOS Device

With new technologies, many industries to rely on a manufacturing of smaller, faster, cheaper and good quality of the MOSFET. With increasing global competition, modern industries have to adapt their production process to be more efficient and competitive. In order to more advanced technologies have to employ to scale down the MOSFET into nanoscale [1]. Silicon oxide (SiO 2 ) has been used as the gate dielectric

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Characterization of High-k gate dielectrics based on HfO2 and TiO2 for CMOS Application

Characterization of High-k gate dielectrics based on HfO2 and TiO2 for CMOS Application

were performed in a light-tight box. Capacitance-voltage data was analyzed using NCSU-CVC Version 7. which extracts parameters from measured capacitance- voltage traces. As for ultrathin gate oxides, quantum mechanical effects near the surface, specifically increased band bending due to localized energy levels, and the charge centroid being located further from the surface than classically predicted, lead to incorrect C-V parameter extraction in classical analysis. NCSU-CVC Version 7 (Hauser’s program) corrects for these-quantum mechanical effects and uses the non linear least squares fitting technique, allowing a more accurate analysis of the data.
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Lightwave circuits for integrated Silicon Photonics

Lightwave circuits for integrated Silicon Photonics

In Chapter 2 low-loss integrated structures have been addressed, using a different guiding material: Si 3 N 4 . Silicon nitride is a silicon-compatible material that offers an intermediate refractive index between those of silicon and silica. The high trans- parency over a large bandwidth and the lower index with respect to silicon permit to realize low-loss structures that operate from the infrared region down to the vis- ible. UHQ resonators based on thick Si 3 N 4 layers have already been demonstrated. However, the devices reported in literature were realized in 900 nm thick Si 3 N 4 res- onators, that require special treatments to avoid film cracking. In this chapter Si 3 N 4 resonators with quality factors comparable to those known from the literature have been reported, realizing structures that feature a Si 3 N 4 film as thin as 115 nm. The structures have been realized exploiting a strip-loaded (SL) configuration, which is conceptually similar to the rib geometry used to achieve low-loss SOI waveguides in Chapter 1. Although pioneering studies on the SL geometry date back to the seven- ties, the field seems still rather unexplored. During this work the SL configuration has been studied and optimized for two particular operating wavelengths, requiring a priori single mode operation. During the experiments it was demonstrated that the single mode operation condition imposed during the simulation stage could be relaxed, obtaining resonant structures with much higher performances. The UHQ- factors obtained within such structures, together with the relaxed fabrication require- ments suggest that the strip-loaded configuration should be considered as a legitimate silicon-compatible integrated platform for the development of high-performance PIC. The modeling and simulations of the structures developed during this work indeed suggest that there is still space for further improvement, especially considering de- velopment in terms of used materials and optimization of the geometry.
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Optimization of nitrided gate dielectrics by plasma-assisted and rapid thermal processing

Optimization of nitrided gate dielectrics by plasma-assisted and rapid thermal processing

effect has its origin in effects well-known in physical optics, where thin surface layers of transparent materials with dif- ferent optical indices of refraction will either enhance or re- duce surface reflectivity, and thereby reduce or enhance, re- spectively, the optical transmission independent of the surface on which the light is incident. The optical path length for these surface layers must be in the range of about one- quarter of the optical wavelength in the surface layer mate- rial. For this type of mechanism to apply to the nitrided oxide dielectrics, the monolayer nitridation would have to have an effective index of refraction higher than that of the oxide surface. Stated differently, the reduced tunneling mechanism would have to rely on a significant phase shift for the electron transport in the nitrided layer relative to that of the non-nitrided interface. This type of contribution to the tunneling transport needs additional theorectical and experi- mental study.
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Linearity and mobility degradation in strained Si MOSFETs with thin gate dielectrics

Linearity and mobility degradation in strained Si MOSFETs with thin gate dielectrics

channel and the gate dielectric is not atomically smooth; hence, carriers scatter against surface asperities in strong inversion conditions. These Si channel surface asperities can be characterised by the root-mean-square roughness and the correlation length [26]. Surface roughness can be modelled as variations in oxide thickness, hence carriers transiting along the channel will be perturbed by a change in potential that is proportional to the average roughness amplitude [26, 27]. According to the Fermi golden rule, the scattering rate is proportional to the square of the perturbation potential resulting from the surface roughness [28]. Under high vertical fields, n in equation 8 is usually 2 for electrons and 1 for holes [7, 25, 26, 28, 29]. Under such conditions, equation 8 can be re-written for electrons as
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Low series resistance structures for gate dielectrics with a high leakage current

Low series resistance structures for gate dielectrics with a high leakage current

The quasistatic (QS) model is used when the operating frequency is low, so the device is able to respond fast enough to follow the small-signal input signal. The charge present in the channel below the gate has no time depen- dency and is in a steady-state. If the opposite occurs, a channel propagation delay will be present and there is a distributed effect of the channel resis- tance. This is also known as the non-quasistatic (NQS) effect. The channel resistance is determined by adding two types of resistances : 1) the static dc channel resistance and 2) the excess-diffusion channel resistance. The latter is caused by the distributed nature of the channel, when high frequencies are applied and long channels are used [29]. Successively, the effective unit-area gate capacitance (C gg,unit ) value will be lowered for devices with long channel
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In- and Ex-Situ Analysis of Silicon Oxide, Silicon Oxynitride, and Silicon Nitride Interfaces by Second Harmonic Generation and Correlation with Other Linear Optical Techniques

In- and Ex-Situ Analysis of Silicon Oxide, Silicon Oxynitride, and Silicon Nitride Interfaces by Second Harmonic Generation and Correlation with Other Linear Optical Techniques

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Interaction of Metal Gatew with High-K Gate Dielectrics in Advanced CMOS Devices

Interaction of Metal Gatew with High-K Gate Dielectrics in Advanced CMOS Devices

[23] Hobbs, C.C.,Fonseca, L.R.C., Knizhnik, A.; Dhandapani, V.; Samavedam, S.B.; Taylor, W.J.; Grant, J.M.; Dip, L.G.; Triyoso, D.H.; Hegde, R.I.; Gilmer, D.C.; Garcia, R.; Roan, D.; Lovejoy, M.L.; Rai, R.S.; Hebert, E.A.; Hsing-Huang Tseng; Anderson, S.G.H.; White, B.E.; Tobin, P.J., “Fermi-level pinning at the polysilicon/metal oxide interface-Part I”, IEEE Transaction of Electron Devices, Vol. 51, Issue 6, 971-977, 2004. [24] Hobbs, C.C.; Fonseca, L.R.C.; Knizhnik, A.; Dhandapani, V.; Samavedam, S.B.; Taylor, W.J.; Grant, J.M.; Dip, L.G.; Triyoso, D.H.; Hegde, R.I.; Gilmer, D.C.; Garcia, R.; Roan, D.; Lovejoy, M.L.; Rai, R.S.; Hebert, E.A.; Hsing-Huang Tseng; Anderson, S.G.H.; White, B.E.; Tobin, P.J., “Fermi-level pinning at the polysilicon/metal oxide interface-Part II”, IEEE Transaction of Electron Devices, Vol. 51, Issue 6, 978-984, 2004. [25] Patrick S. Lysaght, Jeff J. Peterson, Brendan Foran, Chadwin D. Young, Gennadi Bersuker, Howard R. Huff, “Physical and electrical characterization of polysilicon vs. TiN gate electrodes for HfO2 transistors”, Materials Science in Semiconductor Processing 7, 259–263, 2004.
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Carbon assisted growth and high visible light optical reflectivity of amorphous silicon oxynitride nanowires

Carbon assisted growth and high visible light optical reflectivity of amorphous silicon oxynitride nanowires

substrate, and C layer is formed by sputtering initially. From the above analysis, a carbon-assisted vapor-solid mechanism is proposed for the growth of Si-O-N nano- wires, where carbon has played an important role by introducing a redox reaction with the native silicon oxide layer. The proposed reactions that might have taken place are as follows:

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Ru-based Gate Electrodes for Advanced Dual-Metal Gate CMOS Devices

Ru-based Gate Electrodes for Advanced Dual-Metal Gate CMOS Devices

devices continues further, this polysilicon depletion effect will be a major problem and will most likely be unacceptable for 50nm and beyond devices. As devices scale down, polysilicon depletion becomes more significant. With the anticipated scaling by constant field scaling, the oxide field remains essentially constant. This means that the charge per unit area in the polysilicon gate remains constant with scaling. This may result in the voltage drop in the polysilicon as long as gate-doping density remains constant. Thus, since voltage levels decrease, the polysilicon voltage drop becomes a larger fraction of available device voltage and current drive is subsequently reduced. From literature reports, it is anticipated that it will be difficult to get electronically active doping densities much above 10 20 /cm 3 for n-type poly and above the mid 10 19 /cm 3 for p-type poly. This represents a significant degradation in current drive capability. In addition, boron out-diffusion from the P+ doped silicon gates can travel through the gate dielectric and accumulate in the n-Si substrate where it can change the threshold voltage and reduce dielectric reliability, thereby again degrading device characteristics. Finally, it is expected that polysilicon will not be stable on most high-K dielectric materials above since it can react to form silicides. Therefore, the use of stable metallic gate electrodes may solve the above issue.
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High field induced stress suppression of GIDL effects in TFTs

High field induced stress suppression of GIDL effects in TFTs

stress showing reduction in GIDL current.......................................................................... 2   Fig. 2. Subthreshold characteristics of two NFETs showing GIDL current at various drain voltages. As the drain voltage increases so does the current in the off-state [4]. .............. 4   Fig. 3. GIDL in a gated diode configuration showing deep-depletion region and hole and electron band-to-band tunneling. Energy band diagram showing tunneling election from valence to conduction band resulting in excess drain current [4]....................................... 5   Fig. 4. Schematic of N-channel TFT showing the PBT GIDL effect [6]. .......................... 7   Fig. 5. Drain sweep comparison of SOI TFT short-channel and long-channel GIDL behavior that shows the effects of a parasitic bipolar transistor. ........................................ 8   Fig. 6. From top to bottom: No LDD, fully overlapped LDD (with polysilicon spacer), and partially overlapped LDD oxide spacer. Adapted from [9]. ....................................... 9   Fig. 7. Cross section of LDD MOSFET with two GIDL current generation regions shown [5]...................................................................................................................................... 10   Fig. 8. SOI TFT showing interface traps created after either normal mode (N-mode) or reverse mode (R-mode) hot carrier stressing [10]. ........................................................... 11   Fig. 9. (a) Accumulation mode PFET above threshold showing both current in the accumulation layer as well as current in the body. (b) Accumulation mode PFET in subthreshold regime showing body conduction. (c) Accumulation mode PFET in the OFF-state showing inversion layer at the surface of the device [13]. .............................. 14   Fig. 10. (a) Cross-section of fully-depleted SOI TFT showing both top and back gate. (b) Cross-section of partially depleted SOI TFT showing the floating body [14]. ................ 15   Fig. 11. Modeled subthreshold characteristics of an accumulation mode PFET with L=10 µm using Atlas with an implementation of band-to-band tunneling model for realization of GIDL........................................................................................................... 18   Fig. 12. Atlas cross-section of the simulated accumulation-mode PFET. Source/drain regions were specified with doping concentrations of 10 19 cm -3 with a Gaussian lateral distribution of 0.05 µm. Ideal electrodes are specified and have no physical dimension.
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Silicon nanocrystals for silicon photonics

Silicon nanocrystals for silicon photonics

minescence spectrum of a sample fabricated at Intel during our collaboration is shown in figure 2.4. This spectrum is entirely consistent with previously reported silicon nanocrystal photoluminescence results. It is now well established that the characteristic near-infrared photoluminescence, typically observed in the range from ∼ 650 nm to ∼ 950 nm, originates from the band-to-band recombination of quantum confined excitons [52]. Interface states involving oxygen bonds are thought to play an important role in smaller nanocrystals, which emit photons at lower energies than predicted by theory [112]. Reports of silicon nanocrystal photoluminescence at green or blue wavelengths in oxide matrices tend to be met with skep- ticism, and are commonly assumed to be misinterpretations of defect luminescence within the oxide matrix [24]. Within the near-infrared emission band, the emission wavelength can be tuned by controlling the diameter of the silicon nanocrystals [104]. While the strength of band-to-band radiative recombination increases with decreasing nanocrystal size over this spectral range, a transition to a direct gap band structure has not been observed. It has been proposed that the oxygen bond related interface states dominate the recombination for small nanocrystals that might otherwise show direct gap behavior [52]. For this reason, silicon nanocrystals embedded in nonoxide matrices such as Si 3 N 4 have recently attracted
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Fabrication and Evaluation of Devices Containing High K Gate Dielectrics and Metal Gate Electrodes for the 70 and 50NM Technology Nodes of ITRS

Fabrication and Evaluation of Devices Containing High K Gate Dielectrics and Metal Gate Electrodes for the 70 and 50NM Technology Nodes of ITRS

Aggressive scaling of CMOS devices has enabled high speed operation and high density today’s chips. However we are rapidly reaching a fundamental limit with respect to obtaining benefits of transistor scaling. The 2001 edition of the International Technology Roadmap for Semiconductors (ITRS) calls for more rapid scaling than previously anticipated. Semiconductor chips with feature sizes nodes of 0.18 µm (180 nm) with 0.13 µm (130 nm) technologies are just beginning to reach the marketplace and plans are in the place to deliver 90 nm technologies [1]. Table 1 shows the equivalent physical gate oxide thickness for high performance as a function of technology node. There are a number of issues associated with the continued MOSFET scaling for sub 100 nm technology nodes. When the physical thickness of SiO 2 is scaled down below 1.5 nm,
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Review Literature for Mosfet Devices Using High K

Review Literature for Mosfet Devices Using High K

In the current version of the International Technology Roadmap for Semiconductors (ITRS), the scaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) is projected to the year 2016 when the channel length should be 9 nm as shown in Figure 1 [1]. Recently, some semiconductor companies have moved to the leading-edge of the 32 nm technology node and successfully realized advanced product development. Presently companies are continuing research and development the 22 nm and beyond complementary metal oxide semiconductor (CMOS) technology [4]. Oxide materials with large dielectric constants (so-called high-k dielectrics) have attracted much attention due to their potential use as gate dielectrics in MOSFETs [2].
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OXIDATION OF SILICON - THE VLSI GATE DIELECTRIC

OXIDATION OF SILICON - THE VLSI GATE DIELECTRIC

This gate oxide thickness range-a few tens of atomic layers- is also the range in which the oxidation kinetics and the oxide growth mechanism depart from the ‘standard[r]

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