Square Carry select adder root CSLA(SQRT CSLA)
128 BIT SQUARE ROOT CARRY SELECT ADDER
6
FPGA Implementation of High Speed Architecture of CSLA using D-Latches
13
Design and Implementation of Reduced Area and Low Power SQRT CSLA and its Application in ALU
9
KNOWLEDGE EXTRACTION METHOD USING STOCHASTIC APPROACHES IN GOOGLE MAPS
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CSLA Implementation Technique to Minimise the Area, Power and Delay Bhagya Sri Gutthikonda & P Bala Murali Krishna
6
Performance Analysis of Low Power 8 Tap FIR Filter using PFAL
10
Design and Implementation of Efficient Carry Select Adder in QCA
8
Implementation and Comparison of Effective Area Efficient Architectures for CSLA
INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES MANAGEMENT LOW-POWER AND AREA-EFFICIENT CARRY SELECT ADDER
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128 BIT MODIFIED SQUARE ROOT CARRY SELECT ADDER
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Title: AREA-DELAY EFFICIENT IMPLEMENTATION OF SQRT-CSLA
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A NOVEL DELAY EFFICIENT CARRY-SELECT ADDER USING RECURSIVE LOGIC Priyanka Agrawal 1, Prof. Vijay Yadav2 , Prof. Rahul Shrivastava
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Design of 32 bit Carry Select Adder with Reduced Area
5
Performance Analysis of Array multiplier using Optimized SQRT CSLA
5
Design of High Speed Hybrid Sqrt Carry Select Adder
5
Design of Modified Russian Peasant Multiplier using MSQRTCSLA based adder
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An Efficient Wallace Tree Multiplier using Modified Adder
5
16 BIT UNSIGNED MULTIPLIER USING PROPOSED CSLA
6
A Low Power Binary to Excess-1 Code Converter Using GDI Technique
6
Power-Efficient Carry Select Adder
6