two-dimensional hardware implementation

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The Turtles Project: Design and Implementation of Nested Virtualization

The Turtles Project: Design and Implementation of Nested Virtualization

To improve virtualization performance, x86 architec- tures recently added two-dimensional page tables [13]— a second translation table in the hardware MMU. When translating a guest virtual address, the processor first uses the regular guest page table to translate it to a guest phys- ical address. It then uses the second table, called EPT by Intel (and NPT by AMD), to translate the guest physi- cal address to a host physical address. When an entry is missing in the EPT table, the processor generates an EPT violation exception. The hypervisor is responsible for maintaining the EPT table and its cache (which can be flushed with INVEPT), and for handling EPT viola- tions, while guest page faults can be handled entirely by the guest.
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Hardware Implementation of Redundant CORDIC Processors

Hardware Implementation of Redundant CORDIC Processors

COordinate Rotational DIgital Computer is abbreviated as CORDIC. The key concept of CORDIC arithmetic is mainly based on the simple and ancient principles of two dimensional geometry. The origin of the CORDIC algorithm can be traced back to as early as 1624 when Henry Brigg mentioned about digit by digit method for the computation of elementary functions like multiplication and division. It was Jack E. Volder in 1959 [1] [2], who described a novel computational algorithm suitable for special purpose digital computing machine known as Co-Ordinate Rotational Digital Computer (CORDIC) for the computation of trigonometric functions besides multiplication and division [3,4]. Initially it was developed for building real time navigational computer for use in an aircraft and had focused on implementing mostly trigonometric functions.
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VLSI Implementation of Image Denoising Algorithm using Dual Tree Complex Wavelet Transform

VLSI Implementation of Image Denoising Algorithm using Dual Tree Complex Wavelet Transform

In this effort, a hardware-software co-simulation algorithm has been designed for denoising images and implemented on FPGA. The registered noisy images are considered for this work. Then the noisy image of size 256*256 have been applied to 2D-1D block for the conversion of the two- dimensional image data to one dimensional bit stream using simulink block sets. Then, it is given as inputs to system generator model for FPGA implementation process. The proposed denoising model implements a forward 2-level DTCWT hardware to decompose the noisy image into transform domain and the sub band coefficients are obtained. Except the approximate sub band coefficients all the six detail sub bands (Three from first level and three from second level) of real tree and the corresponding six sub bands of imaginary tree are denoised with the hardware shown in fig (6). The denoised sub band coefficients are reconstructed back into spatial domain with the corresponding reverse 2-level DTCWT hardware shown in fig (7).
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CMSC 427 Computer Graphics 1

CMSC 427 Computer Graphics 1

Let us begin by considering the process of drawing (or rendering) a single image of a 3-dimensional scene. This is crudely illustrated in the figure below. The process begins by producing a mathematical model of the object to be rendered. Such a model should describe not only the shape of the object but its color, its surface finish (shiny, matte, transparent, fuzzy, scaly, rocky). Producing realistic models is extremely complex, but luckily it is not our main concern. We will leave this to the artists and modelers. The scene model should also include information about the location and characteristics of the light sources (their color, brightness), and the atmospheric nature of the medium through which the light travels (is it foggy or clear). In addition we will need to know the location of the viewer. We can think of the viewer as holding a “synthetic camera”, through which the image is to be photographed. We need to know the characteristics of this camera (its focal length, for example).
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 EDUCATIONAL MODELLING IN CLOUD COMPUTING USING IMS LEARNING DESIGN

 EDUCATIONAL MODELLING IN CLOUD COMPUTING USING IMS LEARNING DESIGN

Using a System on a Programmable Chip (SOPC) is increasingly common in embedded applications. A SOCP is a circuit comprising multiple functions such as one or more processors, one or more reconfigurable areas, a signal processor DSP (Digital Signal Processor), various peripherals and memory or analog parts. These circuits are increasingly used because of their small size and reduced costs compared to the use of various circuits for performing the same function. Therefore, many hardware and software techniques must be developed to satisfy specific constraints in terms of area, performance, power consumption, etc.
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Creating a Technical Disaster Recovery Implementation Plan (TDRIP)

Creating a Technical Disaster Recovery Implementation Plan (TDRIP)

A Technical Disaster Recovery Implementation Plan (TDRIP) is a plan of the actual implementation of the hardware and software at the disaster recovery location.. Why.[r]

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Ph D  Qualifying Exam

Ph D Qualifying Exam

Summary of Virtualization • Isolation from hardware • Key component of cloud computing but not identical • Software, hardware, or hybrid implementation for virtual resource management...[r]

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Neural Networks for Location Prediction in Mobile Networks in AES Techniques

Neural Networks for Location Prediction in Mobile Networks in AES Techniques

The control and management module of reconfiguration allows choosing a correct memory program (PR) and generating a reconfiguration signal (Cf. Fig. 9). The real dynamic reconfiguration procedure of the AES is preceded by two controllers: the first one, achieved by Microblaze processor, computes the reconfiguration parameters using the available signal and the key size. This is the current state of the system. The second one computes the best parameters under input constraints, and writes these parameters in the configuration register for managing the reconfiguration process.
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Modern aspects of construction of information  microwave therapy devices

Modern aspects of construction of information microwave therapy devices

This article is devoted to presenting modern as- pects of building information microwave therapy devices. And it presents an analysis of the ex- isting problems of the organism homeostasis con- trol by means of electromagnetic radiation. The new principles of synthesis of operating influ- ences are formulated. On the basis of the ther- modynamic approach is justified as a leading role modeling the space microwave background to restore disturbed homeostasis of the organism. The general patterns of development of the path- ological process and possible mechanisms of corrective action of natural electromagnetic back- ground are described. The implementation of the approach offered by the authors to constructing device information physiotherapy allowed creat- ing high-performance hardware and software means for the prevention and treatment of a wide range of human diseases.
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Are coarse grained overlays ready for general purpose application acceleration on FPGAs?

Are coarse grained overlays ready for general purpose application acceleration on FPGAs?

Abstract—Combining processors with hardware accelerators has become a norm with systems-on-chip (SoCs) ever present in modern compute devices. Heterogeneous programmable system on chip platforms sometimes referred to as hybrid FPGAs, tightly couple general purpose processors with high performance reconfigurable fabrics, providing a more flexible alternative. We can now think of a software application with hardware accelerated portions that are reconfigured at runtime. While such ideas have been explored in the past, modern hybrid FPGAs are the first commercial platforms to enable this move to a more software oriented view, where reconfiguration enables hardware resources to be shared by multiple tasks in a bigger application. However, while the rapidly increasing logic density and more capable hard resources found in modern hybrid FPGA devices should make them widely deployable, they remain constrained within specialist application domains. This is due to both design productivity issues and a lack of suitable hardware abstraction to eliminate the need for working with platform-specific details, as server and desktop virtualization has done in a more general sense. To allow mainstream adoption of FPGA based accelerators in general purpose computing, there is a need to virtualize FPGAs and make them more accessible to application developers who are accustomed to software API abstractions and fast development cycles. In this paper, we discuss the role of overlay architectures in enabling general purpose FPGA application acceleration.
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Simulation of SHA-3 Algorithm (KECCAK) With Area Efficient Module

Simulation of SHA-3 Algorithm (KECCAK) With Area Efficient Module

A two-staged pipelined architecture of the new SHA-3 algorithm is presented. The core can operate on both one-block and multi-block messages. In this paper a two-staged pipelined architecture of the new SHA-3 (Keccak) algorithm is presented. The core can operate on both one-block and multi-block messages. Special effort has been paid and different design alternatives have been studied to derive efficient FPGA implementations in terms of throughput and throughput/area metrics. The proposed Xilinx Virtex-5, Virtex-6, and Virtex-7 FPGA technologies and achieves significant improvements compared to existing FPGA implementations. Future work include optimized FPGA implementations of the finalized SHA-3 standard.[4]
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A Security Monitoring Service for NoCs

A Security Monitoring Service for NoCs

Access rights control is performed in parallel with the pro- tocol translation, analysing OCP/IP transactions. As shown in Figure 3, information on OCP/IP signals are looked up to verify access rights. In particular, the source of the transac- tion is identified using a combination of the processor iden- tifier (MConnID) and the thread identifier (MThreadID), while MAddr provides information about the targeted mem- ory block. This information is looked up and access rights of the Load (L) and Store (S) operation for the two roles (User (U )) and Superuser (S)) of the initiator are provided as out- put of the lookup table (LUT) of the DPU. MBurstLength, which gives information about the length of the data to be transferred or received, is used to check if the dimension of the data are outside the block boundaries (upper bound). MCmd identifies type of operation (load /store) on the mem- ory address and together with information on the role of the initiator (MReqInfo) selects the desired signal. Therefore, in case access requirements are satisfied by the information present on the OCP/IP signals, a signal (TX Enable) is risen to allow NI to send packets of the transaction through the network.
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FPGA Based Data Encryption and Decryption Using Hill Cipher Technique

FPGA Based Data Encryption and Decryption Using Hill Cipher Technique

Till now, different approaches have been proposed highlighting the importance of security in the cryptology which is the science of securing particular application from unauthorized access or from getting hacked. Various researchers provides efficient software implementation in securing software applications, but there is limited amount of hardware implementation of the cryptographic algorithms and the hardware implementations which are available follows a single encryption technique and the importance of resource consumption getting neglected while we are securing the application. Developing the hardware platform using the cryptographic algorithms is not an easy task; rather it is a tedious task. So to provide the security and achieving optimization in terms of resource consumption, we have chosen RSA. For achieving the security of the large applications, we can use advance encryption algorithm, since it provides significant level of security. But during the research process, we found that in order to provide optimal level of resource utilization, we have to focus on different parameters i.e. simplicity, security, and operations involved. RSA although is very efficient and standalone algorithm which provides a great amount of security, it provides great level of security but it increases the complexity of the system. We selected Hill Cipher under RSA which is a light weight cryptographic technique, and which can effectively used for small applications since it is known for its simplicity. Some of the limitations which were encountered during the research process are, firstly neglecting the process of efficient resource consumption and its management while securing the applications, secondly single round of encryption, which can be attacked or leaked by unauthorized parties. For more security we have included stenography which helps us to hide our encrypted data into image.
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Higher Order Numerical Solution of Two Dimensional Coupled Burgers’ Equations

Higher Order Numerical Solution of Two Dimensional Coupled Burgers’ Equations

The Burgers’ equation is an important non-linear parabolic partial differential equation widely used to model several physical flow phenomena in fluid dynamics teaching and in engineering such as turbulence, boundary layer behaviour, shock wave formation and mass transport [1]. Due to its wide range of applicability, several researchers, both scientists and engineers, have been interested in studying the properties of the two-dimensional coupled Burgers’ equation (TDCBE) using various numerical techniques.

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Hardware implementation of an automatic adaptive centralized under frequency load shedding

Hardware implementation of an automatic adaptive centralized under frequency load shedding

In this implementation, the SVP represents the central processing unit and contains the load shedding algorithm described in the last chapter. The algorithm is programmed using the SVP Configurator software. The SVP is programmed to collect the measurements from all relays (PMUs), time align these measurements and use the measurements to assess the system frequency stability. Additionally, the SVP calculates the amount of power to be shed, distributes this power among the load buses according to their voltage dip, and asserts the required number of remote bits using the fast operate command to their associated relays to trip the power needed to return the frequency to a safe level.
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Implementation of Dedicated Hardware Using Encryption Technology

Implementation of Dedicated Hardware Using Encryption Technology

ABSTRACT: In this Cyber-Age where every major task, action, or operation executed in real life can be similarly executed in Virtual (E)/ Digital/ Second Life with more ease, be it banking, commerce, work, or communication; digitization has provided seamless options to operate, connect and share. Such a vast pool of ease and liberty gives birth to lack of security and added risk of losing sensitive data and IPR. There are established methods and security solutions which claim to be successful to a certain extent. And in cases where such software based or limited hardware based solutions are not satisfactory there arieses the need of a more developed and mature security solution. Dongles for hardware protection have been present for a while now, but unfortunately, most of these solutions were only effective for a short period, until these methods were circumvented and time has showed that solutions that offer full protection from this phenomenon are impossible. A hardware protection scheme based on dongles provides a Highly Secure Protection scheme. An AES algorithm is implemented on FPGA stage to improve the security of data in transmission. AES algorithms can be implemented on FPGA with a particular deciding objective to speed data taking care of and reduce time for key generation.
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Hardware Implementation of a Novel Image Compression Algorithm

Hardware Implementation of a Novel Image Compression Algorithm

in another layer; feed-forward where neurons in a layer sends output to neurons in another layer but don’t receive any feedback which makes the connection between neurons one-directional; bi- directional where there is a feedback from the neurons in the other layer when they send their output back to the first layer; hierarchical where the neurons in a layer are connected only to the neurons in the next neighboring layer; resonance-two directional connection where neurons continue to send information between layers until a certain condition is satisfied. Neural Networks can also be classified based on the connection between input and output: auto associative, input vector is same as the output. These can be used in pattern recognition, signal processing, noise filtering, etc; heteroassociative, output vector differs from the input vector.
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Compact and High Speed Hardware Implementation of CLEFIA

Compact and High Speed Hardware Implementation of CLEFIA

ABSTRACT: We know that communication is the most important parameter in everyone’s life. Generally, in the process of communication, there is one transmitter/sender and one receiver. For the purpose of security different methods have been developed by many authors. Cryptography is one of them. Basically, it is used to achieve the security in communication process. There are many methods in cryptography. Like, Advanced Encryption Standard, Clefia, RSA, DSA.Clefia is one method used in Cryptography which was developed by Sony Corporation in 2007. It is based on block cipher methodology instead of stream cipher. Different key lengths are used in Clefia like, 128 bit, 192 bit and 256 bit. This paper presents the implementation of small sized and High Speeded Hardware of Clefia.
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Hardware Implementation of LZMA Data Compression Algorithm

Hardware Implementation of LZMA Data Compression Algorithm

Data transmission, storage and processing are the integral parts of today’s information systems. Transmission and storage of huge volume of data is a critical task in spite of the advancements in the integrated circuit technology and communication. In order to store and transmit such a data as it is, requires larger memory and increased bandwidth utilization. This in turn increases the hardware and transmission cost. Hence, before storage or transmission the size of data has to be reduced without affecting the information content of the data. Among the various encoding algorithms, the Lempel Ziv Marcov chain Algorithm (LZMA) algorithm which is used in 7zip was proved to be effective in unknown byte stream compression for reliable lossless data compression. However the encoding speed of software based coder is slow compared to the arrival time of real time data. Hence hardware implementation is needed since number of instructions processed per unit time depends directly on system clock. The aim of this work is to implement the LZMA algorithm on SPARTAN 3E FPGA to design hardware encoder/decoder with reduces circuit size and cost of storage.
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Efficient Hardware Design and Implementation of AES Cryptosystem

Efficient Hardware Design and Implementation of AES Cryptosystem

We propose an efficient hardware architecture design & implementation of Advanced Encryption Standard (AES)-Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology (NIST) of United States has been widely accepted. The cryptographic algorithms can be implemented with software or built with pure hardware. However Field Programmable Gate Arrays (FPGA) implementation offers quicker solution and can be easily upgraded to incorporate any protocol changes. This contribution investigates the AES encryption and decryption cryptosystem with regard to FPGA and Very High Speed Integrated Circuit Hardware Description language (VHDL). Optimized and Synthesizable VHDL code is developed for the implementation of both 128- bit data encryption and decryption process. Xilinx ISE 8.1 software is used for simulation. Each program is tested with some of the sample vectors provided by NIST and output results are perfect with minimal delay. The throughput reaches the value of 352 Mbit/sec for both encryption and decryption process with Device XCV600 of Xilinx Virtex Family.
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