two-wire serial bus

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Two-wire Serial EEPROM AT24C512B

Two-wire Serial EEPROM AT24C512B

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other AT24Cxx devices. When the pins are hardwired, as many as eight 512K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “Device Addressing,” page 8.) A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capaci- tive coupling that may appear during customer applications, Atmel ® recommends always connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10k or less.
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A High Performance System on Chip Bus Design and Verification

A High Performance System on Chip Bus Design and Verification

SPI devices communicate in full duplex mode using Master-Slave architecture with a single master. The master device originates the frame for reading and writing. Multiple slave devices are supported through selection with individual slave select (SS) lines. Sometimes SPI is called a four-wire serial bus, contrasting with three-two-, and one- wire serial buses. The SPI may be accurately described as a synchronous serial interface, but it is different from the Synchronous Serial Interface (SSI) protocol, which is also a four-wire synchronous serial communication protocol, but employs differential signalling and provides only a single simplex communication channel.The SPI bus can operate with a single master device and with one or more slave devices. If a single slave device is used, the SS pin may be fixed to logic low if the slave permits it. Some slaves require a falling edge of the chip select signal to initiate an action; an example is the Maxim MAX1242 ADC, which starts conversion on a high-low transition. With multiple slave devices, an independent SS signal is required from the master for each slave device.
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PCA General description. 2. Features. 2-wire serial bus extender for HDMI DDC I 2 C-bus and SMBus

PCA General description. 2. Features. 2-wire serial bus extender for HDMI DDC I 2 C-bus and SMBus

overvoltage tolerant and are high-impedance when the PCA9507 is unpowered. The port B drivers with static level offset behave much like the drivers on the PCA9515 device, while the port A drivers integrate the rise time accelerator, sink more current and eliminate the static offset voltage. This results in a LOW on port B translating into a nearly 0 V LOW on port A. The static level offset design of the port B I/O drivers prevent them from being connected to another device that has rise time accelerator including the PCA9510, PCA9511, PCA9512, PCA9513, PCA9514, PCA9515, PCA9516A, PCA9517 (B-side), or PCA9518. The port A sides of two or more PCA9507s can be connected together, however, to allow a star topography with port A on the common bus, and port A can be connected directly to any other buffer with static or dynamic offset voltage. Multiple PCA9507s can be connected in series, port A to port B, with no build-up in offset voltage with only time of flight delays to consider. Rise time accelerator on port A is turned on when input threshold is above 0.3V CC(A) .
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DS1990A-F5. Serial Number ibutton TM

DS1990A-F5. Serial Number ibutton TM

The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have an open drain connection or 3-state outputs. The DS1990A is an open drain part with an internal circuit equivalent to that shown in Figure 2. The bus master can be the same equivalent circuit. If a bidirectional pin is not available, separate output and input pins can be tied together. The bus master requires a pullup resistor at the master end of the bus, with the bus master circuit equivalent to the one shown in Figure 3. The value of the pullup resistor should be approximately 5 kΩ for short line lengths. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The 1-Wire bus has a maximum data rate of 16.3k bits per second.
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Sun-3_Architecture_Manual_Ver_1.0_Jan85.pdf

Sun-3_Architecture_Manual_Ver_1.0_Jan85.pdf

the bus error register, the system enable register, the diagnostic register, and the ·,D-PROM. The 10- PROM contains a unique serial number and indicates the implementation type of the[r]

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ICM CPS 16 Schem pdf

ICM CPS 16 Schem pdf

C0UNTER/¶IMER INTERRUPT CONTROLLER CLOCK GENERATOR BUS CONTROLLER SYNC/ASYNC SERIAL CN?RL PARALLEL.. INTERFACE COMPARATOR 4 PROK TS.[r]

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Effect of NTL on Power System Losses at Industrial Load

Effect of NTL on Power System Losses at Industrial Load

As NTL cannot be computed & measured easily, but it can be estimated from preliminary results, i.e. the result of technical losses are first computed and subtracted from the total losses, with the balance as NTL. The technical losses are calculated using appropriate load flow studies using Matlab Software. The low voltage distribution systems of 11KV are not as thoroughly measured because of the costs of the added metering. This is the reason that power flow solutions are used to estimate the states at various points in the system. The conclusion is that if data about NTL loads is available to analyst only then the measurement of NTL and its effects on electrical power systems can be determined. The data is to include, either the NTL load power consumption profile comparable to the legitimate loads, being analyzed at the same time, as well as the NTL power factor, or power factor contribution. In this paper, I have considered a two-bus system with loads at both buses and either of one bus can be selected as a “slack bus” with constant voltage and phase angle necessary for analysis of the system. The extra load was simulated in a simplistic way by adding a profile of demands to the bus 2 load in the form of adding KVA values to the original demand and reducing the total power factors by subtracting a power factor “contribution” for each value of added load. The pf contributions chosen here were negative because the NTL load is assumed to be Inductive. The load profile of each load varies with time and has a different pattern over a period of 24 hours. To make the test loads more realistic they are represented as two sets of power demands with different operation schedules comparable to residential and industrial area. In the case where bus 1 is used as the slack bus, the maximum active power loss in the transmission line is around 380 watts at 15 hrs and that of reactive power loss is 400 VARs at the same time. As NTL is added at node 2 and node 1 is used as the slack node, the maximum active power loss in the transmission line is around 400 watts at 15 hrs and that of reactive power loss is 420 VARs at the same time. Thus, it may be concluded that as NTL load is added to the system, total losses will increase which further creates costs for SEBs in the form of lost revenues.
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Transport NSW TWO DOOR CITY BUS - BUS SPECIFICATION. Outer and Metropolitan Bus System Contract (O/MBSC) November 2010

Transport NSW TWO DOOR CITY BUS - BUS SPECIFICATION. Outer and Metropolitan Bus System Contract (O/MBSC) November 2010

8.11.2 The nearside exterior rear facing mirror must be a heated electrically adjusted convex mirror mounted forward of the entrance doors and visible through the swept area of the windscreen, in accordance with current standards, including those standards set out in the Henderson Report. In the event of an impact, all components must be separately replaceable and the mirror head must be mounted independently from the mounting bracket. Shear bolts are to be used to mount the mirror brackets to minimise damage to the frame in the case of an accident. The lower edge of the mirror must be no less than 2.1 metres from the ground with the Bus standing on level ground and at normal height.
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M68HC08. Microcontrollers. High Data Rate Wireless USB Optical Mouse Solution Using the MC68HC908QY4 and MC68HC908JB12. Designer Reference Manual

M68HC08. Microcontrollers. High Data Rate Wireless USB Optical Mouse Solution Using the MC68HC908QY4 and MC68HC908JB12. Designer Reference Manual

The universal serial bus (USB) is an industry-standard extension to PC architecture providing a low-cost plug-and-play solution for PC peripheral devices. It is a serial data link with a high data-transfer rate and device-control capability. Peripheral USB devices can be configured automatically when connected to a host because the USB software driver is mapped and loaded in the operating system (OS) according to the peripheral device class.

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Fixed-Abrasive Diamond Wire Saw Machining

Fixed-Abrasive Diamond Wire Saw Machining

The three types of wire saw machining of wood to be studied are shown in Figure 1.5. The first method, as shown in Figure 1.5(a), is to use a long wire, stored in two spools, to cut the wood workpiece. Fresh, uncut diamond wire can be continuously introduced during machining, which makes this type of wire saw cutting more precise, but also more expensive. This type of wire saw cutting is commonly used for wafer slicing in the semiconductor industry. For wood machining, the workpiece can move moved in two translational directions, as shown in Figure 1.6(a), or in two translational and one rotational directions, as shown in Figure 1.6(b). The other two types of wire saw machining, as shown in Figures 1.5(b) and 1.5(c), use looped continuous and reciprocal/oscillating diamond wire, respectively. The looped dia mond wire saw cutting (Figure 1.5(b)) is like the band saw but is a lot more flexible. The reciprocal/oscillating wire saw cutting (Figure 1.5(c)) could be conducted with existing scroll saw machines.
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Title: VOLTAGE REGULATION OF A GRID WITH IUPQC USING PI & FUZZY LOGIC CONTROLLER

Title: VOLTAGE REGULATION OF A GRID WITH IUPQC USING PI & FUZZY LOGIC CONTROLLER

impedances are denoted by the pairs (Rs1, Ls1) and (Rs2, Ls2). It can be seen that the two feeders supply the loads L-1 and L-2. The load L-1 is assumed to have two separate components—an unbalanced part (L-11) and a non-linear part (L-12). The currents drawn by these two loads are denoted by il1 and il2, respectively. We further assume that the load L-2 is a sensitive load that requires uninterrupted and regulated voltage. The shunt VSC (VSC-1) is connected to bus B-1 at the end of Feeder-1, while the series VSC (VSC-2) is connected at bus B-2 at the end of Feeder-2. The voltages of buses B-1 and B-2 and across the sensitive load terminal are denoted by Vt1, Vt2 , and Vl2, respectively.
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A Review on Selection of Proper Busbar Arrangement for Typical Substation (Bus Bar Scheme)

A Review on Selection of Proper Busbar Arrangement for Typical Substation (Bus Bar Scheme)

In this scheme three circuit breakers are used for controlling two circuit as shown in Fig. (I & J). Each breaker is provided with two isolators and two earth switch. It is most used schemes for high voltage switchyard. Normally, both the bus-bar are in services. This scheme is suitable for those substations which handle large amounts of power on each circuit. The scheme has been widely used in USA particularly for their EHV substations operating at 330 kV and above. It is also used in India for 420 kV systems. A fault on any bus is cleared by the opening of the associated circuit breakers without affecting continuity for supply. Its operation is simple because, all load transfer is done by the breaker is possible in this scheme. However relaying is somewhat more involved as the third breaker has to be responsive to troubles on either feeder in the correct sequence. In this scheme each breaker has to be suitable for carrying operations, which may in some cases increase the cost [3].
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SMART USB – ‘Wireless Data Transfer’ Amit Hire 1, Rahul Mamania1 , Vivek Kongari 1, Prof. Prashant Gadakh2 Prof. Ramkrushna M 2

SMART USB – ‘Wireless Data Transfer’ Amit Hire 1, Rahul Mamania1 , Vivek Kongari 1, Prof. Prashant Gadakh2 Prof. Ramkrushna M 2

Several devices have been developed to overcome the reliance of a user on a PC for transferring data among distinct storage devices. One of the recently developed similar systems had used USB host controller (VNCIL) along with microcontroller ARMLPC 2138.[1] A Pen drive is an external device which is used to store the data and also help us to move files or folders from one central processing unit to another; hence they are in addition called as USB flash drives. An USB flash drive includes flash memory, which is interfaced with integrated Universal Serial Bus (USB). USB flash drives are not fixed and rewritable, and physically much minor than a disc. Since, to copy data from one Pen drive to another pen drive, third medium is needed and pen drives are USB slave device, since USB slave devices cannot directly converse with another USB slave devices.
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Experimental Investigation of WEDM Variables on Surface Roughness of AISI D3 Die Steel By Using Two Cryogenically Treated Different Wires

Experimental Investigation of WEDM Variables on Surface Roughness of AISI D3 Die Steel By Using Two Cryogenically Treated Different Wires

The effect of varying wire mechanical tension on surface roughness is shown in Figure 4. When wire mechanical tension increases there is decrease in surface roughness. The surface roughness quality of the machined part is improved due to increase of wire tension because of reduction in its vibration. Similar results have been represented by Sharma et al. [3], who conducted experiments to optimization of process parameters of cryogenic treated D-3 in WEDM by Taguchi Approach and find that the with more increased wire tension, the surface roughness has been reduced.
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Evaluation of Bus/Bicycle andBus/Right-Turn Traffic Delays and Conflicts

Evaluation of Bus/Bicycle andBus/Right-Turn Traffic Delays and Conflicts

This research evaluates conflicts and delays caused by interactions between buses, bicycles, and right-turning vehicles. Two concerns caused by these overlapping bus, bicycle, and automobile facilities are analyzed; the first concern is the number of bus-bicycle conflicts (as a proxy for safety) and the second concern is bus delay. Video data was collected and analyzed to quantify conflicts, travel time, and delay. For every bus passing through the study site, the mixed-traffic scenario that the bus incurs was categorized as one of 72 different combinations of bus, bicycle, and automobile interactions. Video count data was weighted according to seasonal, weekly, and hourly bicycle volume data to estimate the number of annual bus-bicycle conflicts. A regression analysis was performed to identify potential sources of delays. The results indicate that each bicycle crossing the intersection after the bus (within 60 feet of the bus) contributes to bus delay. No statistically significant delay was found from the bicycles stopped in the bicycle box, bicycles stopped behind the bicycle box, bicycles that crossed the intersection before the bus, or the presence of right-turning vehicles.
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Optimization of orthodontic treatment using the Centrex System to retract anterior teeth

Optimization of orthodontic treatment using the Centrex System to retract anterior teeth

The use of prosthetic implants in orthodontic plan- ning requires from Implantology and Orthodontic professionals a varied knowledge. As in cases that are referred by implantodontists for an orthodontic prep- aration prior implants placement, as in cases referred by orthodontists for the insertion of osseointegrated implants that will work as anchorage, a great interac- tion is demanded between professionals involved, as well as a minimal knowledge of the resources of an- other specialty, at least enough to discuss the needs and possibilities involved in the case. In the first case, the mastery of orthodontic set up preparation allows the correct planning of implant positioning without the risk of making these implants prevent posterior tooth movement. In the second case, the implant type choice, the region to receive the implant, the healing period prior to the application of orthodontic force and the magnitude of that force, they are all informa- tion that should be shared between the two specialties. In the case of implants used only for anchorage, the location choice, size and even the type of head of the implant are defined by the orthodontist. These are al- ways orthodontic options, since they are directly and inseparably linked to the treatment planning and to the chosen mechanics. Thus, it is natural that the or- thodontist keeps taking for himself the responsibility of placing mini-implants in his clinical practice. This transition has been occurring gradually.
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FEATURES APPLICATIONS

FEATURES APPLICATIONS

As shown in Figure 4, the SDO pin from device #1 is con- nected to the SDI input of device #2, and is repeated for additional devices. This in turn forms a large shift regis- ter, in which gain data may be written for all PGA4311s connected to the serial bus. The length of the shift regis- ter is 32 • N bits, where N is equal to the number of PGA4311 devices included in the chain. The CS input must remain LOW for 32 • N SCLK periods, where N is the number of devices connected in the chain, in order to allow enough SCLK cycles to load all devices.

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Dynamic scheduling of message flow within 
		a distributed embedded system connected through a RS485 network

Dynamic scheduling of message flow within a distributed embedded system connected through a RS485 network

dynamic scheduling has to be effected is the worst case response expected for processing an event. When the messages are dynamically scheduled based on the priority set considering the environmental conditions, sometimes may lead to loss of worst case response time, defeating the design of the embedded system itself. The designer of an embedded system must consider the worst case response time along with the scheduling of the event processing, so the dynamic nature of the embedded system could be met. Dynamic scheduling of the message processing initiated by a master to be processed by a slave is much more complicated as the events happen randomly at distributed locations. The worst-case response times of each of the events differs greatly. Processing time of any of the message also depends on network latencies, traffic flow and congestion. In this paper, dynamic scheduling of messages to be processed by a master connected to the slaves using RS485 bus based serial communication network has been presented. The RS845 based network connects a single master and several slaves and the processing takes place in a distributed manner.
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Power System Simulation for Engineers (PSS/E): Fault Analysis

Power System Simulation for Engineers (PSS/E): Fault Analysis

2. This will open a “Build New Case” dialog box. Select the base MVA as “100” from the “Base MVA” drop down list box. Then there will be two blank spaces corresponding to Heading line 1 and Heading line 2. You may leave these text boxes blank, and Click OK. 3. This will get you to the spreadsheet interface, where you are going to build your new

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Serial Attached SCSI Host Bus Adapters Installation. CDP A Rev. A Issue: March 21, 2013

Serial Attached SCSI Host Bus Adapters Installation. CDP A Rev. A Issue: March 21, 2013

You may need to reset, or flash, your Adaptec Host Bus Adapter if it becomes inoperable or if a firmware upgrade is unsuccessful. Adaptec HBAs support a reset protocol called HDA mode flash. To locate the flash jumper on your HBA, see the illustrations in About Your Host Bus Adapter on page 14. For more information about HDA mode reset, contact your support representative.

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