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An FPGA based high speed network performance measurement for RFC 2544

An FPGA based high speed network performance measurement for RFC 2544

Aiming at the problem that existing network performance measurements have low accuracy for (Request for Comments) RFC 2544, this paper proposes a high-speed network performance measurement based on field-programmable gate array (FPGA). The active measurement method is used to generate probe data frames, and a passive measurement method is employed to count network traffic. According to the statistical laws based on throughput variation, interval stretching mechanism is used to dynamically adjust interframe gap. When our approach approaches the maximum throughput, the network performance parameters are achieved. A prototype based on NetFPGA is also implemented for evaluation. Experimental results show that our approach can be applied in high-speed network and the latency can be accurate to the nanosecond. Compared with network performance measurement using software to send probe data frames and a similar work based on FPGA, our approach can be more flexible and the evaluation data are more accurate.
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A performance model for the link-transport layer serving XTP in a high speed network

A performance model for the link-transport layer serving XTP in a high speed network

The queue length distribution observed at the MMB P-stream packet arrival instances, and the waiting time distribution and the blocking probability for the MMBP-stream are then obtained [r]

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Performance analysis of error recovery schemes in high speed network - part II

Performance analysis of error recovery schemes in high speed network - part II

A link level virtual circuit model of the link-by-link error recovery scheme is shown in. Fig(6)[r]

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Performance analysis of error recovery schemes in high speed network - part I

Performance analysis of error recovery schemes in high speed network - part I

The result shows that under a particular condition, if we keep the number of hops between the source and the destination node below a certain number, the frame relay scheme can have shor[r]

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High speed variable length FIFO for POS PHY level-3

High speed variable length FIFO for POS PHY level-3

In the Internet Protocol (IP) network architecture, Synchronous Optical Network/Synchronous Digital Hierarchy (SONET/SDH) is used to transport information such as voice, data, and video. The Packet over SONET (POS) technology supports this transport mechanism and takes advantage of the existing SONET infrastructure. Implementing the POS technology involves direct mapping of the IP layer over SONET, thus, bypassing the ATM layer. The result is an efficient utilization of bandwidth with no ATM cell header, and the elimination of overhead associated with processing ATM cells such as IP encapsulation over ATM, and segmentation size, bandwidth efficiency can be as high as 99% and re-assembly (SAR) depending on the packet. The processing of information (packets) from the source to the destination traverses through layers of functional responsibility. In each layer, the processing of packets can be done with hardware, software, or both. The Lattice POS-PHY Level 3 PHY (PL3-PHY) Layer Interface-core is a highly-configurable core that provides hardware resources for data transfers between the PHY and Link Layer devices that support the POS technology. The majority of networked applications, application layer data frames are basically split into several smaller sized packets, before transmission across the network. The receiving side can make use of the data only if it receives all (sufficiently many to decode) packets of a frame. So it is necessary that a receiver should receive all the packets of frame and that is possible only when the good-put and also through-put of the FIFO buffer should be high. The depth of the FIFO buffer memory leads to delay if the proper interfaces have not done. This discussion tells that today high speed network has interpacket dependency architecture which leads “that we collect it but not got it”. This leads us to find the new architecture for FIFO buffer for POS PHY level-3.
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High Speed and Low Power Architecture for Network Intrusion Detection System

High Speed and Low Power Architecture for Network Intrusion Detection System

The tremendous growth in the field of modern communication and network systems places de- mands on the security. As the network complexity grows, the need for the automated detection and timely alert is required to detect the abnormal activities in the network. To diagnose the sys- tem against the malicious signatures, a high speed Network Intrusion Detection System is re- quired against the attacks. In the network security applications, Bloom Filters are the key building block. The packets from the high speed link can be easily processed by Bloom Filter using state- of-art hardware based systems. As Bloom Filter and its variant Counting Bloom Filter suffer from False Positive Rate, Multi Hash Counting Bloom Filter architecture is proposed. The proposed work, constitute parallel signature detection improves the False Positive Rate, but the throughput and hardware complexity suffer. To resolve this, a Multi-Level Ranking Scheme is introduced which deduces the 13% - 16% of the power and increases the throughput to 23% - 30%. This work is best suited for signature detection in high speed network.
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Performance Evaluation of Scheduling Algorithms for 4G (LTE)

Performance Evaluation of Scheduling Algorithms for 4G (LTE)

DOI: 10.4236/cn.2018.104013 154 Communications and Network access to services that offer information on demand at a very high data commu- nication speed because it was designed to provide 3 times faster speed than 3G. It has higher data rates of about 300 Mbps peak downlink and 75 Mbps peak up- link. LTE supports scalable carrier bandwidths from 1.4 MHz to 20 MHz and supports both Frequency Division Duplex (FDD) and Time Division Duplex (TDD); thus resulted to better performance than 3G. LTE gives QoS to agencies of all sizes and people of all races including those in remote rural areas without wireless internet coverage. LTE supporting technology includes OFDM which can achieve the targeted high data rates with simpler implementation and rela- tively low cost and power efficient hardware [11]. It removes the limitations of previous wireless technology by deploying OFDMA for downlink and SC-FDMA technology for uplink. SC-FDMA is technically similar to OFDMA but it suits better for hand-held devices because it is less demanding in battery power. LTE uses MIMO technology to send data, thereby, minimizing noise effect, increase throughput, and spectrum utilization. The basic idea of MIMO is to use multiple smart antennas at the receiver end and use multiple transmitters when sending the data. LTE is the technological path followed to achieve 4G network speeds.
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Development of SCADA System for Turbocharger Testing

Development of SCADA System for Turbocharger Testing

Endurance test is carried out to check behavior of turbo when speed is continuously increasing and decreasing. This situation is seen when vehicle is traveled on road which has continuous up and down movement. In this test turbo is run at maximum speed for 5 min, then speed is decreased to lowest in just 3 min, again at low speed turbo is run for 5 min. This cycle is repeated 6 times. This test is done generally for few number of turbos to check lifetime of turbocharger in case of speed variation.

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Travelling Wave Based Fault Location Analysis for Transmission Lines

Travelling Wave Based Fault Location Analysis for Transmission Lines

In general, is considered that the methods that use information from both line ends are more robust than methods that use information from only one line end. Although in general, this statement is well founded, this paper demonstrated that is not absolutely correct since the two-end method proved to be more sensitive to the variations that the one-end method. In any case, these results are not alarming since differences between errors are very small, and also the two-end methods have better results at higher sample rates which are the most common used samples for the traveling wave fault location methods. But in some cases this needs to be clarified in order to avoid confusions.
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Establishing a valuable method of packet capture and packet analyzer tools in firewall

Establishing a valuable method of packet capture and packet analyzer tools in firewall

Deep Packet Capture has the ability to capture packet data from the data link layer on up of the ISO-OSI Reference model. This includes headers and payload. Headers include information about what is contained in the packet. The payload includes the actual content of the packet. The Deep Packet capture encompasses every packet that crosses a network segment, regardless of source, protocol or other distinguishing bits of data in the packet. Deep packet capture is the unrestricted, unfiltered, raw capture of all network packets. Our system is to implement the method of Deep Packet Capture (Bendrath, 2009; Office of the Privacy Commissioner Of Canada, n.d.; Porter, 2010).
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Network effects of intelligent speed adaptation systems

Network effects of intelligent speed adaptation systems

The finding that the effect of ISA on network travel time is more significant for the off-peak period than for the morning peak period is interesting. It is possible that, during the morning peak period, there is a lot of delay and queuing experienced on the network. Therefore vehicles will have very little opportunity to exceed speed limits, and consequently there is very little variation in the average vehicle journey duration. During the off peak period however, there are less vehicles on the network allowing vehicles to travel at higher speeds, sometimes exceeding speed limits. With the implementation of ISA, the amount of vehicle- hours exceeding the speed limits would decrease, resulting in longer journey times. Therefore during off peak times increasing penetration levels of ISA tends to increase average journey times, whereas during peak periods, the congestion automatically reduces vehicles speeds, and hence ISA has very little influence on their journey times. This is further confirmed with detailed analysis of speed distributions in Section 5.2.4.
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Influence of oxygen uptake kinetics on physical performance in youth soccer

Influence of oxygen uptake kinetics on physical performance in youth soccer

Match Average 5 min HSR (m) 68.1 ± 26.0 49.5 86.7 101.9 ± 28.5 82.1 121.6 P = 0.022 -61.9 -5.7 1.32 large very likely positive Match Average 5 min VHSR (m) 9.9 ± 5.4 4.8 15.1 20.9 ± 7.9 15.5 26.4 P = 0.004 -17.9 -4.1 1.75 large very likely positive Match Average 5 min HSR (efforts) 11.9 ± 4.5 8.7 15.1 17.7 ± 4.9 14.3 21.1 P = 0.024 -10.6 -0.9 1.36 large very likely positive Match Average 5 min VHSR (efforts) 1.8 ± 1.0 0.9 2.8 3.8 ± 1.5 2.8 4.8 P = 0.005 -3.2 -0.7 1.69 large very likely positive

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High Performance Low Delay 10T Full Adder

High Performance Low Delay 10T Full Adder

In this paper, we have proposed a high performance low power 10T full adder which gives better performance than other FAs. It shows lowest delay and power dissipation. It gets almost full swing for Sum and Carry out (for particular combinations) during operations . 10T FA gives 10.93% lower delay than 9T FA circuit and 45.50% lower delay than 8T FA circuit. Proposed 10T FA is beneficial for the higher bit adders and it can be used for any arithmetic operations.

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Real Time Hardware Software Co-Simulation Edge Map Accumulation Based Feature Extraction

Real Time Hardware Software Co-Simulation Edge Map Accumulation Based Feature Extraction

Therefore, after LFE, GFE is performed to retain only salient features. This is completed by selecting only a pre- determined percentage which is also called as the edge detecting threshold of significant edge flags out of all pixels that have larger gradient values than the rest. This type of selection is possible because convolution values are all preserved which obtained from every pixel site. The four edge maps having only the significant flags after the selection very well represent global features and we call them the “Significant Edge Maps (SEMs)”.Only the salient features in the original image are highlighted. The SEMs are used for both static image recognition and motion analysis. For static image recognition, a feature vector representation algorithm called Projected Principal Edge Distribution (PPED) or Averaged Principal-Edge Distribution (APED) is employed to transform the four directional SEMs into a single 64-dimension feature vector. For motion analysis, the four directional SEMs are merged into one MSEM.
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Study of 3G/4G Network Convergence Planning Scheme in High Speed Railway

Study of 3G/4G Network Convergence Planning Scheme in High Speed Railway

Fast moving of the high-speed railway causes the fading process of signal. The new cell should be switched quickly. It only takes seconds for high-speed trains to pass hundreds of coverage range. In this high-speed situation, it is easily to appear out-of-service and fail to selection cell etc. So the setting of the cell switch area is mainly related to the running speed of the trains, cell re-election and switch time for cells. It must be enough overlapping coverage area for two adja- cent cells to meet the needs of the switch time for terminals when fast moving.
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Institute for Prospective Technological Studies 1992 EUR 15002

Institute for Prospective Technological Studies 1992 EUR 15002

3.3.1.2 Workshop on the intercomparison of the three main European Rail Network electrical supply systems by simulation of the network requirement for three reference high speed lines 30[r]

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Chordates - Fish Classification and intro ch15

Chordates - Fish Classification and intro ch15

Lunate - (tuna) - poor acceleration and maneuvering but very low drag for very efficient high speed cruising. Heterocercal - sharks, one lobe larger (upper due to vertebral extension) [r]

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Experimental demonstration of cap transmitter using very high speed IC hardware description language (VHDL)

Experimental demonstration of cap transmitter using very high speed IC hardware description language (VHDL)

Just like OOK, Binary Phase Shift Keying (BPSK) also using symbol ‘1’ and ‘0’ to modulate the phase of the carrier. Logical ‘1’ is represented as sin ɷt while ‘0’ represented as – sin ɷt. The constellation for BPSK is assigned by different carrier phases at 180º each as shown in Figure 2.2 [12]. In the constellation diagram, I axis is refer to the in-phase carrier wave while the Q stands for Quadrature carrier. BPSK has very complex circuit at receiver due to phase shift detection.

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Numerical Simulation of Air Flow Properties around High Speed Train in Very Long Tunnel

Numerical Simulation of Air Flow Properties around High Speed Train in Very Long Tunnel

volume method. The velocity streamline, second flow at the wake flow, total pressure and the coefficient of flow resistance have been described in detail. According to the previous work, the train nose angle leads instead to a more pronounced effect in air flow properties around train body in despite of train speed and blockage ratio being known to be one of the most important parameters influencing the aerodynamics of train/tunnel system. We have confirmed:

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Piggyback Scheme over TCP in Very High Speed Wireless LANs: Review

Piggyback Scheme over TCP in Very High Speed Wireless LANs: Review

CC links in transparent (voice) mode suffer from a residual FER of 1% to 2%, after low level error recovery, despite their short frames [29]. For example, a full rate IS-95 link would segment a 1400 byte IP datagram into 68 frames. Assuming independent frame errors, the probability of a successful packet transmission is 50.49% at a FER of 1%. Frame errors are bursty than bit errors, because multiple frames are interleaved before transmission. Although this process reduces the loss rate and randomizes frame errors, thus avoiding audible speech degradation, it considerably increases processing delay because of interleaving before transmission and deinterleaving after reception. If we reduce the size of IP datagrams to reduce the packet loss probability, user data throughput also decreases because of the higher TCP/IP header overhead. TCP/IP header compression may be used over slow CC links, shrinking TCP/IP headers to 3 to 5 bytes [30]. Header compression, however, may adversely interact with TCP error recovery and link layer resets, leading to a loss of synchronization between the compressor and the decompressor, thus causing entire windows of TCP data to be dropped [31]. Although the RLP used in the nontransparent mode of GSM usually manages to recover from wireless losses before TCP timers expire, it exhibits high and widely and varying RTT values. Measurements using ping over a GSM network in San Francisco showed that 95% of the RTT values were around 600ms with a standard deviation equivalent to 20ms [32]. Our measurements with ping over GSM networks in Oulu, Helsinki, and Berlin produced similar results but with higher standard deviations. Large file transfer experiments, however, reveal that RTT can be occasionally much higher with real applications over operational networks, reaching values of up to 12 seconds. Increasing the size of the TCP Maximum Transfer Unit (MTU) not only reduces TCP/IP header overhead, thus improving bulk transfer throughput,
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