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very high-speed VLSI

A Novel Design of Low Power, High Speed VLSI for Processing Signals Using Multirate Techniques

A Novel Design of Low Power, High Speed VLSI for Processing Signals Using Multirate Techniques

... of speed at extremely fewer ...a very Last phase, component regarding Multirate polyphase Interpolator as well as Decimator provides presented with fresh designed ...

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RECENT TRENDS OF POWER DELAY FOR LOW POWER & HIGH SPEED VLSI CIRCUITS

RECENT TRENDS OF POWER DELAY FOR LOW POWER & HIGH SPEED VLSI CIRCUITS

... inlight of the fact that the development rate of the battery innovations is not all that promising. As indicated by Morre’s law semiconductor innovation will twofold in each 18 months.& at the same time gadget number ...

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DESIGN AND IMPLEMENTATION  OF HIGH SPEED VLSI ADDER USING LING EQUATIONS

DESIGN AND IMPLEMENTATION OF HIGH SPEED VLSI ADDER USING LING EQUATIONS

... 531 After simulation of two structures the timing analysis is performed on Xilinx 13.4 ISE suite. The maximum combinational delay for Ling adder is 15.384ns where as for PPCs traditional adder is 21.869ns.from the ...

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High Speed VLSI Architecture of Wallace Tree Multiplier Utilised in FIR Filter

High Speed VLSI Architecture of Wallace Tree Multiplier Utilised in FIR Filter

... The benefit of the Wallace tree is that there are only O(log n) reduction layers, and each layer has O(1) propagation delay. As making the partial products is O(1) and the final addition is O(log n), the multiplication ...

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A High Speed Vlsi Architecture For Image Deinterleaver For Compression

A High Speed Vlsi Architecture For Image Deinterleaver For Compression

... [5] A. Karagounis, A. Polyzos, B. Kotsos, and N. Assimakis, “A 90nmManchester code generator with CMOS switches running at 2.4 GHzand 5 GHz,” in Proc. 16th Int. Conf. Syst., Signals Image deinterleaverProcess.,Jun. 2009, ...

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FUZZY BASED DETECTION AND SWARM BASED AUTHENTICATED ROUTING IN MANET

FUZZY BASED DETECTION AND SWARM BASED AUTHENTICATED ROUTING IN MANET

... non-separable VLSI architecture by combining row and column processor as proposed by Mashiro et al [7] can be used for high speed VLSI implementation of lifting 2-D DWT with reduced number of ...

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Sensor-less Vector speed Control of Induction motor Drives using MRAS technique.

Sensor-less Vector speed Control of Induction motor Drives using MRAS technique.

... simplest speed estimate technique for controlling induction motor from very low to very high speed ...control speed as per ...a speed estimation algorithm which overcomes ...

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Piggyback Scheme over TCP in Very High Speed Wireless LANs: Review

Piggyback Scheme over TCP in Very High Speed Wireless LANs: Review

... CC links in transparent (voice) mode suffer from a residual FER of 1% to 2%, after low level error recovery, despite their short frames [29]. For example, a full rate IS-95 link would segment a 1400 byte IP datagram into ...

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VLSI Implementation of a Fixed Complexity Soft Output MIMO Detector for High Speed Wireless

VLSI Implementation of a Fixed Complexity Soft Output MIMO Detector for High Speed Wireless

... In both LTE and WiMAX, spatial multiplexing (SM) and transmit diversity have been adopted as the two major MIMO schemes. SM is a MIMO technique aimed at maximizing the data throughput by exploiting the degrees of freedom ...

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VLSI Architecture for Kogge- stone High Speed Addition Technique using XOR Gate

VLSI Architecture for Kogge- stone High Speed Addition Technique using XOR Gate

... The main object of this paper is to reduce the route delay and logic delay. As soon as we increase the bit for addition in kogge stone adder area will be increased. So, area and propagation delay can be reduced by the ...

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A VLSI implementation of RSD based high speed ECC processor using arithmetic operations

A VLSI implementation of RSD based high speed ECC processor using arithmetic operations

... The result of experiment demonstrates that our outline creates high throughput and power effectiveness of 44.8 mW in FPGA and 5.22 mW in ASIC. The proposed Dual field engineering encourages the design exploration ...

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VLSI design of high-speed adders for digital signal processing applications.

VLSI design of high-speed adders for digital signal processing applications.

... A simple solution to the throughput rate problem is to allow sim ul taneous execution of many tasks by multiple arithmetic units. Parallel pr ocessing with straight har dware duplication, however, may not be economical ...

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Implementation on STM-16 Frame Termination VLSI with High-Speed and Low-Power GDI Techniques

Implementation on STM-16 Frame Termination VLSI with High-Speed and Low-Power GDI Techniques

... for high-speed digital services, a nested level of four is required for each STM; that is, the lowest level of container, virtual container, administrative unit (AU), AU group, and ...The VLSI has ...

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RLC Parameter Extraction and Step Input Response Analysis of Coupled High Speed Distributed VLSI Interconnects

RLC Parameter Extraction and Step Input Response Analysis of Coupled High Speed Distributed VLSI Interconnects

... On-chip high speed VLSI interconnects, therefore, crosstalk and its effects are a serious issue in the system ...of high speed interconnects are becoming comparable with clock ...

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High Speed and Energy Efficient Carry Skip Adder Operating Under a Wide Range of Voltage Levels
L Priyanka, Mr Devireddy Venkatarami Reddy & Mr T Narasimha Rao

High Speed and Energy Efficient Carry Skip Adder Operating Under a Wide Range of Voltage Levels L Priyanka, Mr Devireddy Venkatarami Reddy & Mr T Narasimha Rao

... In this paper, given the attractive features of the CSKA structure, we have focused on reducing its delay by modifying its implementation based on the static CMOS logic. The concentration on the static CMOS originates ...

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Numerical Simulation of Air Flow Properties around High Speed Train in Very Long Tunnel

Numerical Simulation of Air Flow Properties around High Speed Train in Very Long Tunnel

... volume method. The velocity streamline, second flow at the wake flow, total pressure and the coefficient of flow resistance have been described in detail. According to the previous work, the train nose angle leads ...

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VLSI Design and Implementation of High Speed and High Throughput DADDA Multiplier
U V N S Suhitha & Mr G Ravikanth

VLSI Design and Implementation of High Speed and High Throughput DADDA Multiplier U V N S Suhitha & Mr G Ravikanth

... Finite field multipliers play a very important role in the areas of digital communication especially in the areas of cryptography, error control coding and digital signal processing. In this paper, two multipliers ...

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VLSI Implementation of 4 bit 50Gbps High Speed Pipelined ADC Architecture for I UWB Receiver

VLSI Implementation of 4 bit 50Gbps High Speed Pipelined ADC Architecture for I UWB Receiver

... The high-speed low resolution analog-to-digital converters (ADCs) become more and more important in high-speed analog interface applications such as hard disk read channel, radar, digital ...

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HIGH SPEED AND LOWER HARDWARE COMPLEXITY VLSI ARCHITECTURE FOR LIFTING BASED DISCRETE WAVELET TRANSFORM

HIGH SPEED AND LOWER HARDWARE COMPLEXITY VLSI ARCHITECTURE FOR LIFTING BASED DISCRETE WAVELET TRANSFORM

... “A high-performance and memory-efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform,” IEEE ...efficient VLSI architecture for lifting-based ...

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LOW-POWER HIGH-SPEED CIRCUIT DESIGN FOR VLSI MEMORY SYSTEMS

LOW-POWER HIGH-SPEED CIRCUIT DESIGN FOR VLSI MEMORY SYSTEMS

... some high threshold transistors called rest transistors ...a high threshold gadget is embedded in the arrangement with low threshold transistors making a rest ...

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