[PDF] Top 20 Engineered Emitters for Improved Silicon Photovoltaics
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Engineered Emitters for Improved Silicon Photovoltaics
... on photovoltaics came from the space industry in the 1960s for satellite ...of silicon integrated circuits helped reduce ...terrestrial photovoltaics. From the 1980s to the 1990s, the efficiency of ... See full document
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Silicon Nanostructure Photovoltaics
... The excellent match between the measured EQE and the absorptance for the nanowire and nanohole arrays implies that we can accurately predict the optical characteristics of such materials from bulk optical constants, at ... See full document
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Applications of Spectrally Resolved Photoluminescence in Silicon Photovoltaics
... from silicon wafers under various surface ...be improved by performing measurements at higher temperatures, rather than room temperature, due to the increasing impact of carrier profiles and surface ... See full document
163
Research and Developments in Thin-Film Silicon Photovoltaics
... film silicon photovoltaic devices, multi-junctions such as the micromorph tandem junction have to be developed, and selective light trapping into the thin solar cell is ...amorphous silicon microcrystalline ... See full document
15
Germanium-on-Silicon Strain Engineered Materials for Improved Device Performance Grown by Chemical Vapor Deposition.
... Returning to academia after ten years in the industry was a difficult and risky decision and he was very accommodating with my requests to make this transition a smooth one. I would like to thank Dr. Narayan, Dr. Cuomo, ... See full document
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Low temperature gettering in multicrystalline silicon materials for photovoltaics
... 6.4.4.1 Bottom and top wafers In the bottom and top samples with both the SiN x and I-E passivation, the behaviour is quantitatively similar. Bottom samples have a relatively low starting lifetime and relatively high ... See full document
252
Over the last 50 years, commercial silicon photovoltaics
... of silicon nanowires with radial p-n ...our improved process maintains the advantages of our previous work but also dramatically reduces surface rough- ness and improves control over the nanowire diameter ... See full document
6
Engineered Alumina / Silicon Carbide Laminated Composites
... work silicon carbide has been selected as second phase to graduate the thermal expansion coefficient of alumina due to its relatively low specific density that could allow the production of lighter components with ... See full document
169
Dislocation engineered silicon Light Emitting Diode
... Figure 3-27: Difference in distribution function (notice the tail for perfect loops). Authors assign optimum light emission to annealing temperatures varying between 975−1100°C, with an average of 1050°C and annealing ... See full document
143
Comparative study of absorption in tilted silicon nanowire arrays for photovoltaics
... further improved through tilted ...exhibit improved per- formance compared to vertical nanowires arrays over a broad range of tilt angles (from 38° to ...exhibit improved absorption over the ... See full document
6
Investigation of microcrystalline silicon emitters and DC sputtered ZnO:Al as front contact in silicon heterojunction solar cells
... Figure 5.2(b) demonstrates the variation of the VOC and the efficiency values with respect to the front ZnO:Al layer thickness. The highest efficiency is obtained for SHJ solar cells with a front electrode thickness of ... See full document
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Polycrystalline Silicon Germanium Emitters for Gain Control, With Application to SiGe HBTs
... polysilicon emitters, SiGe, SiGe HBTs, SiGe heterojunction bipolar ...has improved to such an extent that several research groups have reported values of and/or over 100 GHz [1]–[5], and the ... See full document
7
Laser Fired Aluminum Emitter for High Efficiency Silicon Photovoltaics Using Hydrogenated Amorphous Silicon and Silicon Oxide Dielectric Passivation
... induced boron-oxygen complex and thus reduction in cell efficiency; in contrast, n-type material does not suffer from this degradation [42]. The LFE cell concept facilitates the formation of an emitter in a matter of ... See full document
141
Engineered exciton diffusion length enhances device efficiency in small molecule photovoltaics
... Conclusion We investigated the problems of short L D and domain size, and enhanced them to improve OPV efficiency in two highly efficient small molecules using solvent vapour annealing. We explored the effect of a range ... See full document
9
First principles simulation of amorphous silicon bulk, interfaces, and nanowires for photovoltaics
... An improved version of the algorithm is known to generate high-quality models with a modest computation ...liquid silicon to obtain a structure of the amorphous phase 171 ...of silicon and hydrogen ... See full document
105
Nickel Silicide as a Contact and Diffusion Barrier for Copper Metallization in Silicon Photovoltaics
... a seed is formed from printing, electroplating, or by other means because they quickly thicken the gridlines, reducing series resistance, while remaining separate from the formation of the contact to silicon. ... See full document
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Silicon Microwire Photovoltaics
... 2.2.3 Single-wire solar cell model Brendan Kayes presented a quasi-analytical approach to the device physics of radial p-n junction solar cells in 2005. [20] This study has played a seminal role in the development of Si ... See full document
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Paths Towards High Efficiency Silicon Photovoltaics
... in silicon wire growth at elevated temperatures, as explored in section ...quality silicon wires at this temperature, the SiGe growths were generally more difficult to grow, either due to increased ... See full document
129
Room-temperature single-photon emitters in silicon nitride
... S15). The direct comparison of the selected PL spectra from SPEs in SiN grown on 3-m-thick and 285-nm-thick SiO 2 , respectively, as well as histograms of the wavelength distribution demonstrate the similar nature of ... See full document
8
Engineered Silicon Substrates Selector Guide
... DRIE Silicon etch options with minimum feature size 2um, on SOI up to 300um thick, trenches with aspect ratios of 20:1, large area patterns on SOI and Si wafers with exposed areas up to 65% and up to 500um through ... See full document
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