Top PDF Hardware security design from circuits to systems

Hardware security design from circuits to systems

Hardware security design from circuits to systems

are triggered by one or more rarely switching nets or a sequential combination of them, which makes activation during testing highly difficult, especially due to the increasing density of integration. The payload can have a destructive impact, e.g. modifying signals or deteriorating the circuit, or can have the purpose of leaking confidential information. Hardware Trojans which leak confidential information as their sole payload have been characterized as especially dangerous, as they minimally change the overall system behavior [88]. For instance, a hardware Trojan was shown to be capable of inferring and leaking the secret key in an advanced encryption standard (AES) circuit implementation without directly probing it [89]. Even secure storage of the cipher key, e.g. in a physically unclonable function (PUF) which is highly volatile against physical modification or probing, would not prevent this indirect information leakage. An example Trojan which indirectly leaks the cipher key by tapping into the net containing the round key in the ‘Add Round Key’ phase of AES is shown in Figure 5.1.a). Ideally, the confidential information, in this case the cipher key, is dispersed over multiple operations as shown in Figure 5.1.b). As the information contained in the cipher key and all dependent instructions and values such as the round key is dispersed through multiple paths, the device does not expose a single point of vulnerability anymore and, therefore, is much less likely to be successfully infiltrated by a hardware Trojan. Although Trojans inserted in the design or manufacturing stage should ideally be detectable in pre- or post-silicon verification and testing respectively, the
Show more

148 Read more

Lower bounds: from circuits to QBF proof systems

Lower bounds: from circuits to QBF proof systems

A. From propositional to QBF: new QBF proof systems. We exhibit a general method how to transform a propositional proof system to a QBF proof system. Our method is both conceptually simple and elegant. Starting from a propositional proof system P comprised of axioms and rules, we design a system P + ∀red for closed prenex QBFs (Definition 3.1). Throughout the proof, the quantifier prefix is fixed, and lines in the system P + ∀red are conceptually the same as lines in P , i.e. clauses in resolution, circuits from C in C-Frege, or inequalities in cutting planes. Our new system P + ∀red uses all the rules from P, and can apply those on arbitrary lines, irrespective of whether the variables are existentially or universally quantified. To make the system complete, we introduce a ∀red rule that allows to replace universal variables by simple Herbrand functions, which can be represented as lines in P . The link to Herbrand functions provides a clear semantic meaning for the ∀ red rule, resulting in a natural and robust system P + ∀red.
Show more

29 Read more

A Methodology for the Design of Microwave Systems and Circuits Using an Evolutionary Algorithm

A Methodology for the Design of Microwave Systems and Circuits Using an Evolutionary Algorithm

Abstract—This work presents a methodology for the development of microwave systems and circuits. Starting from the system decomposition, the proposed method is aimed at estimates the requirements of each component of the system taking into account the effects on the whole system and the interactions with the others microwave components. The obtained requirements are then used to design or optimize each device with standard design methodologies or CAD tools. The problem is recast as an optimization one by defining a suitable cost function able to take into account the interactions between all the components of the system. The cost function is then minimized with an evolutionary optimization technique, namely the particle swarm optimizer. The obtained preliminary results, concerning the design of a broad-band bidirectional amplifier, demonstrate the potentialities of the proposed approach.
Show more

13 Read more

Large Scale Complex Systems: From Antenna Circuits to Power Grids

Large Scale Complex Systems: From Antenna Circuits to Power Grids

This work proposes a new type of smart antenna system, referred to as passively controllable smart (PCS) antenna, which can be used as an efficient transmission device in wireless sensor networks. A PCS antenna system is accompanied by a tunable passive controller whose adjustment at every signal transmission generates a possibly unique radiation pattern. To reduce co-channel interference and optimize the transmitted power, this antenna can be programmed to transmit data in a desired direction in such a way that no signal is transmitted (to the far field) at many pre-specified undesired directions. In particular, it is shown that a set of voltage signals can be sent to different directions if and only if a linear matrix inequality problem is feasible. Later on, this result is exploited to prove that a set of voltages can be generated at the far field if and only if the associated vector of voltages belongs to an ellipsoidal region. This region can be computed at a very high speed online by the transmitting sensor node in order to program its PCS antenna for sending data towards an intended node in such a way that a zero signal is sent in several undesired directions. The PCS antenna proposed here is made of only one active element and its programming has a low complexity. These two properties differentiate a PCS antenna from the existing smart antennas, and make it possible to implement a PCS antenna on a cheap, small-sized, low-power silicon chip.
Show more

235 Read more

Design of Analog CMOS Circuits for Batteryless Implantable Telemetry Systems

Design of Analog CMOS Circuits for Batteryless Implantable Telemetry Systems

A wireless biomedical telemetry system is a device that collects biomedical signal measure- ments and transmits data through wireless RF communication. Testing medical treatments often involves experimentation on small laboratory animals, such as genetically modified mice and rats. Using batteries as a power source results in many practical issues, such as increased size of the implant and limited operating lifetime. Wireless power harvesting for implantable biomedi- cal devices removes the need for batteries integrated into the implant. This will reduce device size and remove the need for surgical replacement due to battery depletion. Resonant inductive coupling achieves wireless power transfer in a manner modelled by a step down transformer. With this methodology, power harvesting for an implantable device is realized with the use of a large primary coil external to the subject, and a smaller secondary coil integrated into the implant. The signal received from the secondary coil must be regulated to provide a stable direct current (DC) power supply, which will be used to power the electronics in the implantable de- vice. The focus of this work is on development of an electronic front–end for wireless powering of an implantable biomedical device. The energy harvesting front–end circuit is comprised of a rectifier, LDO regulator, and a temperature insensitive voltage reference. Physical design of the front–end circuit is developed in 0.13 µm CMOS technology with careful attention to analog layout issues. Post–layout simulation results are presented for each sub–block as well as the full front–end structure. The LDO regulator operates with supply voltages in the range of 1V to 1.5V with quiescent current of 10.5 µA The complete power receiver front–end has a power conversion e ffi ciency of up to 29%.
Show more

103 Read more

Consolidating  Security  Notions  in  Hardware  Masking

Consolidating Security Notions in Hardware Masking

[HT16] Michael Hutter and Michael Tunstall. Constant-time higher-order Boolean- to-arithmetic masking. IACR Cryptology ePrint Archive, 2016:1023, 2016. [ISW03] Yuval Ishai, Amit Sahai, and David A. Wagner. Private circuits: Securing hardware against probing attacks. In Dan Boneh, editor, Advances in Cryp- tology - CRYPTO 2003, 23rd Annual International Cryptology Conference, Santa Barbara, California, USA, August 17-21, 2003, Proceedings, volume 2729 of Lecture Notes in Computer Science, pages 463–481. Springer, 2003. [JKP03] Burton S. Kaliski Jr., Çetin Kaya Koç, and Christof Paar, editors. Crypto- graphic Hardware and Embedded Systems - CHES 2002, 4th International Workshop, Redwood Shores, CA, USA, August 13-15, 2002, Revised Papers,
Show more

29 Read more

Using Java to Design and Test Hardware Circuits Over a Classroom Network

Using Java to Design and Test Hardware Circuits Over a Classroom Network

Working with circuits when there is a short time to cover the material is difficult. Hardware breadboards only allow focus on smaller circuits; any kind of coverage of circuits as they fit into a larger structure (e.g., the construction of a CPU) usually requires simulation of some sort. Many simulation systems are very complicated (e.g., PSPICE [1]) or focus on precise realism and analysis. Other simulation environments are focused on a particular hardware platform and, while useful for teaching, do not lend themselves to rapid learning and component sharing. We decided that we needed to develop our own circuit simulation system, perhaps based on an existing environment.
Show more

5 Read more

Design and Architecture of Hardware-based Random Function Security Primitives

Design and Architecture of Hardware-based Random Function Security Primitives

will no longer be operating within optimal parameters. To alleviate this problem, one must adjust the system to maintain its performance and functionality in an optimal range (e.g. tuning the system). In other words, the purpose of tuning a system is to customize its behavior in an optimal operation manner. The act of tuning will most definitely add circuit overhead to the PCB, the design, and the development of a given system. The advantage of this is that once the op- eration of a circuit has been tuned within some threshold, this removes the need for, and errors caused by, human interaction and environmental changes. The adaptive methodology of tuning circuits allows for more robust systems. Pandey et al. [74] examined several works making use of adaptive and self-tuning control (STC) approaches for load-frequency control in power systems, showing their ef- fectiveness in improving system performance. In 2015, research work was done [6] to implement generalized frequency domain controller tuning for voltage sourced converter (VSC) systems, showing that active variations in power can be damped within tolerable levels.
Show more

201 Read more

Hardware design and CAD for processor-based logic emulation systems.

Hardware design and CAD for processor-based logic emulation systems.

2. DPGA[25]: stands for Dynamically Program m able G ate A rray and was developed a t th e MIT Artificial Intelligence Laboratory. D PG A is an F PG A w ith four configuration contexts and each context is stored in its configuration memory. The contexts are switched under external control. The basic logic element is in fact a 4-input LUT combined w ith a single flipflop th a t is shared among all contexts. D PG A is a general purpose hardw are development platform th a t was not necessarily optimized for logic em ulation purposes. For logic em ulation purposes, a netlist m ust be partitioned into sub-circuits th a t each will fit into single context. T he D PG A m ust contain sufficient memory capacity to store the results of each context (combinational logic blocks+flipflops) as well as configuration bitstream . C urrent em bodim ent of D PG A fails to provide such provisions, therefore, roughly speaking, it is not suitable for logic emulation. O n th e other hand if the tim e delay caused by context switching is significantly higher th an em ulation tim e of one logic slice, th en em ulation speed will be drastically reduced to unac­ ceptable levels. However, D PG A dem onstrate how time-m ultiplexing technique could result in b ette r logic ca p a city u tiliza tio n in F P G A s.
Show more

128 Read more

Towards Embedded System Hardware Security Design and Analysis

Towards Embedded System Hardware Security Design and Analysis

Common cryptographic systems, such as Advanced Encryption Standard (AES) and Data Encryption Standard (DES), have been hacked by scan-based attacks [57], [58], [3], [5]. In [3], scan chains were utilized to retrieve the key of the DES algorithm. Because of the iterative computation of DES, different parts of the user key is carried by each round of key generation. If attackers can switch scan chains between the nor- mal and test modes, by putting carefully prepared plaintext contents (i.e., plaintexts with only one bit difference) into the DES circuit, they are able to determine the user key from scan outputs during the internal rounds. Similarly, scan-based attacks can be carried out against AES ciphers as well [5]. It takes advantage of the basic differential properties of AES as a block cipher, where if a pair of plaintext inputs are only one bit different in the least significant bit of any byte, the possibility of output difference of first round is restricted. Moreover, only a few of these output pairs can be generated by a unique pair of S-box inputs. Hence, attackers can switch between the test and normal modes of scan chains in order to observe the first round response for input pairs with designated differences. The overall computational complexity for retrieving the user key is greatly reduced with the acquired internal state informa- tion. Furthermore, the need of switching between the scan and test modes can also be avoided once attackers figure out the mapping between the input bit to the scan cell [4].
Show more

137 Read more

Modeling and Design of Asynchronous Circuits

Modeling and Design of Asynchronous Circuits

When designing data paths for synchronous systems, a designer trades off clock rate against complexity of each processing stage so as to ensure that data are valid at the beginning and end of each clock period. The issues of data validity and completion detection of processing are handled very differently in asynchronous design, either by careful matching of delays or by special data coding schemes. Both approaches allow processing to take place at the natural frequency of the task, rather than under the worst-case conditions required by a global clocking scheme. Unfortunately, the performance of asynchronous systems is hard to predict; care must be taken to avoid bottlenecks. In this Special Issue, one paper [13] provides
Show more

9 Read more

Analog hardware security and hardware authentication

Analog hardware security and hardware authentication

axis which intersects with the quiescent point of the circuit is enough to guarantee to find all the stationary modes of operation. In second order dynamic systems, the appearance of the orbit is predictable. However, for higher order dynamic systems, the shape or appearance of the stationary periodical orbits is usually unimaginable. Even, the one-dimensional linear scan would be adequate for determining the presence or absence of Trojan operating modes in second order dynamic circuits, a high dimensional transient simulation scan is usually necessary for other systems that have multiple energy storage elements, if the phase plane is more than two dimensions. In this section, the sequential transient simulation with one dimensional initial condition scanning method is presented. The one-dimensional initial condition scan can be any random angle to the axis, but in this section, the one-dimensional initial condition scan is along the axis for easy implementation and explanation. It is efficient to find all existing stationary modes in second order dynamic systems and also valid on some circuits with higher order dimensions. Two examples will be given to demonstrate this method of identifying Trojan dynamic modes. One is an analog circuit using the popular Wien-bridge oscillator architecture and the second is an injection-locked ring-oscillator that can be used for clock generation in digital systems.
Show more

177 Read more

On Design of Memristive Amplifier Circuits

On Design of Memristive Amplifier Circuits

memristors like quantised conductance devices and MOSFET. The results of the simulations showed the im- proved performance of the common source, common drain and differential amplifiers in terms of the area, power and THD when implemented using the memristor elements instead of the conventional resistors or pseudo-resis- tors. The idea of controlling the resistance of the amplifier in an integrated circuit and the use of memristor ele- ment in the amplifier design is the new ideas suggested in this work. The proposed approach can have a wide- spread use in the implementation of analog amplifier circuits in sensory signal processing circuits, analog neu- romorphic networks, and memory driven circuits and systems.
Show more

10 Read more

A Hardware Trojan for Cryptographic Countermeasure Circuits

A Hardware Trojan for Cryptographic Countermeasure Circuits

Abstract— A hardware Trojan is a malicious hardware virus that is incorporated into the LSI circuit by a designer as the LSI is being designed or manufactured. When the hardware Trojan trigger is not actuated, the LSI acts according to its own specifications. Therefore, a hardware Trojan is difficult to detect using general functional tests. Unlike a software Trojan, a hardware Trojan is difficult to identify from the outside and it cannot be removed since it is physically incorporated into the LSI. In previous studies that focus on hardware Trojan, a hardware Trojan is often incorporated into a cryptographic circuit. Since confidential information is generally protected using a cryptographic circuit, important information can be stolen by attacking that cryptographic circuit. In general, circuits that contain measures to protect them from illegal attacks (hereinafter referred to as countermeasure circuits) are often used as cryptographic circuits. In the future, fault attacks will be the most threatening type of illegal attacks. Measures that use back-check circuits are said to be most effective against fault attacks. Since circuits that do not contain measures against illegal attacks (hereinafter referred to as non-countermeasure circuits) were used as Trojan circuits in previous studies, Trojan circuits are difficult to directly use as countermeasure circuits in systems that use back-check circuits. In order to examine a type of hardware Trojan that will have important implications for the future security of circuits, the present study develops a new hardware Trojan for countermeasure circuits that can be used against fault attacks and verifies the validity of the new hardware Trojan.
Show more

5 Read more

Verification Techniques for Hardware Security

Verification Techniques for Hardware Security

Chapter 4 provides general guidelines for identifying dangerous unspecified func- tionality for an important class of design: on-chip bus systems [25]. Regardless of the specific bus topology and protocol, bus behavior is never fully specified, meaning there exist cycles/conditions where some bus signals are irrelevant, and ignored by the verification effort. Chapter 4 presents a general model for creating a covert Trojan com- munication channel between SoC components by altering existing on-chip bus signals only when they are unspecified and demonstrates how a Trojan channel can be inserted undetected in several widely used standard bus protocols such as AMBA AXI4 and APB. To illustrate how a Trojan channel can give an attacker a powerful foothold in a complex system, a Trojan channel is inserted in an SoC design running a multi-user Linux OS. An on-chip memory (OCM) is available to all users, but access is managed by the kernel to ensure memory isolation and privacy. The channel allows an unprivileged attacker running software on the system to access root-user memory transactions.
Show more

146 Read more

Security enhancement for A5/1 without losing hardware efficiency in future mobile systems

Security enhancement for A5/1 without losing hardware efficiency in future mobile systems

In the improved version of A5/1, the size of the chip was the same (Figure 4) since only one AND gate was added to the original design (Figure 1). However, the minimum clock cycle period and the maximum speed of the modified version were 42.0ns and 23.8MHz respectively. The delay in the minimum clock period and the maximum speed of the chip was also expected once the digital logic was increased with the key setup routine and the new clock control mechanism. The total delay, as shown in Figure 4c, is very small and it does not exceed GSM specifications where 228 bits must be generated within a time slot duration (i.e. 0.6ms).
Show more

8 Read more

Design for Test and Hardware Security Utilizing Tester Authentication Techniques

Design for Test and Hardware Security Utilizing Tester Authentication Techniques

The small feature sizes resulted in a substantial increase in the operating frequency of integrated circuits [1]. However, shrinking feature sizes and increasing the number of transistor on a single chip can increase the chance of defects. Considering sub-nanometer technology, defects may occur in manufacturing process that can lead to a faulty transistor or an interconnect wire. Manufacturing defects of ICs are inevitable as it requires a single transistor or interconnect to break down the functionality of the entire chip or at least prevent the system from proper operation at the desired frequency. There is factor known as Part Per Million (PPM) which indicate the quality of the ICs launched to the market. PPM indicates how many ICs out of one million are faulty. In general, a PPM of 50 is considered acceptable for commercial applications. For certain applications such as military projects, this rate much lower and falls below 4 PPM. Thus, it is highly required to test VLSI devices at different stages of device production Fig. 2.
Show more

76 Read more

Hardware and Security: Vulnerabilities and Solutions

Hardware and Security: Vulnerabilities and Solutions

12.2.1. Testing for Trojan Circuits One approach to Trojan circuit detection is to look for additions and modifications to an IC in a laboratory setting prior to deploying the final product. Lab-based detection augments the test phase of the supply chain with silicon design authentication, which verifies that an IC con- tains only the designer’s intended functionality and nothing else [ 6 ]. Silicon design authentica- tion is difficult due to increasing IC complex- ity, shrinking feature sizes, rarity of conditions for activating malicious logic, and lack of knowl- edge about what functionality has been added to the IC. Testing cannot capture the behavior of added functionality, so an IC could contain all of the intended functionality while having extra malicious logic that might not be activated or detected by tests. Detection by physical inspec- tion is insufficient due to the complexity and size of modern ICs. Destructive approaches are too costly and cannot be applied to every IC. Detection based on physical characteristics of the IC are imprecise because fabrication introduces physical variations that increase as ICs shrink. Two promising directions that are active areas for research in the area of Trojan circuit detec- tion at the silicon design authentication step are side-channel analysis and Trojan activation.
Show more

28 Read more

Design Guidance: Building Security Systems

Design Guidance: Building Security Systems

Interior doors requiring standard mortise locks should be provided with VonDuprin, CorbinRusswin, or Best hardware. The appropriate 24VDC power supply shall be provided within 50 feet of the door. The supply is to be located in an electrical or telephone closet where available, or may be located in an accessible location above the finished ceiling if necessary. The supply must be fed from an emergency power source. Electric strikes are discouraged because of poor security and reliability. Power Transfer

23 Read more

Robust and Energy Efficient Hardware-Oriented Security for IoT Systems and Applications

Robust and Energy Efficient Hardware-Oriented Security for IoT Systems and Applications

Lastly, in the third part, we propose two applications that could greatly benefit from our proposed designs and techniques introduced in the first two parts. We first present an ultra lightweight onboard anomaly detection mechanism that has excellent potential to accurately detect suspicious voltage and temperature changes in Chapter 7. By actively monitoring sta- bility variations of onboard analog PUFs, our design could perform flexible, fine-grained chip monitoring service while reducing 63% of area and 13% of power compared to sensor-based Xilinx System Monitor. Lastly, we investigated the well-known problem of key management in IoT systems in Chapter 8. We propose to use multistage interconnected PUF (MIPUF) to assist the protection of key management system at both software and hardware level. Our experimental result indicates that our design provides physical protection when compared to Elliptic-Curve Cryptography (ECC) based solutions and reduces global energy consumption by 47.33%.
Show more

186 Read more

Show all 10000 documents...