Top PDF Signal generation and processing in high-frequency / high-speed silicon-based integrated circuits

Signal generation and processing in high-frequency / high-speed silicon-based integrated circuits

Signal generation and processing in high-frequency / high-speed silicon-based integrated circuits

This results in a 1000 km dispersion limit in the previous OC-48 case. However, it is evident that the dispersion limit decrease with R 2 b from (4.3), which means it shrinks to 1/16 for every generation of fiber-optic systems, whose bit-rate increases by 4 times every generation. For example, the same fiber network has a dispersion limit of less than 70 km for OC-192 (10 Gb/s), and about 4 km for OC-768 (40 Gb/s). Therefore, CD has a major impact on long-haul fiber-optic systems. Since the introduction of erbium-doped fiber amplifiers, fiber-optic systems began shifting to 1.56 µm transmission window, in which erbium-doped amplifiers are more effective than in the 1.3 µm transmission window. This makes CD more problematic since most conventional fibers were designed to have minimum CD in the latter. Polarization mode dispersion (PMD) [85][84] occurs because of the velocity difference between the two polarization modes in single-mode fibers, which can be caused by fiber asymmetry, fiber bending, temperature variation, etc. PMD is a random process and can only be describe using a statistical model [86]. PMD is proportional to the square of the bit-rate and square root of the distance, and is usually given in ps/ √ km, typically 0.1∼0.5 ps/ √ km. For fiber-optic networks operating below 10 Gb/s, PMD effect is usually smaller than that of CD. However, it becomes more problematic as the data rate further increases.
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An integrated nonlinear optical loop mirror in silicon photonics for all-optical signal processing

An integrated nonlinear optical loop mirror in silicon photonics for all-optical signal processing

The nonlinear optical loop mirror (NOLM) has been studied for several decades and has attracted considerable attention for applications in high data rate optical com- munications and all-optical signal processing. The majority of NOLM research has focused on silica fiber-based implementations. While various fiber designs have been considered to increase the nonlinearity and manage dispersion, several meters to hundreds of meters of fiber are still required. On the other hand, there is increas- ing interest in developing photonic integrated circuits for realizing signal processing functions. In this paper, we realize the first-ever passive integrated NOLM in sili- con photonics and demonstrate its application for all-optical signal processing. In particular, we show wavelength conversion of 10 Gb/s return-to-zero on-off keying (RZ-OOK) signals over a wavelength range of 30 nm with error-free operation and a power penalty of less than 2.5 dB, we achieve error-free nonreturn to zero (NRZ)- to-RZ modulation format conversion at 10 Gb/s also with a power penalty of less than 2.8 dB, and we obtain error-free all-optical time-division demultiplexing of a 40 Gb/s RZ-OOK data signal into its 10 Gb/s tributary channels with a maximum power penalty of 3.5 dB. © 2018 Author(s). All article content, except where oth- erwise noted, is licensed under a Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/). https://doi.org/10.1063/1.5013618
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Study and Performance Analysis of High Frequency and High Speed Operational Amplifier

Study and Performance Analysis of High Frequency and High Speed Operational Amplifier

Over the last few years, the electronics industry has exploded. The largest segment of total worldwide sales is dominated by the MOS market. Composed primarily of memory, micro and logic sales, the total combined MOS revenue contributed approx 75% of total worldwide sales, illustrating the strength of CMOS technology [1]. CMOS technology continues to mature with minimum feature sizes now. Due to relatively simple circuit configurations and flexibility of design, CMOS technology has an edge over NMOS technology and is gaining rapid acceptance as the future technology for linear analog integrated circuits, especially in the telecommunication field. Operational amplifiers (usually referred to as OPAMPs) are key elements in analog processing systems. OPAMP can be said to be the main bottleneck in an analog circuit. Ideally they perform the function of a voltage controlled current source, with an infinite voltage gain. Operational amplifiers are an integral part of many analog and mixed- signal systems. OPAMPs with vastly different levels of complexity are used to comprehend functions ranging from dc bias generation to high-speed amplification or filtering. The design of OPAMPs continues to pose a challenge as the supply voltage and transistor channel lengths scale down with each generation of CMOS technologies [2].
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A Review on Low Power Compressors for High Speed Arithmetic Circuits

A Review on Low Power Compressors for High Speed Arithmetic Circuits

In [11], all schematic simulations are performed on Tanner EDA tool version 12.6 at 45nm technology with input voltage ranging from 0.4 V to 1.0 V in steps of 0.1 V. Both the designs are analysed in terms of power consumption and power-delay product at varying input voltages, frequencies and temperatures. The results shows that the 4-2 compressor using proposed 8T full adder has better temperature sustainability which remains constant over large range of temperature than 4-2 compressor using existing 8T full adder. The proposed design shows 92% and 99% improvement in terms of power consumption and PDP in comparison to existing design. Hence, it proves itself to be a better option for low power devices and complex systems. In [12], all pre-layout and post-layout simulations have been performed on Tanner EDA tool version 12.6 at 45nm technology with input voltage ranging from 0.6V to 1V in steps of 0.1V. The proposed design shows 57-81% improvement with varying input voltage, 54-65% with varying temperature and 39-54% with varying frequency in term of PDP in comparison to existing design. Hence, the 2x2 array multiplier based on proposed XNOR-XOR cell has been proved to be a better option for low power complex system design.
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Performance Analysis of High Speed Domino CMOS Logic Circuits

Performance Analysis of High Speed Domino CMOS Logic Circuits

with higher complication forces us to enhance the performance, area, efficiency and practicality of arithmetic logic circuits. Several efforts are targeted on the development of adder styles [4]. Since the utilization of carry look-ahead principle for high-speed arithmetic units, one in all, the challenges in VLSI processor style these days is structured for constructing CLA circuits, exactly for the 8-bit circuits while not limiting the purposeful flexibility. A coffee power high performance FTL circuit technique is projected in [5] for reducing power dissipation and decreasing propagation delay in domino logic. The low power FTL dynamic logic is achieved with the help of feed through dynamic CMOS logic structure [6]. Wang, Tsai [7] used the 8-bit CLA victimization- the dual-Vt domino logic blocks that are organized in a very PLA- like manner and synchronously triggered. It is enforced on chemical element to verify the facility reduction also because of the preservation of high speeds [8]. Proposed an 8-bit pipelined CLA victimization- the dual- Green Mountain State domino logic blocks to scale back the facility dissipation. Dual-Vt Domino Logic Circuits foreseen for reducing sub-threshold discharge current in domino logic circuits is projected in [9]. Sleep switch twin threshold voltage domino logic with reduced sub-threshold logic gate compound discharge current is projected and tried in [10]. The high speed arithmetic circuit obtained victimization FTL logic in [11]. Normally, domino CMOS logic is widely employed in high performance integrated circuits. It reduces the device count and chemical element space, and improves performance in comparison to the quality totally complementary static CMOS logic [12].
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Adiabatic Logic Circuits for Low Power,  High Speed Applications

Adiabatic Logic Circuits for Low Power, High Speed Applications

Since the last few decades, the electronics industry has been growing enormously due to integrated circuit technology. Now, we have come a long way from the single transistor era of 1958 to ULSI (Ultra Large Scale Integration) which support the fabrication of more than fifty million transistors over a single chip. The increased use of portable electronics devices has made power dissipation an important design parameter in modern electronics. Portable devices that work using a battery have limited energy supplies and thus have a lifespan that are constrained by their power consumption. Until now, power consumption was not the greatest concern because of the availability of large packages and cooling techniques that have the capability of dissipating the generated heat. However, due to continuously increasing density as well as the size of the chips in the system might cause difficulty in providing adequate cooling and hence, add significant cost to the system. That is why we need a circuitry which can reduce power dissipation even if a number of components are integrated over a single chip. Our objective is to reduce the power dissipation in digital CMOS VLSI circuits.
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Radial Displacement Extraction Method of BLIM based on High Frequency Signal Injection

Radial Displacement Extraction Method of BLIM based on High Frequency Signal Injection

To achieve the radial displacement observation of bearingless induction motor (BLIM), a displacement extraction method based on high frequency signal injection is presented. According to the variation principle of the mutual inductance between torque and suspension windings, by injecting a high frequency voltage to torque winding, the induced high frequency current signal in suspension winding is detected; then the radial displacement is extracted by demodulation. Simulation results show that the radial displacement can be effectively extracted, the BLIM can operate stably under the conditions of none displacement sensor.
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TRANSFORMER DESIGN GUI APPLICATION FOR HIGH FREQUENCY ELECTRICAL CIRCUITS

TRANSFORMER DESIGN GUI APPLICATION FOR HIGH FREQUENCY ELECTRICAL CIRCUITS

The application is a GUI based application that is created using JAVA-programming language, including concepts of SWINGS, AWT. The application is created on NetBeans IDE which made our task easier because of its user friendly interface and coding options. Finally, the output of the application was recorded in MySQL database which was connected to the application using the JDBC-ODBC driver.importjava.sql.*;

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A High Speed Robust Easily Cascaded Penta Mtj-Based Combinational and Sequential Circuits

A High Speed Robust Easily Cascaded Penta Mtj-Based Combinational and Sequential Circuits

Fig 2 shows the block diagram for logic in memory. It mainly includes into three parts.1.PCSA for sensing the difference between two 2.penta MTJ logic .3.PCSA is used to sense the difference between two states of resistance and it is dynamic logic ckt.4.it has two phases one is pre phase and another is evaluation phase. In the discharging of branches occurred depends on the o/p mode of returns resistances. Relative resistance ate lower resistance that discharge the output node capacitance to cut off the other branch. Basically, low resistance branch pulls down towards the ground and high resistance branch pulls up towards the vdd. Now in proposed structures there are low reading disturbance and dynamic sensing capabilities which reduce the delay power. Both writing path and pre charging in penta MTJ are separated by nMOS transistors MN2 and MN3. There are two limitations of PCSA that unbound the proposed logic gates.
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FPGA Implementation of a High Speed Matrix Multiplier for Use in Signal and Image Processing Applications

FPGA Implementation of a High Speed Matrix Multiplier for Use in Signal and Image Processing Applications

Systolic system consists of a set interconnected cells, each capable of performing some simple operation. Systolic approach can speed up a compute-bound computation in a relatively simple and inexpensive manner [12]. A systolic array in particular, is illustrated below. (We achieve higher computation throughput without increasing memory bandwidth).

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Crosstalk Interconnect Noise Optimization Technique Using Wire Spacing and Sizing for High Speed Integrated Circuits

Crosstalk Interconnect Noise Optimization Technique Using Wire Spacing and Sizing for High Speed Integrated Circuits

Abstract—Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 3GHz has caused crosstalk noise to become a serious problem that degrades the performance and reliability of high speed integrated circuits. This paper presents an efficient method for computing the capacitive crosstalk in sub-quarter micron VLSI circuits. In this paper, we present a complete analytical crosstalk noise model which incorporates all physical properties including victim and aggressor drivers, distributed RC characteristics of interconnects and coupling locations in both victim and aggressor lines. We present closed-form analytical expressions for peak noise and noise width to estimate on-chip crosstalk noise and also shown that crosstalk can be minimized by wire spacing and wire sizing optimization technique. These models are verified for various deep submicron technologies.
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DATA SHEET. TDA bit high-speed analog-to-digital converter INTEGRATED CIRCUITS Aug 26

DATA SHEET. TDA bit high-speed analog-to-digital converter INTEGRATED CIRCUITS Aug 26

The TDA8703 is an 8-bit high-speed Analog-to-Digital Converter (ADC) for video and other applications. It converts the analog input signal into 8-bit binary-coded digital words at a maximum sampling rate of 40 MHz. All digital inputs and outputs are TTL compatible, although a low-level AC clock input signal is allowed.

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DESIGN OF 64-BIT ALU USING VEDIC MATHEMATICS FOR HIGH SPEED SIGNAL PROCESSING RELEVANCE’S

DESIGN OF 64-BIT ALU USING VEDIC MATHEMATICS FOR HIGH SPEED SIGNAL PROCESSING RELEVANCE’S

Nowadays due to the growing demand for improving processor performance in handling the complex algorithms and multi functioning making the all processor cores are going to integrate on single chip. Even though the burden on the processor is not reducing. In order to reduce this we should provide the coprocessor for supporting operations done by main processor, these coprocessors will perform numeric operation like addition, multiplication, DSP application, etc. The speed of the processor will depend on the speed of the coprocessors. Vedic mathematics is the ancient type of mathematics which are having unique technique of 16 formulas to find solution of various application in the fast way. Here we are designing an ALU which was based on these maths using Verilog HDL and synthesised in Xilinx ISE 13.2, found that it’s having enhanced performance.
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High-speed transparent switch via frequency upconversion

High-speed transparent switch via frequency upconversion

A horizontally polarized signal is transmitted through a polarizing beam splitter and a QWP which rotates the signal into right-circular polarization. The signal is then split using a 50/50 beam splitter, so one half travels clockwise around the interferometer and the other half travels counter-clockwise. The escort applies a π -phase shift to the (co-propagating) clockwise beam, while the counter-clockwise beam is counter-propagating to the escort and therefore not af- fected. If the escort is off, the signal (now left-circular after having seen three reflections) exits the interferometer along the path which it came. The HWP rotates it to vertical polarization and it reflects off the PBS, passes through a HWP to become horizontally polarized again, and leaves the switch through Port 1. If the escort is on, the interference condition on the beam splitter is reversed, and the signal leaves though Port 2 after the final QWP rotates it back to horizontal polarization. To upconvert both the horizontal and vertical components of the cir- cularly polarized light inside of the interferometer, we require two upconversion crystals with perpendicular optic axes, and a diagonally polarized escort. Since both paths (clockwise and counter-clockwise) have to pass though the same crystals with each polarization, there is no need for any bias control, since it is self-stabilizing: any index changed caused by temperature instability will identically affect both paths. This yields a bias-free switching configuration that only needs to be temperature stabilized to the level required for phase-matching.
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Signal Integrity Analysis of High Speed Interconnects in SATA Connector

Signal Integrity Analysis of High Speed Interconnects in SATA Connector

SI ensures the signals to reach their destination in good condition. Also application of SI finds solutions for the following critics such as Crosstalk: Unnecessary coupling which may be capacitive or inductive. Secondly, Power distribution: It directly influences the high speed system performance and reliability. It should offer reduced noise power in PCB including Vcc and ground. Finally, Reflection, Overshoot, Ringing: Undesired characteristics such as Isochronous Switching Noise, impedance mismatch, discontinuous interconnection [1].

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SOI for Frequency Synthesis in RF Integrated Circuits

SOI for Frequency Synthesis in RF Integrated Circuits

As explained in the introduction, one of the main purposes of the first SOI fabrication was to verify the functionality of the devices and circuits that will be used in the later versions of the frequency synthesizer. To this end, various single MOS devices and ring oscillators were fabricated. The results were collected and analyzed provided insight into the abilities of SOI to be used in RF frequency synthesis. One of the primary goals of this characterization of devices and circuits was to determine the effects of device layout technique on the characteristics of the device and the circuits that utilize them. Device layout technique (explained in Appendix 1) is not modeled for in the device libraries, which adds risk to the fabrication of a chip. It is important to find out before fabrication of the final SOI receiver if (for example) one layout technique is more reliable than another or if one layout technique is more sensitive to process variations or has a large un-modeled parasitic capacitance. These factors will greatly affect the matching or performance of the device. The devices and oscillators that were fabricated for this purpose were not randomly chosen. Each oscillator was designed for a possible implementation in a future RF frequency synthesizer. Different device sizing and layout techniques were used for each oscillator to test different concepts. The size and layout technique of the individual devices was also carefully to resemble the devices that were used in the oscillators.
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Parallel and distributed processing in high speed traffic monitoring

Parallel and distributed processing in high speed traffic monitoring

filter list g_listFilters. Each filter may access a packet in the shared PBuf by one of the following two ways: (1) directly getting the next available packet in PBuf by reading X up to the global W position, increasing its local R position in PBuf, and eventually marking, into a local index buffer (IBuf), the packets found interesting for other filters such as higher level applications, or (2) by getting the next packet pointed by the local IBuf being marked as interested beforehand by other filters. The latter option is useful when using a chain of filters. The main purpose of the BMS is to capture all packets that are considered ‘interesting’ and hand a reference to these packets to the appropriate applications. The idea behind FFPF is simple. Users start applications in user-space (see App.1, App.n in Figure 4.2) that load filters. A filter is an application oriented on packet processing only and it runs at low levels such as OS kernels, or even in hardware. An application may use the processing results of one or more loaded filters by way of a shared memory that is called MBuf and is located inside each filter. Moreover, an application may use a filter as a ‘pre-processor’ so as to offload part of its heavy packet processing job onto lower processing levels. In this case, the application retrieves from its loaded filter indexes to the packets needed for a more exhaustive processing than the filter was able to perform.
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Comparative Performance Analysis of XOR - XNOR Function Based High - Speed CMOS Full Adder Circuits

Comparative Performance Analysis of XOR - XNOR Function Based High - Speed CMOS Full Adder Circuits

Some different logic styles have been used in the past times for design of the full-adder cells[5]-[19] and those techniques are used in this paper. Although they are used for producing similar function and the way of producing transistor count and intermediate nodes are varied. Different logic styles have different advantages such as the size, power dissipation, speed and the wiring complexity of the circuit. Different logic styles have different performance aspects. The propagation delay of a circuit is determined by the number of inversion levels, number of transistors in series, the transistor sizes or channel widths and the intra cell wiring capacitances. The size of the circuit depends on the number of transistors and their sizes and also on wiring complexity of the circuit. In order to get switching point to half of V DD proper sizing should have to be done [1]-[4].
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High-voltage (100 V) Chipfilm™ single-crystal silicon LDMOS transistor for integrated driver circuits in flexible displays

High-voltage (100 V) Chipfilm™ single-crystal silicon LDMOS transistor for integrated driver circuits in flexible displays

Integration of organic, a-Si or poly-Si based transistors on flexible substrates can be achieved through large-area fab- rication processes (Bock, 2005; Troccoli et al., 2006). An integrated source and gate driver chip using a-Si transistors has already been reported in Venugopal and Allee (2007). The low mobility of carriers in organic/a-Si/poly-Si based transistors, however, makes them unsuitable for high per- formance systems. Crystalline silicon transistors are better suited for efficient systems but the high processing tempera- tures required for their fabrication prevent from direct fabri- cation on flexible substrates. A solution comes from transfer- ring pre-fabricated thin-film single-crystal silicon transistors onto flexible substrates (Li et al., 2006). Good resistance to fatigue and mechanical flexibility of pre-fabricated single- crystalline silicon MOSFETs on organic substrates has been reported in Li et al. (2006). But, most of the research work has focused on low-voltage single-crystal MOSFETs. The design of a thin-film high-voltage MOS (HVMOS) structure in single-crystalline silicon for flexible applications has not seen much attention yet due to unavailability of a suitable thin-chip technology.
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HIGH SPEED INTEGRATED SIGNALING SYSTEM FOR UNDERGROUND MINES

HIGH SPEED INTEGRATED SIGNALING SYSTEM FOR UNDERGROUND MINES

All most every underground mine is exposed to a number of risks - exposure to fire, roof falls or explosions tearing down wires, power failure or battery failure. So, underground mines mainly rely on alarm systems, such as stench gas, audible or visual alarms, pager phones, telephones, and messengers to warn miners of fire or other emergencies. These systems are often slow, unreliable, and limited in mine coverage. Meanwhile, many well-known research and commercial institutes have established many communication signaling systems: Through-the-Wire (TTW), Through-the-Earth (TTE), and Through-the-Air (TTE) etc. Coal mines are particularly unique environment for radio signals. Stopping or roof falls halt or impede conventional radio signal propagation. It is also believed that ionized air resulting from a mine fire could be a problem. In this paper we have developed a simple, cost effective, high speed integrated circuit designing to cope with the failing of alarming systems inside the mine. Single receiver may not be sufficient, as signal may be lost in between. So, we monitored signals, received by different receivers, situated at different places, inside the mine to ensure more safety. This system includes the application of high speed data acquisition, processing and decision making circuits.
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