Top PDF UVM Verification of an I2C Master Core

UVM Verification of an I2C Master Core

UVM Verification of an I2C Master Core

A UVM agent comprises of the sequencer, driver and the monitor of an interface. Multiple agents could be used to drive multiple interfaces, and they are all connected to the test-bench through the environment component. A UVM agent could be active or passive. Active agents include a driver and have the ability to drive signals, but passive agents only have the monitor and cannot drive pins. Even though a passive agent consists of the monitor only, it is vital to maintaining the level of abstraction that UVM promises and to maintain its structure by having all agents in the environment and not sub-components like monitors by themselves. By default, the agent is considered active, but this could be changed using the set() method of the UVM configuration database.
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Title: Development of Verification Environment for I2C Controller Using System Verilog and UVM

Title: Development of Verification Environment for I2C Controller Using System Verilog and UVM

I2C provides the serial cmmunication through SCL and SDA lines, where address and data are in synchronizaation with the SCL through SDA. SDA is a single data line which have the multiple states through which Address and Data is transmitted from Master to Salve. Data through SDA is transmitted with the following stages as shown in Figure 2.

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IJCSMC, Vol. 7, Issue. 6, June 2018, pg.64 – 69 An Efficient Design and Verification of I2C Master Core

IJCSMC, Vol. 7, Issue. 6, June 2018, pg.64 – 69 An Efficient Design and Verification of I2C Master Core

Every byte on the SDA line must be eight bits long. There is no limit for transfer of data over the number of bytes that can be transmitted. At transmission each byte must be followed by an Acknowledgement bit. With the Most Significant Bit (MSB) the data is transferred first . If a slave cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL low(0) to set the master into a wait state. Data transfer then continues when the slave is ready for another byte of data and releases clock line SCL.
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UVM Verification of an SPI Master Core

UVM Verification of an SPI Master Core

determines the sampling edge of send and receive signal. These two flags should have opposite values to each other since the SPI read input and write output takes place at the same single buffer in a shift register fashion. The master also configures its divider register and slave select register. Once all SPI registers are initially set up, then go flag of the control signal is asserted, which starts the transfer. The testbench uses the flag transfer in progress to synchronize driver and monitor respective forever loop part. Finally as given in Figure. 5.4 after 32 clock cycles, the transfer in progress signal is de-asserted and thus informs the end of communication for the WISHBONE interface to collect the data.
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AMBA 3 AHB LITE PROTOCOL Verification through an Efficient and Reusable Environment with an Optimum Assertion and Functional and Code Coverage in UVM

AMBA 3 AHB LITE PROTOCOL Verification through an Efficient and Reusable Environment with an Optimum Assertion and Functional and Code Coverage in UVM

It is one of the components that is used while creating a VIP. The driver requests for signals or data transactions from the sequencer. These transactions are then processed in the run phase and then sent to the DUT via an interface for verifying it. Any basic driver that we create is extended from the base class named as uvm_driver which is a parameterized class with REQ (Request) and RES (Response) as its two parameters. These parameters are of type sequence_item which is in fact a transaction. Here, we may also include pipelining where a number of parallel stages are considered. At first, we declare a virtual interface which is used for communicating with the design under verification, and then other phases are included such as the run_phase et. al.
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Design and Verification of a Pipelined Advanced Encryption Standard (AES) Encryption Algorithm with a 256-bit Cipher Key Using the UVM Methodology

Design and Verification of a Pipelined Advanced Encryption Standard (AES) Encryption Algorithm with a 256-bit Cipher Key Using the UVM Methodology

the DUT. There is an interaction between the sequencer and the driver as the sequencer sends packets of data which are known as transactions. The driver translates the data packets into signals which are fed to the DUT. The DUT can only identify the data coming from the interface. The data which is coming from the interface must be encapsulated for verification of the stimulus. The driver converts transactions to signals, another block named as driver_out performs the exact opposite operation of the driver. The monitor observes the interaction between the driver and the DUT and recovers the transaction. It also helps in comparing the results fo the DUT with the reference model. In this paper, the reference model is a C-model which is compiled and tested. It simulates the DUT at a high level of abstraction.
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Physical Design Implementation of I2C Bus Master Controller
Panthnagi Saidulu & N Nirmala Devi

Physical Design Implementation of I2C Bus Master Controller Panthnagi Saidulu & N Nirmala Devi

The I2C bus is a true multimaster bus that allows more than one master to be connected on it. If two or more masters simultaneously try to control the bus, a clock synchronization procedure determines the bus clock. Because of the wired-AND connection of the I2C signals a high to low transition affects all devices connected to thebus. Therefore a high to low transition on the SCL line causes all concerned devices to count off their low period. Once a device clock has gone low it will hold the SCL line in that state until the clock high state is reached. Due to the wired-AND connection the SCL line will therefore be held low by the device with the lon- gest low period, and held high by the device with the shortest high period.
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Design and Simulation of I2C protocol

Design and Simulation of I2C protocol

The functional description of I2C master has to be described in the Verilog HDL. That is called design module . The test bench program has to be developed to test the design module. The test bench gives the input to the design module & verifies the outputs. The test bench has to be written in such way to check the design module in all possible conditions. Verilog simulator tool is used to verify the design functioning(Simulation). Normally, a standard communication protocol consists of four parts: A. START signal generation

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Verification of AXI IP Core(Protocol) using System Verilog

Verification of AXI IP Core(Protocol) using System Verilog

that this paper does not involve Designing of AXI VIP Core, for the verification one needs its Design Specification Sheet to understand the working of the design so that it can be simulated in the Advanced Verification tools. Advance Extensible Interface (AXI) is using more in todays industry due to frequency and performance operations in the absence of complicated bridges. Actual AHB and APB interfaces are additionally good with AXI . We use AXI for multiple tasks it is not possible in the other protocol but it is possible in AXI because it consists of five different channels write address and information channels and dependent on the transaction ID. AXI supports burst based transfer. The AXI protocol has been designed using the system Verilog and Universal Verification Methodology (UVM) we verified it .The five channels of AXI as write address, write data, write response, read address, read data channels are observed in verification. With respect to AXI convention verification environment is created and distinct test cases will be passed by randomization. The AXI protocol design can be verified by using Questa sim tool and assertions and functional coverage has been obtained.
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USING I2C WITH PICAXE

USING I2C WITH PICAXE

The IC that controls the bus is called the Master, and is often a microcontroller – in this article a PICAXE-18X microcontroller will be used as the master device. The other ICs connected to the bus are called Slaves. There can be more than one slave on the bus, as long as each slave has been configured to have a unique ‘slave address’ so that it can be uniquely identified on the bus. In theory there are up to about 112 different addresses available, but most practical applications would generally have between 1 and 10 slave ICs.

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Design and verification of low speed 
		peripheral subsystem supporting protocols like SPI, I2C and UART

Design and verification of low speed peripheral subsystem supporting protocols like SPI, I2C and UART

The communication between modules are very important, each and every system includes some microcontroller core intelligence control etc. For example RAM EEPROM (or) data converters. Now a day’s interface is the heart of the system performance, on the cases of Intellectual property macro cell is the key source of design mode, and can able to produce chip. In order to attain an error free communication, each and every soc must linked properly in an efficient manner. Generally SOC uses peripheral subsystem in order to connect with external chips, the protocols which used to form subsystem are categorized into two types one is high speed communication protocol and other is low speed communication protocols. Here we are using low speed communication protocols, because low speed communication protocols leads to low power consumption. The SPI, I 2 C and UART are low speed communication protocols. They all together forms Low speed peripheral sub system in order to connect with external chips. In this work, design and verification of low speed peripheral subsystem is presented.
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Design and Verification of PHY Interface for PCIe Gen 3 0 and USB Gen 3 1 using UVM Methodology

Design and Verification of PHY Interface for PCIe Gen 3 0 and USB Gen 3 1 using UVM Methodology

(PCI) was developed in the early 90’s. The standard followed earlier was IBM’s advance Technology bus (AT), usually referred as Industry Standard Architecture Bus (ISA), IBM’s Microchannel Architecture Bus (MCA), EISA (Extended Industry Standard Architecture) and VESA (Video Electronics Standard Association). Eventually PCI became a standard peripheral bus. After few years, PCI-X (Extended) was developed followed by PCI-X 2.0. The speed ceiling and the high pin count turned the interest from parallel to serial bus model. PCIe (Peripheral Component Interconnect express) is of the third generation and supports servers, systems and mobile devices. PCIe incorporates a layered architecture consisting transaction layer, data link layer and the physical layer. It also owes much to its antecedents, PCI and PCI-X. The PHY (Physical Layer) consists of two sub-blocks logical and electrical which supports duplex communication. Logical sub block has MAC (Media Access Control), PCS (Physical Code Sublayer) and the electrical sub block has PMA (Physical Media Attachment Layer). In this thesis, the work includes, design and verification of several blocks of physical layer for PCI Express and USB. The RTL is modelled in Verilog and the same is verified in UVM (Universal Verification Methodology) environment using Questasim 10.0c from Mentor Graphics.
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Functional Verification of an ALU Core applying the Constrained Random approach

Functional Verification of an ALU Core applying the Constrained Random approach

Verification requires a lot of planning to be successful, it is important to know where to allocate the resources and what the critical parts of the design are. For this purpose the ASIC design specification is used to produce a list of features and modes that need to be tested. This list of features is then turned into a conformance verification plan (CVP)[5] by specifying testcases that exercise and test that specific feature or function [3]. These testcases focus on specific functionality, which is why they are sometimes referred to as directed tests. A device is said to conform with the specification if it passes all the tests. These tests verify top-level features, since the device is treated as a black-box. A testcase is a part of the testbench, it is an application usually written in the same language as the behavioral model. It runs as one or several processes using the generators and monitors of the testbench to stimulate the design and check for the expected behavior. The result of the simulation run of the test case is passed or failed, but a lot more information is stored for debugging purposes [1]. It is important for the testcase to be able to produce a
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IMPLEMENTATION OF I2C PROTOCOL USING FPGA

IMPLEMENTATION OF I2C PROTOCOL USING FPGA

InI2C protocol, only master can involve in arbitration. Slaves are not involved in arbitration. Master initiate transfer only and only when bus is idle. Two masters may initiate a START condition within the minimum hold time of the I2C bus START condition for which gives in a valid START condition on it. Arbitration is needed to check which master will complete their transmission as early as possible. There is no data lost in it. The advantage is that two master can complete its transmission without causing any hazard or error. Arbitration procedure keeps sending pattern bit by bit. When the SCL is gone high it will also verify SDA level for which is sent. For the first time a master try to initiates or generate a HIGH period, but that will be detecting the SDA level also gone LOW, the master knows that it will be lost the arbitration procedure and turns off its SDA output driver. Another master goes to finish their entire transaction.
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Implementation of I2C Using ARM9 Controller

Implementation of I2C Using ARM9 Controller

Embedded system design is mainly for making and managing communication between various bus interfaces and attaching multiple systems with different interfacing protocols to a main processor with high speed and low power consumption. ARM968E-S is a high performance; low power consumption microcontroller running at frequencies up to 125 MHz [4] . Embedded systems mainly uses serial communication to communicate with peripherals. I 2 C is a simple structured serial communication protocol, it gives excellent speed compared to other protocols. I 2 C uses only two wires for communication serial data line (SDA), serial clock line (SCL), so less number of wires required for connections and provides communication without data loss [2] . I 2 C bus supports for multiple masters and slaves. In this paper one master and two slaves are connected.
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Design of CAN Transmitter with an I2C Interface

Design of CAN Transmitter with an I2C Interface

The transmitter can be sure that the data was read by the receiver without any error only when the receiver acknowledges the reception. If the data packet and acknowledgement packet are sent separately, there is always a doubt whether the error was in receiving data or the acknowledgement packet, forcing the transmitter to resend the data. So, acknowledgement is often a part of the data packet itself, only that it is not originated by the transmitter but by the receiver. In I2C, the acknowledge-phase handshaking is described. The transmitter releases the SDA line (making it high), clock pulse is generated by the master, the receiver must pulls down the SDA line if there is no error, if there was error in reception, receiver leaves SDA line high, receiver maintains SDA line status till the clock goes low. When a slave-receiver doesn‟t acknowledge the slave address, the data line must be left high by the slave. The master can then generate a STOP condition to abort the transfer. If a slave- receiver does acknowledge the slave address but, sometime later in the transfer cannot receive any more data bytes, the master must again abort the transfer. This is indicated by the slave generating the not acknowledge on the first byte to follow. The slave leaves the data line high and the master generates the STOP condition. If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not generating an acknowledgement on the last byte that was clocked out of the slave. The slave- transmitter must release the data line to allow the master to generate a STOP or repeated START condition.
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A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems

A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems

Schranzhofer et al. published a series of three papers [112–114] during 2010 and 2011 based on the superblock model. In this model each task is represented by a sequence of superblocks, which may have branches and loops within them. The task set is assumed to be periodic and all execution on a core is assumed to be described by a sequence of superblocks (i.e. an oline static cyclic schedule). The irst paper [112] considers TDMA bus arbitration. The second paper [113] provides worst-case completion time analysis for the superblocks and hence a schedulability test. It covers three models: (i) arbitrary memory accesses anywhere in the superblocks, (ii) dedicated phases where accesses only occur at the start and end of each superblock, and (iii) a hybrid where most accesses are in the acquisition and replication phases, but some accesses can take place in the intervening execution phase. The conclusion is that the dedicated model improves schedulability due to less contention. The third paper [114] extends the approach to an adaptive bus arbiter with both static and dynamic segments. The method uses a dynamic programming technique to compute the minimum amount of execution of a superblock which must have taken place to reach a particular frame in the arbitration schedule, considering the interference due to requests from tasks executing on other cores. The task ΩCRTs are then computed from this information.
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Master of Divinity Degree Program Core Courses

Master of Divinity Degree Program Core Courses

Biblical Courses 9 Credits Historical Courses 6 Credits Theological Courses 6 Credits Arts of Ministry Courses 6 Credits Field Education 6 Credits World Religions 3 Credit[r]

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Design and Implementation of Serial Port Communication by Using I2C Master Controller
B  Kanniram & Dr  D  Nageshwar Rao

Design and Implementation of Serial Port Communication by Using I2C Master Controller B Kanniram & Dr D Nageshwar Rao

I2C is a two wire, bidirectional serial bus that provides effective data communication between two devices. I2C bus supports many devices and each device is rec- ognized by its unique address. In Fig -1 data_in and addr_in are the 8 bit address given as an input. Clk and reset are the input lines used to International confer- ence on Communication and Signal Processing initiate the bus controller process. The R/ w signal is given as an input to indicate whether master or slave acts as a transmitter in the data transmission.The physical I2C bus consists of just two wires, called SCL and SDA. SCL is the clock line. It is used to synchronize all data trans- fers over the I2C bus. SDA is the data line. The SCL and SDA lines are connected to all devices on the I2C bus. As both SCL and SDA lines are “open drain” drivers they are pulled up using pull up resistors .The I2C bus is said to be idle when both SCL and SDA are at logic 1 level. When the master (controller) wishes to transmit data to a slave (DS1307) it begins by issuing a start se- quence on the I2C bus, which is a high to low transition on the SDA line while the SCL line is high as shown in Fig – 2(a).The bus is considered to be busy after the START condition.
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Analysis and Verification of Core Factors in Radio Wave Propagation Loss

Analysis and Verification of Core Factors in Radio Wave Propagation Loss

Abstract. Radio wave propagation prediction can calculate the radio frequency link parameters such as field strength coverage and reception of power, which is an important foundation of electromagnetic compatibility (EMC) analysis and frequency coordination. This paper reviews the advances in the research of radio wave propagation by the International Telecommunication Union (ITU) and the International Radio Science Consortium (USRI), analyzes the core influencing factors related to the propagation of radio waves, including the propagation environment and the propagation model used in the calculation which EMC analysis system has been verified. The related content can provide reference for electromagnetic compatibility analysis and the border coordination.
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