Top PDF Wireless Interconnects for Intra-chip & Inter-chip Transmission

Wireless Interconnects for Intra-chip & Inter-chip Transmission

Wireless Interconnects for Intra-chip & Inter-chip Transmission

With the emergence of Internet of Things and information revolution, the demand of high performance computing systems is increasing. The copper interconnects inside the computing chips have evolved into a sophisticated network of interconnects known as Network on Chip (NoC) comprising of routers, switches, repeaters, just like computer networks. When network on chip is implemented on a large scale like in Multicore Multichip (MCMC) systems for High Performance Computing (HPC) systems, length of interconnects increases and so are the problems like power dissipation, interconnect delays, clock synchronization and electrical noise. In this thesis, wireless interconnects are chosen as the substitute for wired copper interconnects. Wireless interconnects offer easy integration with CMOS fabrication and chip packaging. Using wireless interconnects working at unlicensed mm-wave band (57-64GHz), high data rate of Gbps can be achieved.
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A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band

A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band

antenna. Therefore, on-off keying (OOK) based modulation is inherently adopted via the graphene based antenna structures as electrical pulses cause emission while an absence of a pulse does not. The characterization of the graphene based antenna array has been analyzed with different configurations in terms of power consumption and the area overhead [19]. The path loss of wireless communication with such antennas increases with the distance. Therefore, it is necessary to increase the antenna gain to compensate the high path loss problem with increasing distance for wireless communication. The antenna gains can be increased by using the array of graphene structures to create constructive interference patterns creating high directional gains. The radiation pattern of graphene based antenna arrays could be changed by turning off the first and the fourth row of a 4x4 array as shown in [19]. Due to this pattern, a gain of 10dB can be achieved with an efficiency of 89.14% while operating at 1.05 THz [19]. This is in deep contrast with any other type of antenna arrays which requires phase shifters. The high gain makes the antenna array highly directional which would support our architecture that requires directional wireless links enabling the toroidal folding based interconnection fabric. Even though the graphene antenna array will require multiple elements each element is only a few hundred microns in dimension (equal to λ/2 of the THz carrier) due to the high resonant frequency in the range of THz bands. This enables antenna arrays with 16 elements to be only a few hundred square microns which can decrease further with increase in carrier frequencies. This enables low area overheads by using these antenna arrays enabling the use of multiple antenna arrays in each chip.
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Design, Fault Modeling and Testing Of a Fully Integrated Low Noise Amplifier (LNA) in 45 nm CMOS Technology for Inter and Intra-Chip Wireless Interconnects

Design, Fault Modeling and Testing Of a Fully Integrated Low Noise Amplifier (LNA) in 45 nm CMOS Technology for Inter and Intra-Chip Wireless Interconnects

30 4.2 shows the circuit topology of the proposed low-power LNA based on a two stage Common Source (CS) design. Both LNA stages are chosen to be inductive source degeneration to obtain better thermal noise performance [15]. We specifically choose a two- stage CS configuration as both the Common Gate (CG) and Resistive feedback based topologies suffer from noise figure degradation due to the occurrence of noisy resistances in the signal path. Moreover, cascode structures, which are used commonly in low- frequency design for their high gains, are not suitable for the high frequency application. This is because the parasitic capacitances in the cascode transistors become dominant at higher frequencies, which reduces the inter stage impedance and hence, overall gain.
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Design Trade-offs for reliable On-Chip Wireless Interconnects in NoC Platforms

Design Trade-offs for reliable On-Chip Wireless Interconnects in NoC Platforms

Since the transceivers send data simultaneously, at the each receiver, the wirelessly transmitted CDMA bits from different transmitters may arrive in or out of synchronization. This is because data transmission happens in a distributed manner, thus making impossible to have all transmitters synchronized with all receivers. The ensuing difference in clock phases between the received CDMA streams results in loss of orthogonality between the different Walsh codes. This loss of orthogonality increases the interference at the receivers and the bit error rate (BER). This section studies this effect, leading to the calculation of the worst case BER in the proposed system. The analysis follows the work in [34] that studied CDMA for standard radio communication devices. Here, we summarize the study for completeness of presentation and adapted where necessary to the particularities of CDMA applied to an on-chip scenario.
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RAICON: ROUTING ARBITRATION FOR INTER/INTRA CHIP OPTICAL NETWORK

RAICON: ROUTING ARBITRATION FOR INTER/INTRA CHIP OPTICAL NETWORK

In RAICON’s inter-chip network, the number of data bus channels is based on the number of routers present in the top level router. Each data bus channel is composed of a on-chip silicon waveguide, a polymer waveguide embedded on PCB board, and optical connectors which connect on-chip waveguides with on-board waveguides. The bus channel presented here is considered to be a bidirectional and half-duplex, that means at a time either one transmission can be made not two way communication at a same time. If we consider there are 64 cores in the fat tree then it requires only 16 data bus for communication N o r m a l l y intra-chip network and optical data bus channels are connected by means of an interface switch as said in architecture. The interface switch is designed with MRs and waveguides. Data signals can be sent to the bus in either direction depending on which MR is powered on. A important feature of the designed optical data bus is that a single data channel can be used by multiple chips simultaneously. Single data channel can be divided into multiple sections using the unidirectional property of optical signals by the interface switch, and each section can operate independently. The distributed priority arbitration can utilize this feature to reduce data collisions and improve performance.
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Power Control And Inter Symbol Interference Of Optical – Wireless Link At Chip Level

Power Control And Inter Symbol Interference Of Optical – Wireless Link At Chip Level

Abstract: The optical communication has developed as a practical solution to a high-speed transmission systems owing to the higher bandwidth of its encompassing greater data rates. With this study, the performance analysis of simple correlator as well as chip level detector in OCDMA- optical code division multiple access wireless systems for uplink is actually suggested. We check out the overall performance in 2 various situations of (ISI) being negligible and also the ISI degrading the receiver efficiency. Use of advanced modulation formats which could support higher data rates with easier spreader and receiver designs is actually among the appealing resolution to develop the spectrally effective high velocity optical transmission links. This particular method additionally motivates the scientists as well as style engineers to further examine the skills of various modulation platforms.
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ANTENNA-ON-CHIP FOR WIRELESS APPLICATIONS: MODELLING AND SIMULATION ANALYSIS

ANTENNA-ON-CHIP FOR WIRELESS APPLICATIONS: MODELLING AND SIMULATION ANALYSIS

On-chip antennas are tiny surface mount devices designed to provide inter and intra-chip wireless communication or for short range of air transmission. The typical on-chip antenna integrated with analog and digital circuitry on the same wafer finds applications in wireless LAN, GPS receiver, Bluetooth and cellular transceivers [1]. Earlier, antennas have to be interfaced with chip circuit using bond wires (off-chip). An on-chip antenna fabrication avoids the requirement of bond wires or off the chip components. Thus the on-chip antenna fabrication provides a robust solution in smaller form factors [2]. Furthermore monolithic fabrication of the antenna with RF electronics reduces power losses and parasitic effect compared to integration of discrete components. To achieve antenna integration within a single chip, different solutions have been suggested [3-4-5]. Silicon substrate allows the antenna coupling on a chip with RF electronics. Antenna integration with silicon has been demonstrated in [6-7]. However, most of them are either bulky or having narrow bandwidth. In this work copper nanofilm is modeled instead of bulk copper as antenna radiating element. There are two advantages by employing copper nanofilm, first, the density of antenna decreases, and second, improvement in impedance bandwidth due to high surface resistivity of nanofilm. The increase in high surface resistivity increases bandwidth. To our knowledge, for the first time we are modeling an on-chip nanofilm antenna using coplanar waveguide (CPW) proximity coupled antenna through simulation to decrease the density of antenna, enhancing the bandwidth and increasing return loss.
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Dynamic Voltage and Frequency Scaling for Wireless Network-on-Chip

Dynamic Voltage and Frequency Scaling for Wireless Network-on-Chip

the number of interconnects. As shown in [30] irregular networks of size 64, 128 and 256 cores require 4, 6 and 9 layers for deadlock-free routing. Each layer is considered to have a single VC reserved. The mesh architecture is considered to have 4 VCs in each input and output port. Each VC has a buffer depth of 2 flits. A uniform random spatial distribution of traffic is used for the all experiments. All the NoC components are driven with a 2.5GHz clock. All simulations are performed for ten thousand cycles allowing for transients to settle in the first few thousand cycles. If the wireline links are long enough to take more than 1 clock cycle for transmission of a flit they are pipelined by insertion of FIFO buffers such that between any two stages it is possible to transfer an entire flit in 1 clock cycle. The on-chip zig-zag antennas are able to provide a bandwidth of 16GHz around a center frequency of 60GHz [3] while the transceivers [23] are able to sustain a maximum data rate of 6Gbps. All the wireless switches are equipped with the same transceivers. We have considered a flit size of 32 bits and a packet size of 64 flits.
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An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links

An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links

It can be observed from the figure that the packet energy increases significantly for the I/O based architectures when the system size is scaled up, while that of the wireless architectures do not increase drastically. This is due to the same fact, as described in the previous section, that the wireline system involves multihop interchip communication. Also, the I/O module is connected to only a single corner switch in each chip, and so, is prone to congestion at this switch. As the number of chips increases, the percentage of interchip traffic also increases which implies that a much larger number of packets need to use the interchip I/O interconnections. This creates a bottleneck at the I/O modules and causes a drastic decrease in bandwidth per core and hence an increase in the buffering energy at those modules. Furthermore, this I/O interconnection is considered to be a switch based architecture instead of a shared bus in order to enable concurrent communication
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An Enhanced Inter/Intra-Chip Optical Network for Chip Multiprocessors

An Enhanced Inter/Intra-Chip Optical Network for Chip Multiprocessors

3) Network Protocols: Inter-chip communications require both the intra-chip and inter-chip networks, and are managed collaboratively by the network controllers. When a processor core wants to start a communication with another core on a different chip, it first sends a request to the network controller through a concentrator, which is the same as an intra-chip communication. After receiving the request, the network controller will broadcast it to the network controller on the destination chip. The source and destination network controllers will simultaneously start to reserve an on-chip up- link path and down-link path respectively. They will use the same deterministic routing algorithm as for intra-chip commu- nications. Network controllers will broadcast successful path reservations on the control bus. When both the on-chip up- link and down-link paths are reserved, network controllers will reserve a data bus channel and sends a grand signal to the source processor. After receiving the grand signal, source processor will send immediately. Upon finishing the data transmission, a tear down signal is sent from the source core to the source network controller, which in turn broadcast it to the destination controller. All network controllers will update their status buffers based on received information.
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Intra Chip and Inter Chip Wireless Communication Analysis for Millimeter Wave using Miniaturized On Chip Antenna

Intra Chip and Inter Chip Wireless Communication Analysis for Millimeter Wave using Miniaturized On Chip Antenna

[5]. On-chip antennas are mainly used as wireless interconnects for the purpose of inter-chip/intra-chip communications. Generally, interconnect is a physical or logical connection between two electronic devices or networks. Connections between chips are mainly categorised as conventional, RF, Optical and 3D interconnects. Conventional interconnects are the low frequency metal wired connections. Since these ICs require high signal speed requirements, the wired interconnect structures are becoming the bottleneck for delay and noise in chips, making them an obstacle for increasing IC speed and performance. This is because resistance-capacitance (RC) delay is a characteristic of interconnects that increases sharply with increase in resistance. Hence, there is a need for better compaction using microwave and millimetre components. To make these antennas feasible with other components, they are usually designed on a millimetre scale at higher frequencies of around 10GHz (up to 60 GHz). However, communication range is limited. For frequencies lower than 10GHz, near field or inductive coupling is being used [6]-[8].
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Optical Solutions for Manycore Inter/Intra-Chip Interconnects

Optical Solutions for Manycore Inter/Intra-Chip Interconnects

Figure 4 shows the modification of a typical style flow to include the utilization of optical interconnects. basically the choice of whether or not to use optical interconnect or not is predicated on the distance between two points to be connected and therefore the rate of the signals between the points. Of course, this info is not noted before final placement, however early constraints before system refinement are helpful to avoid repetitive style loops. These constraints are often generated early within the style cycle through the definition of fixed-complexity (constant variety of gates) zones, where ideally intra-zone links are metallic and inter-zone links are optical. This suggests that solely distance info is taken into account that is why a posteriori correction ought to be administered after final placement. This section describes the ways that are usually utilized in the optical domain and so details however such tools are often integrated into customary EDA surroundings. We are aiming at remaining compatible with top-down and bottom- up methodologies characteristic of IC style, sanctioning informatics apply. This basically needs a definition of gradable description levels for all parts, with short simulation time at system level and high simulation accuracy at device level.
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An RF Transceiver for Wireless Chip-to-Chip Communication Using a Cross-Coupled Oscillator

An RF Transceiver for Wireless Chip-to-Chip Communication Using a Cross-Coupled Oscillator

The feasibility of wireless chip-to-chip communication (WCC) to overcome the drawbacks of TSV technology has already been proven through various previous studies [8–15]. To enhance the overall yields of 3DICs, the usage of through via holes should be minimized by utilizing WCC technology. However, the complexity of typical WCC technology should be moderated for mass production. In this work, we propose a WCC method using on/off keying (OOK) modulation to moderate the complexity of a typical WCC transceiver.

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A STUDY OF LOW TO HIGH SWING CONVERTERS FOR ON-CHIP INTERCONNECTS IN CMOS VOLTAGE INTERFACE CIRCUITS

A STUDY OF LOW TO HIGH SWING CONVERTERS FOR ON-CHIP INTERCONNECTS IN CMOS VOLTAGE INTERFACE CIRCUITS

behaves as a differential amplifier and the internal inverter further attenuates some noise through re-generation. It requires two extra power rails to limit the interconnect swing and uses special low-Vi devices to compensate for the current-drive loss due to the lower supplies. As the performance of VLSI’s increases, the chip size and the bus width will also increase and the total wiring capacitance of the bus lines will considerably larger. In addition to the increase in chip power, another concern for the design of VLSI’s is the reliability problems of interconnections. It relieves problem due to the reduced charging and discharging current.
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Coupled Chip-to-Chip Interconnect Design

Coupled Chip-to-Chip Interconnect Design

AC coupled interconnect (ACCI) has been demonstrated as a systematic solution for providing higher pin density, smaller transceiver design and lower power dissipation for high speed chip-to-chip communications. ACCI utilizes non-contact capacitor plates as signal I/O which yields a much higher pin density than traditional solder bump I/O. The coupling capacitors provide passive equalization, thus eliminating the need for costly traditional active equalization. This saves both power and area associated with the equalization circuitry used in a traditional transceiver. ACCI also saves significant power on the transmitter by using pulse signaling instead of traditional non-return-to-zero (NRZ) signaling.
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AC Coupled Interconnect for Inter-chip Communications

AC Coupled Interconnect for Inter-chip Communications

The scaling of integrated circuit (IC) technology demands high-speed, high-density and low-power input/output (I/O) for inter-chip communications. As an alternative scheme for conductive interconnects, AC coupled interconnect (ACCI) was proposed previously to meet these increasing I/O requirements. ACCI includes AC coupling elements into a signal channel; it has contactless physical structure and band-pass channel characteristic. ACCI can be classified into two categories: capacitively coupled interconnect (CCI) that includes series capacitors, and inductively coupled interconnect (LCI) that includes spiral transformers. This dissertation addressed research progresses on both CCI and LCI for multi-Gb/s inter-chip communications.
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Stream Arbitration: Towards Efficient Bandwidth Utilization for Emerging On-Chip Interconnects

Stream Arbitration: Towards Efficient Bandwidth Utilization for Emerging On-Chip Interconnects

In large-scale CMPs, it is no longer the case that all the network elements are communicating with all other elements uniformly. The state-of-the-art nonuniform cache architecture (NUCA) management schemes, such as RNUCA [Hardavellas et al. 2009] and page-recoloring scheme [Cho and Jin 2006], intend to place cache blocks near their most frequent requestors by smart initial placement, dynamic migration, and replication. Moreover, cache partitioning schemes [Qureshi and Patt 2006; Lee et al. 2010; 2011] can be used so that a cluster of cores are only going to access a locally allocated cache partition. Communication between these partitions is only required when there are coherence invalidations and fills. Therefore, it is expected that in future large-scale CMPs, the local communication in a core-cluster will dominate the overall communication. Under this circumstance, a flat stream arbitration scheme that uses a single curl to go across all nodes is wasting resources and unnecessarily limiting performance. Here, we propose a hierarchical stream arbitration scheme to make use of the communication patterns expected to be found in future large-scale CMPs. In the hierarchical stream we have a local transmission line (TL) for each core-cluster, and a global TL to connect these local TLs. Each TL consists of a curled arbitration channel and a set of data channels, as shown in Figure 14. The stream arbitration is performed independently in each level of the hierarchy.
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CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers

CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers

These observations motivate us to propose Cache- Coherence Network-on-Chip (CCNoC), a heterogeneous dual- network architecture for manycore server chips. CCNoC op- timizes power and performance based on the characteristics of the two dominant message classes. The networks are asymmetric in their datapath width and router architecture. The request network is optimized for short messages, and thus it has a narrow datapath. As requests (e.g., reads) and the associated coherent requests (e.g., downgrades) travel through the same network, the network relies on virtual channels to segregate these message classes for deadlock avoidance. In contrast, the response network does not require any virtual channels and is customized for cache block transfers via a wide datapath and low-complexity wormhole routers.
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Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects*

Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects*

Traditional on-chip interconnects have been implemented mostly using shared bus architecture but due to its limited scalability, it becomes less suitable in meeting the requirements of the future multi-core environment. As an alternative, Network-on-Chip (NoC) architectures have been recently introduced, where a packet-based network infrastructure provides interconnection among IP blocks, allowing concurrent transfer in the network [3, 4]. However, NoCs suffer from their inherent constraints such as limited area and power budget. Such limitations also bound the flexibility in network configuration such as routing algorithms, buffer size, and arbitration logic. Many researchers have focused on several aspects of the NoCs proposing efficient router pipeline design [5-7], fault-tolerant techniques [8, 9], deadlock-free routing algorithms [10-12], and thermal-aware low-power designs [13-15], etc.
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Design and Analysis of On-Chip Router for Network on Chip

Design and Analysis of On-Chip Router for Network on Chip

A variety of interconnection schemes are currently in use, including crossbar, buses and NOCs. Of these, later two are dominant in research community. However buses suffers from poor scalability because as the number of processing elements increases, performance degrades dramatically. Hence they are not considered where processing elements are more. To overcome this limitation attention has shifted to packet-based on-chip communication networks, known as Network-On-Chip (NOC).

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