6. Symbols for Devices and Functions
6.7 Abutment of Symbols
Logic symbols, whether representing elements in the same or different packages may be abutted according to the rules of ANSI/IEEE Std 91-1984 provided that
1) All required application information is shown 2) All connections external to the devices are shown
3) Nonexistent internal connections are not implied. See Fig 14.
Figure 14ÑAbutment of Symbols 6.8 Detached Representation of Symbols
Logic symbols may be shown in detached (disassembled) form provided that connections internal to a device are clearly indicated. See also 6.4.1.1.
Internal connections, if necessary to depict the logical relationships, shall be shown as solid connecting lines. An internal connection is implied by
1) The omission of terminal identiÞcations at the outline of the separated symbol portion, 2) Stating IC at the usual terminal identiÞcation location, or
3) Special identiÞers explained on the diagram or in a reference document
Connecting lines depicting internal connections may be interrupted provided the requirements of 7.4 are met.
Figure 15ÑDetached Representations of Devices 6.9 Unused Terminals and Elements
Terminals or circuit elements that are not used (for example, inputs, outputs, or complete elements in a multiple-element package) may be shown. If shown, terminal identiÞcation shall be included. If reserved for a speciÞc future use, the intended use should be indicated.
Any terminal that, if connected, could adversely affect the circuit shall be shown and labeled11 to warn against use.
6.10 Devices Having a Large Number of Terminals
The depiction of complex devices having very large numbers of terminals (for example, hundreds of pins) may be impractical using techniques applicable to less complex devices. The following possibilities should be considered:
1) Break the main complex device outline into parts. Put each part on a separate sheet of the diagram.
2) Break the main complex device into functional groups and detail each group separately.
3) Show the main complex device as a reentrant (open-jaw) shape. Place external devices connected between the terminals of the main device in the reentrant space. Other external connections may be shown around the outside periphery of the main device.
11Presently published conventions are:
ANSI Y1.1-1972 (R 1984) None.
IEC Publication 147-OF NU = not usable.
MIL-STD-12 DNU = do not use.
4) Group leads and use the Bus or Data Path symbols where practical.
5) Tabulate the full details of multilead paths in a separate table.
7. Interconnection of Symbols
7.1 General Requirements
Lines should be drawn horizontally or vertically except in those isolated cases where oblique lines improve the clarity of the diagram. After arranging the symbols on the diagram for functional clarity and symmetry, connecting lines should be drawn with as few bends and crossovers as possible.
If a signal feeds a multiplicity of elements, the use of a single straight line with appropriate indications of T-junctions aids comprehension of the diagram. See Fig 16.
Figure 16ÑDiagram Layout 7.2 Line Spacing
Minimum spacing (center-to-center) between parallel connecting lines, shall be approximately twice the lettering height if there is lettering between the lines. If there is no lettering between the lines the minimum spacing shall be equal to the general lettering height used on the diagram. See 4.6 and Appendix 11.. The longer parallel lines shall be arranged in groups, with approximately double spacing between groups. In determining the grouping, the functional relationship of the lines should be considered.
7.3 Junctions and Crossovers
All junctions of connecting lines should be shown as T-junctions, as shown in Fig 17(a), or Fig 17(b). When layout considerations prevent the exclusive use of the T-junction methods of Fig 17(a) or (b), multiple junctions may be shown as in Fig 17(c). Figure 17(d) illustrates the use of both the no-dot T-junction and multiple-junction methods in an array of lines if spacing or clarity of presentation precludes the exclusive use of the no-dot T-junction method of Fig 17(a).
Figure 17ÑJunctions and Crossovers 7.4 Interrupted Lines
Complex diagrams with many crossovers or with many elements in series (see Fig 18) may be simpliÞed by breaking ßow lines and providing a cross-reference between the interrupted connections. The cross-reference may be by signal names, common connection symbols, connection tables, or other unambiguous means. If necessary for clarity, reference to the locations (on the diagram) of the related common connections shall be provided.
Figure 18ÑLayout Techniques (a) Complex Presentation (b) Alternative Presentation The same techniques shall be used for common connections between sheets of multiple sheet drawings.
7.5 Grouping of Lines
The recommendations for grouping and omission of lines given in ANSI Y14.15-1966 (R 1973) apply also to lines representing information ßow and connection lines in logic diagrams. The techniques of highway or cable diagrams, ANSI Y14.15-1966 (R 1973) , can be used to simplify logic diagrams where groups of similar signals are encountered.
For example, binary coded decimal (BCD) lines 1, 2, 4, 8, 10, 20, 40, and 80 could be combined (see Fig 19), provided that the individual lines are properly identiÞed at both ends.
Figure 19ÑGrouping of Lines 7.6 Polarity and Negation Matching
The symbols used in an application usually are chosen so that the polarity or negation indication at an input is the same as that at the source of a signal feeding that input. If this is done, a reader of the diagram can directly apply the internal logic state of an output as the internal logic states of the inputs fed by that output. In the case of direct polarity indication, if the form of the signal name is chosen as described in 8.2.2.2 the signal name, excluding the level indication, directly expresses the meaning of that internal logic state.
However, it is not always possible to choose symbols so that all the inputs and outputs connected by a signal carry the same polarity or negation indication. If there is a mismatch between the indication at the source of a signal and the indication at the destination, a reader of the diagram must invert the internal logic state of the source before using it as the internal logic state of the next input. Because these mismatches are a common source of errors in logic circuit design, it can be helpful to clearly indicate where such mismatches (and inversions) intentionally exist. If it is desired to highlight these mismatches, it should be done using a short perpendicular line (the mismatched symbol) across the connecting line.
This symbol divides the connection into two segments each of which contains consistent polarity or negation indicators. If the connecting line is branched, one or more symbols should be used to divide the connection tree into consistent subtrees.
7.7 Power Connections
Power connections (voltage requirements) to logic devices shall be speciÞed on detailed logic diagrams. Normally connections to logic device power terminals (for example, VCC, VBB, GND) are not shown graphically but are speciÞed in a table or a note.
8. Labeling of Connecting Lines
8.1 General
Labeling of connecting lines can greatly promote the understanding of a diagram and facilitate the maintenance of a logic system, provided that the lines are labeled intelligently and that names are chosen carefully, based on system functions. Each label should be shown adjacent to the line to which it applies or within a break in that line.
8.2 Names for Logic and Analog Signals
Signal names are used to uniquely identify sets of points that are electrically interconnected without intervening devices.
8.2.1 General Requirements
Signal names should be concise, informative, and unambiguous.
8.2.1.1 Descriptive Requirements
Signal names should indicate the function performed by the signal or the particular information carried. Every effort should be made to use mnemonic names (see Appendix A) and standard abbreviations (see ANSI Y1.1-1972 (R 1984) . The mnemonics and abbreviations used should be explained on the diagram or in supporting documentation. If space permits, easy-to-understand mnemonics should be used instead of overly short abbreviations. For example, SELDEV1 better conveys the meaning SELECT DEVICE 1 than does SD1. For other examples see Figs 20, 31, and 32.
Signals should be named based on the function they perform rather than on the signals that are used to generate them.
If a signal PRUN is gated with a second signal TP6 to produce a signal that sets a bistable element called RUN, then its function is obvious if the output signal is named SETRUN. However, if the output signal is named PRUNTP6, then its function is open to speculation. See Fig 20, Example (a).
NOTE Ñ Mnemonics and abbreviations based on typical usage in the English language cannot all be translated without risk of confusion.
8.2.1.2 Recommended Characters
Signal names should be composed from standard character sets, excluding lowercase letters. Single embedded spaces may be used where necessary. To maintain compatibility with computer processing, it is recommended that character sets be restricted to12
8.2.1.3 Length
Practical considerations and design automation systems usually place limits on the allowable length of signal names.
Therefore, it is recommended that a maximum length of 24 characters be mutually supported by designers and design-automation systems.
8.2.1.4 Similar and Equivalent Signals
Identical names shall not be applied to different signals, no matter how similar the functions. A signal name shall be altered whenever the signal is ampliÞed, inverted, gated with another signal, delayed, chopped, stored, or changed in any way. This change may take the form of an addition of a suitable sufÞx to the signal name so as to construct a new signal name. For example see Fig 20, Examples (d) and (f).
If the same signal is generated more than once, is ampliÞed, or is level shifted, then each occurrence or variation of the basic signal should have the same basic name modiÞed by the addition of a different serial number or letter sufÞx. The serial number or letter may be concatenated with the basic name or separated from it by a space. For example, if the signal STOP drives two ampliÞers, the outputs of those ampliÞers may be labeled STOP1 and STOP2. For example, see Fig 20, Example (f).
12ISO 646-1983 , 7-bit Character Set (International Reference Version (except for Â).
ANSI X3.4-1977, 7-bit Character Set (except for - Â).
(1) Capital letters A to Z
(2) Digits 0 to 9
(3) Negation characters - ~ Â
(4) Special characters ! " % & ' ( ) * + , - . / : ; < = >
? ^ Ñ
Figure 20ÑExamples of Signal Name Allocation
If a binary logic signal is simply inverted, then the inverted signal should have the same basic name as the uninverted signal, modiÞed by the addition (or deletion) of negation bars (or other negation indication). On diagrams using direct polarity indication, the indicated signal level (see 8.2.2.2) may be changed instead. If a signal is inverted more than once, serial numbers or letters should be used to distinguish different inverted or uninverted versions of a signal.
8.2.2 Binary Logic Signals
Binary logic signals are signals having only two states, represented by two nonoverlapping ranges of physical values for the signal. These two ranges are called levels.
8.2.2.1 Signal State
For binary logic signals, the signal name should include an abbreviation of a statement or expression that is either true or false. For example, the name ALARM is an abbreviation of the statement ALARM IS ACTIVE. A signal name shall not contain an inherent contradiction. The name ON/OFF consists of two parts, and when one part is true the other is false. Such a signal name is ambiguous and might seem to imply a statement that is always true.
The truth value obtained from evaluating the statement or expression represented by the signal name is called the signal state.
The true value of a statement represented by the signal name corresponds to the 1-state of the signal. The false value of a statement represented by the signal name corresponds to the 0-state of the signal. For example, the signal name ALARM means that ALARM IS ACTIVE is true when the signal is in its 1-state and false when the signal is in its 0-state. See Table 1, rows 1 and 2.
Table 1ÑRelationships Among States and Signal Names (Single Logic Convention) Relationship Defined by Presence or Absence of
Negation Symbol
Row Input (or Output)
System
1ÑThe signal state being true always corresponds to the external logic state being 1.
2ÑThe signal state being false always corresponds to the external logic state being 0.
8.2.2.1.1 Negated Signals
Signal names that embody an inherent negative, such as NORUN, are difÞcult to understand. It requires some mental somersaults to say whether the corresponding statement NORUN IS ACTIVE is true or false. If possible, such signal names should be made inherently true. For example, STOP or HALT could be substituted for NORUN.
However, sometimes an action should take place when a certain statement, or expression, is not true. The preferred method of indicating negation of a signal name is to place a negation bar over the portion of the name representing the expression to be negated. For example, RUN corresponds to the statement RUN IS NOT ACTIVE. Note that the signal name includes the negation bar. The signal name RUN means that RUN IS NOT ACTIVE is true when the signal is in its 1-state and false when the signal is in its 0-state. This further implies that RUN IS ACTIVE is true when the signal RUN is in its 0-state and false when the signal RUN is in its 1-state. See Table 1, rows 3 and 4.
If an in-line notation for negation is required, then the negation bar may be replaced by a preceding mathematical symbol for logic negation
Â
13 or a different notation explained on the diagram or in supporting documentation, for exampleÂ
RUN. If confusion is likely regarding which portion of the signal name is negated, that portion of the signal name to be negated shall be enclosed in parentheses with the negation symbol placed immediately following the opening parenthesis, subject to the following rule:The in-line negation symbol applies to the string to the right of the symbol up to the Þrst occurrence of 1) An unmatched closing parenthesis,
2) A solidus that is itself not enclosed within a matching set of parentheses to the right of the negation symbol, or
3) The end of the string.
For example
The tilde (~) may be substituted for the symbol for logic negation on computer systems not having the logic negation symbol
Â
as part of their character sets.8.2.2.1.2 Arithmetic and Logical Expressions
The plus sign (+) denotes algebraic addition and the minus sign (-) denotes algebraic subtraction; for example, AR+1 may be the mnemonic for ADDRESS REGISTER PLUS 1.
In signal names the plus sign (+) should be used to denote the OR function only if no confusion with algebraic addition is likely. If the content does not clarify the distinction, an often used solution is to substitute the words OR or PLUS as appropriate in one or both of the cases.
13ISO 31/1-1978 , Symbol 11-2.3.
A logic AND function may be denoted by a dot (á), an asterisk (*), or, if no confusion is likely, by normal juxtaposition.
For example, ENAáBLE may be the mnemonic for ENABLE A ANDed with BLOCK E; PQ may mean P ANDed with Q. See also 8.2.1.1.
Parentheses may be used to clarify expressions. For example, (ENA)BLE is another way to indicate the mnemonic for ENABLE A ANDed with BLOCK E.
8.2.2.1.3 Bus Signals and Other Grouped Signals
Bit and byte labeling within a bus or other set of grouped signals should include a numeric sufÞx to the bus or group name. For buses or groups with an inherent weighting of the signals within, the numeric sufÞxes should represent the actual weights of the signals, all of which are consistently expressed either as decimal numbers or as exponents of the powers of 2. The numeric sufÞx may be enclosed in angle brackets.14 For example, the 32 lines of an intermediate register may be labeled IRBUS<1> to IRBUS<2147483648>, or IRBUS<00> to IRBUS<31>. A seven line BCD intermediate register should be labeled IRBUS<1>, IRBUS<2>, IRBUS<4>, IRBUS<8>, IRBUS<10>, IRBUS<20>, IRBUS<40>.
Connecting lines representing entire buses, rather than individual signals within them may be labeled as follows:
IRBUS<0:31> º IRBUS<0>, IRBUS<1>, ..., IRBUS<31>
IRBUS<1,2,4,8,10,20,40> º IRBUS<1>, IRBUS<2>, IRBUS<4>, ..., IRBUS<40>
If any other convention is used, and the meaning is not obvious, it shall be explained on the diagram or in supporting documentation.
For clarity, weighting of individual bits of a bus shall be indicated either in the symbol elements or with the connecting lines. IEC Publication 113-7 (1971-1983) states that connecting lines for buses should be ordered proceeding from least signiÞcant to most signiÞcant, from top to bottom, or from left to right. This is the normal result of using logic symbols for weighted arrays having a common control block on the top or left of the symbol.
8.2.2.1.4 Clock Signals
In signal names for clocks, it is often helpful to include important characteristics such as period (or frequency) and phase. For example, if the basic clock period is 25 ns, the mnemonic might be CP25N. Clocks derived from the basic clock might then be termed CP50N, CP100N, and so on.
The timing pulses from CP50N might be designated as indicated in Fig 21.
8.2.2.2 Signal Level
In detailed logic diagrams employing a single logic convention (positive or negative logic), the relationship between the external logic states of the signals and the corresponding logic levels is Þxed. For example, if the positive logic convention is in force, the 1-state of a signal (the true state of the signal name) always corresponds to the H-level. For the negative logic convention, the 1-state always corresponds to the L-level.
14 Angle brackets can be formed from the less than (<) and greater than (>) characters.
Figure 21ÑClock and Timing Pulses
In detailed logic diagrams employing direct polarity indication, the logic symbols do not imply any external logic state, only logic levels. Therefore, each logic signal name should include an indication of which logic level corresponds to the 1-state (true state) of the signal. The preferred method for doing this is to place an indication of that logic level (for example, H or L) within parentheses at the end of the signal name.
EXAMPLES:
ALARM(H) means ALARM IS ACTIVE is true when the logic level of the signal is high and is false when the logic level is low.
ALARM (H) means ALARM IS NOT ACTIVE is true when the logic level is high and is false when the logic level is low. This further implies that ALARM IS ACTIVE is true when the logic level of the signal is low and false when the logic level is high. See Table 2 for all combinations.
STOP(L) means STOP IS ACTIVE is true when the logic level of the signal is low and is false when the logic level is high.
A signal whose true state corresponds with a high level may be referred to as a true-when-high signal.
A signal whose true state corresponds with a low level may be referred to as a true-when-low signal.
If all signal names on a diagram are true when high, the logic level indications may be omitted from the names.
Table 2ÑRelationships Among States, Levels, and Signal Names (Direct Polarity Indication)
A signal name that can be derived by applying both logic negation and level inversion to an existing signal name is equivalent to the existing signal name and therefore shall not be used to identify a different signal. For example:
STOP(L) = STOP(H) ALARM(H) = ALARM(L) RD/WR(H) = RD/WR(L)
Relationship Defined by Presence or Absence of
1 Ñ The signal state being true corresponds to the external logic level being that level speciÞed in the signal
1 Ñ The signal state being true corresponds to the external logic level being that level speciÞed in the signal