13 Characteristics
13.4 AC electrical characteristics
13.4.1 Separate read/write strobe bus timing
Table 154. Antenna driver output pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
VOH HIGH-level output voltage
VDD(TVDD) = 5.0 V; IOL = 20 mA - 4.97 - V
VDD(TVDD) = 5.0 V; IOL = 100 mA - 4.85 - V
VOL LOW-level output voltage
VDD(TVDD) = 5.0 V; IOL = 20 mA - 30 - mV
VDD(TVDD) = 5.0 V; IOL = 100 mA - 150 - mV
IO output current transmitter; continuous wave;
peak-to-peak
- - 200 mA
Table 155. Timing specification for separate read/write strobe
Symbol Parameter Conditions Min Typ Max Unit
tLHLL ALE HIGH time 20 - - ns
tAVLL address valid to ALE LOW time 15 - - ns
tLLAX address hold after ALE LOW time
8 - - ns
tLLRWL ALE LOW to read/write LOW time
ALE LOW to NRD or NWR LOW
15 - - ns
tSLRWL chip select LOW to read/write LOW time
NCS LOW to NRD or NWR LOW
0 - - ns
tRWHSH read/write HIGH to chip select HIGH time
NRD or NWR HIGH to NCS HIGH
0 - - ns
tRLDV read LOW to data input valid time
NRD LOW to data valid - - 65 ns
tRHDZ read HIGH to data input high impedance time
NRD HIGH to data high-impedance
- - 20 ns
tWLQV write LOW to data output valid time
NWR LOW to data valid - - 35 ns
tWHDX data output hold after write HIGH time
data hold time after NWR HIGH
8 - - ns
tRWLRWH read/write LOW time NRD or NWR 65 - - ns
tAVRWL address valid to read/write LOW time
NRD or NWR LOW (set-up time)
30 - - ns
tWHAX address hold after write HIGH time
NWR HIGH (hold time) 8 - - ns
tRWHRWL read/write HIGH time 150 - - ns
Remark: The signal ALE is not relevant for separate address/data bus and the
multiplexed addresses on the data bus do not care. The multiplexed address and data bus address lines (A0 to A2) must be connected as described in Section 9.1.3 on page 8.
13.4.2 Common read/write strobe bus timing
Fig 19. Separate read/write strobe timing diagram
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Table 156. Common read/write strobe timing specification
Symbol Parameter Conditions Min Typ Max Unit
tLHLL ALE HIGH time 20 - - ns
tAVLL address valid to ALE LOW time 15 - - ns
tLLAX address hold after ALE LOW time 8 - - ns
tLLDSL ALE LOW to data strobe LOW time NWR or NRD
LOW
15 - - ns
tSLDSL chip select LOW to data strobe LOW time
NCS LOW to NDS LOW
0 - - ns
tDSHSH data strobe HIGH to chip select HIGH time
0 - - ns
tDSLDV data strobe LOW to data input valid time
- - 65 ns
tDSHDZ data strobe HIGH to data input high impedance time
- - 20 ns
tDSLQV data strobe LOW to data output valid time
NDS/NCS LOW - - 35 ns
tDSHQX data output hold after data strobe HIGH time
NDS HIGH (write cycle hold time)
8 - - ns
tDSHRWX RW hold after data strobe HIGH time
after NDS HIGH 8 - - ns
tDSLDSH data strobe LOW time NDS/NCS 65 - - ns
13.4.3 EPP bus timing
tAVDSL address valid to data strobe LOW time
30 - - ns
tRHAX address hold after read HIGH time 8 - - ns
tDSHDSL data strobe HIGH time period between
write sequences
150 - - ns
tWLDSL write LOW to data strobe LOW time R/NW valid to NDS LOW
8 - - ns
Fig 20. Common read/write strobe timing diagram
Table 156. Common read/write strobe timing specification …continued
Symbol Parameter Conditions Min Typ Max Unit
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Table 157. Common read/write strobe timing specification for EPP
Symbol Parameter Conditions Min Typ Max Unit
tASLASH address strobe LOW time nAStrb 20 - - ns
tAVASH address valid to address strobe HIGH time
multiplexed address bus set-up time
15 - - ns
tASHAV address valid after address strobe HIGH time
multiplexed address bus hold time
8 - - ns
tSLDSL chip select LOW to data strobe LOW time
NCS LOW to nDStrb LOW
0 - - ns
tDSHSH data strobe HIGH to chip select HIGH time
nDStrb HIGH to NCS HIGH
0 - - ns
tDSLDV data strobe LOW to data input valid time
read cycle - - 65 ns
Remark: Figure 21 does not distinguish between the address write cycle and a data write cycle. The timings for the address write and data write cycle are different. In EPP mode, the address lines (A0 to A2) must be connected as described in Section 9.1.3 on page 8.
tDSHDZ data strobe HIGH to data input high impedance time
read cycle - - 20 ns
tDSLQV data strobe LOW to data output valid time
nDStrb LOW - - 35 ns
tDSHQX data output hold after data strobe HIGH time
NCS HIGH 8 - - ns
tDSHWX write hold after data strobe HIGH time
nWrite 8 - - ns
tDSLDSH data strobe LOW time nDStrb 65 - - ns
tWLDSL write LOW to data strobe LOW time nWrite valid to nDStrb LOW
8 - - ns
tDSL-WAITH data strobe LOW to WAIT HIGH time
nDStrb LOW to nWrite HIGH
- - 75 ns
tDSH-WAITL data strobe HIGH to WAIT LOW time
nDStrb HIGH to nWrite LOW
- - 75 ns
Fig 21. Timing diagram for common read/write strobe; EPP
Table 157. Common read/write strobe timing specification for EPP …continued
Symbol Parameter Conditions Min Typ Max Unit
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13.4.4 Clock frequency
The clock input is pin OSCIN.
The clock applied to the MFRC500 acts as a time constant for the synchronous system’s encoder and decoder. The stability of the clock frequency is an important factor for ensuring proper performance. To obtain highest performance, clock jitter must be as small as possible. This is best achieved using the internal oscillator buffer and the
recommended circuitry; see Section 9.8 on page 26.