Access Paths

An access path describes the value or location of an operand, result or jump target. We classify an instruction as a 0-, 1-, 2-, or 3-address instruction according to the number of access paths it species. Very seldom are there more than three access paths per instruction, and if more do exist then they are usually implicit. (For example, in the MVCL instruction of the IBM 370 the two register specications R1 and R2 actually dene four operands in registers R1, R1+1, R2 and R2+1 respectively.)

Each access path species the initial element of an operand or result in a storage class. Access paths to some of the storage classes (such as the stack, program counter, condition code and special registers) are not normally explicit in the instruction. They will appear only when there is some degree of freedom associated with their use, as in the PDP11 where any register can be used as a stack pointer.

The most common explicit access paths involve one of the following computations: Constant. The value appears explicitly in the instruction.

Register. The content of the register is taken as the value.

Register+constant. The sum of the content of the register and a constant appearing explicitly in the instruction is taken as the value.

Register+register. The sum of the contents of two registers is taken as the value. Register+register+constant. The sum of the contents of two registers and a constant

appearing in the instruction is taken as the value.

The computed value may itself be used as the operand (immediate), it may be used as the eective address of the operand in main storage (direct), or it may be used as the address of an address (indirect). On some machines the object fetched from main storage in the third case may specify another computation and further indirection, but this feature is rarely used in practice. Figure 3.3 illustrates these concepts for typical machines.

The addresses of registers must almost always appear explicitly as constants in the instruc- tion. In special cases they may be supplied implicitly, as when the content of the (unspecied) program counter is added to a constant given in the instruction (relative addressing). If the computed value is used as an address then the registers must belong to the base register or index register class; the sum of the (unsigned) base address and (signed) index is often

3.1 Basic Characteristics 41

i: Operand is the byte i from the instruction.

d(m,n): Operand is the 24-bit value obtained by (Rm)+(Rn)+d. Only the low-order 24 bits of each register are used, and the value is interpreted as positive. Overow in the addition is ignored. If m or n is 0 then the content of the register is assumed to be 0; the actual content of general register 0 is not used.

m: Operand is the content of general register Rm.

m: Operand is the content of general register pair (Rm,Rm+1). m: Operand is the content of oating point register Fm.

d(m,n): Operand is the content of a memory area whose address is the value computed as discussed above.

Implicit access to the condition code and program counter. Note: 0i <2 8, 0 d <2 12, 0 m;n <2 4 a) IBM 370 =i16: Operand is the word following the instruction. =i32: Operand is the doubleword following the instruction. i16: Operand is the value (PC)+i16.

i8(Am): Operand is the value (PC)+(Am)+i8. i8(Dn): Operand is the value (PC)+(Dn)+i8. Am: Operand is the content of address register Am. Dn: Operand is the content of data register Dn.

(Am): Operand is the content of a memory area whose address is the content of address register Am. i16(Am): Operand is the content of a memory area whose address is the value of (Am)+i16. i8(Am,Dn): Operand is the content of a memory area whose address is the value of (Am)+(Dn)+i8. (Am)+: Operand is the content of a memory area whose address is the content of Am. Am is then

incremented by the operand length. The increment is never less than 2 for A7.

-(Am): Am is decremented by the operand length. Operand is then the content of a memory area whose address is the content of Am. The decrement is never less than 2 for A7.

Implicit access to the condition code and program counter. b) Motorola 68000

Figure 3.3: Access Paths

interpreted modulo the address size. The values of constants in instructions are frequently re- stricted to nonnegative values, and often their maximum values are far less than the maximum address. (An example is the restriction to the range [0,4095] of the IBM 370.)

Not all computers allow every one of the access paths discussed above; restrictions in the combination (operation, access path) can also occur. Many of these restrictions arise from the properties of the machine's registers. We distinguish ve architectural categories based upon register structure:

Storage-to-storage. All operands of a computational operation are taken from main storage, and the result is placed into main storage (IBM 1400 series, IBM 1620). Storage- to-storage operations appear as a supplementary concept in many processors.

Stack. All operands of a computational operator are removed from the top of the stack, and the result is placed onto the top of the stack (Burroughs 5000, 6000 and 7000 series, ICL 2900 family). The stack appears as a supplementary concept in many processors. Single Accumulator. One operand of a computational operator is taken from the accu-

mulator, and the result is placed into the accumulator; all other registers, including any accumulator extension, have special tasks or cannot participate in all operations (IBM 7040/7090, Control Data 3000 series, many process-control computers, Intel 8080 and microprocessors derived from it).

Multiple Accumulator. One operand of a computational operator is taken from one of the accumulators, and the result is returned to that accumulator; long operands and

results are accommodated by pairing the accumulators (DEC PDP11, Motorola 68000, IBM 370, Univac 1100)

Storage Hierarchy. All operands of a computational operator are taken from accumula- tors, and the result is returned to an accumulator (Control Data 6000, 7000 and Cyber series). This architecture is identical to the storage-to-storage architecture if we view the accumulators as primary storage and the main storage as auxiliary storage.