Algorithm Attributes

There are a few attributes of the SCR algorithm that are not clearly captured by the discussion in Section 4.2.1, but are important to mention. These attributes include the algorithm’s extensibility; vital characteristics that affect the success of gate recognition; and abilities to handle various types of gate inputs and outputs, accurately identify gates used in feedback structures, and successfully produce a netlist even when un-recognized gates are encountered. Each attribute will be discussed in the following paragraphs.

Extensibility. In terms of extensibility, the form of future growth that must be taken into consideration when crafting the structure of the SCR code is the addition of gates that the SCR algorithm can recognize. In order to accomodate this type of growth, the SCR code was given a hierarchical structure. The hierarchical structure provides for good organization of the SCR code, which makes it simple to understand where code must be added to provide for the processing of new gates. The following example explains how to add code in order to expand the SCR algorithm to recognize an OR3 gate. No adjustments would be made to the SCR function in the first hierarchical level, as functions for specific gates are detailed in lower levels of hierarchy. In the second hierarchical level, the

functions Find cells and Find cell types would need to be modified. Find cells would be modified to call an additional child function: Find OR3. Similarly, Find cell types would be modified to call an additional child function: Find OR3 types. As Find cells is

structured to call its child functions in the order of increasing level of gate abstraction (this concept is discussed in the next section), Find OR3 would be inserted between the

functions Find OR2 and Find NAND2b0. Likewise, in the parent function

Find cell types, the child function Find OR3 types would be inserted between the child functions Find OR2 types and Find NAND2b0 types. In the third hierarchical level, the functions Find OR3 and Find OR3 types would need to be defined. Additionally, the

Write cells to netlist would need to be modified with the addition of calls to the child functions Remove OR3 transistors from components, Add OR3s to components, and Write OR3s to netlist, respectively. In the fourth hierarchical level, the functions Remove OR3 transistors from components, Add OR3s to components, and

Write OR3s to netlist would need to be defined. In summary, the process for expanding the SCR algorithm to recognize additional gates requires modifying parent functions in the second and third hierarchical levels and defining child functions in the third and fourth hierarchical levels.

Vital Characteristics for Success in Gate Recognition. There are a few important

characteristics of the algorithm that greatly affect its ability to accurately recognize the gates. First, the algorithm executes a specific order in finding the gates. The gates are found in order of increasing levels of abstraction, but decreasing complexity within each level of abstraction. Gates within a level of abstraction must be found in order of

decreasing complexity since certain gates in a given level can appear to be composed of other gates within the same level. For example, as seen in Figure 78, a NAND2b0 consists of an inverter and an OR2 gate, and an OAI21b1 consists of a NAND2 gate, OR2 gate, and inverter. Thus, if the gates of fourth-level abstraction were identified in order of increasing complexity (OAI21b1 identified after NAND2b0), the OAI21b1 gate would be falsely identified as a NAND2b0 gate connected to a NAND2 gate. Identifying gates in order of decreasing complexity (NAND2b0 identified after OAI21b1) enables accurate identification.

Second, the algorithm must specify rules to identify fourth-level gates. For example, Figure 78 shows that the OAI21b0b1 consists of an OR2, AND2, and inverter. In the figure, a NAND2 gate is connected to the inverter of the OAI21b0b1; thus, given that gate identification occurs in order of increasing levels of abstraction, instead of identifying an OAI21b0b1 connected to a NAND2 gate, the algorithm (without rules) would identify an

OR2 gate connected to two AND2 gates. The rules guide the algorithm to separate the AND2 gate (that has the OR2s output as an input) into a NAND2 gate and an inverter so that the OAI2b0b1 can be identified.

Figure 78: Full adder cell. Compositions of gates at the fourth level of abstraction are shown in boxes

Gate Inputs. There are four significant details regarding the algorithm’s ability to handle various types of gate inputs and outputs. First, the algorithm can recognize gates regardless of whether or not the inputs are pins or are connected to actual power sources. Second, the algorithm can recognize gates regardless of the output connection (a pin or a load). The first and second details are evidenced by the success of the algorithm in

recognizing both the gates in Section 4.1.2, which are connected to power sources, and the gates in Section 4.1.4, which are not connected to power sources. Third, one signal can be connected to more than one input of a single gate, as evidenced in Section 4.1.4 with the example of the 2-to-1 MUX circuit. This example also provides evidence for the fourth detail, that one signal can be connected to inputs of more than one gate.

Gate A. Hence, it is a feedback structure. The algorithm achieved perfect recognition results for the Master/Slave DFF, indicating that the algorithm is capable of processing feedback structures.

Encounters with Unrecognized Gates. A significant feature of the algorithm is that

it is still capable of producing an output netlist even when it is unable to recognize all the gates in the circuit. In this type of situation, the algorithm simply maintains a

transistor-level representation of the unrecognized gates in the output netlist. Hence, the output netlist will not be constructed purely at the gate level or purely at the transistor level. Rather, it will contain a mixture of both. An example of this can be seen with the test circuit Test1. The output netlist for Test1 generated by the algorithm is reproduced in Appendix D.