3.1 Topological Sorting of the Prediction Graph . . . 41 3.2 Computation of a Longest Path . . . 42 4.1 Detection of Timing Anomalies . . . 52 5.1 Validation of Prediction Event Graph against Measured Trace . . . 70
Bibliography
[1] AEROFLEX GAISLER. http://www.gaisler.com.
[2] ALTMEYER, S., DAVIS, R. I., AND MAIZA, C. Cache related pre-emption aware response time analysis for fixed priority pre-emptive systems. InProceedings of the 32nd IEEE Real-Time Systems Symposium (RTSS’11) (December 2011), R. I.
Davis and N. Fisher, Eds., pp. 261–271.
[3] BERG, C. PLRU cache domino effects. In 6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, Dresden (July 2006), F. Mueller, Ed., no. 06902 in Dagstuhl Seminar Proceedings, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI).
[4] CASSEZ, F., HANSEN, R. R., AND OLESEN, M. C. What is a Timing Anomaly?
In12th International Workshop on Worst-Case Execution Time Analysis (Dagstuhl, Germany, 2012), T. Vardanega, Ed., vol. 23 ofOpenAccess Series in Informatics (OASIcs), Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik, pp. 1–12.
[5] COUSOT, P., AND COUSOT, R. Static determination of dynamic properties of programs. InProceedings of the second international Symposium on programming (1976), Dunod, Paris, France, pp. 106–130.
[6] COUSOT, P., AND COUSOT, R. Abstract interpretation: A unified lattice model for static analysis of programs by construction or approximation of fixpoints. In POPL ’77: Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages (New York, NY, USA, 1977), ACM, pp. 238–252.
[7] DAVEY, B. A., AND PRIESTLEY, H. A.Introduction to Lattices and Order, 2nd ed.
Cambridge University Press, May 2002.
[8] EISINGER, J., POLIAN, I., BECKER, B., THESING, S., WILHELM, R., AND METZNER, A. Automatic identification of timing anomalies for cycle-accurate worst-case execution time analysis. InDDECS ’06: Proceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems (Washington, DC, USA, 2006), IEEE Computer Society, pp. 13–18.
[9] ENGBLOM, J., AND JONSSON, B. Processor pipelines and their properties for static WCET analysis. InEMSOFT ’02: Proceedings of the Second International Conference on Embedded Software (London, UK, 2002), Springer-Verlag, pp. 334–
348.
[10] ERC32 chipset documentation. http://microelectronics.esa.int/erc32/.
[11] FEDERAL AVIATION ADMINISTRATION. What is a “decision” in application of modified condition/decision coverage (MC/DC) and decision coverage (DC)?
Position paper CAST-10, U.S. Department of Transportation, Washington, DC 20591, June 2002.
[12] FERDINAND, C. Cache Behaviour Prediction for Real-Time Systems. PhD thesis, Universität des Saarlandes, 1997.
[13] FERDINAND, C., AND WILHELM, R. Efficient and precise cache behavior prediction for real-time systems. Real-Time Systems 17, 2-3 (1999), 131–181.
[14] GEBHARD, G., CULLMANN, C., AND HECKMANN, R. Software Structure and WCET Predictability. In Bringing Theory to Practice: Predictability and Performance in Embedded Systems (Dagstuhl, Germany, 2011), P. Lucas, L. Thiele, B. Triquet, T. Ungerer, and R. Wilhelm, Eds., vol. 18 of OpenAccess Series in Informatics (OASIcs), Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik, pp. 1–10.
[15] GRUND, D., REINEKE, J., AND GEBHARD, G. Branch target buffers: WCET analysis framework and timing predictability. In15th International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2009 (August 2009).
[16] INSTITUTE OF ELECTRICAL AND ELECTRONIC ENGINEERS. VHDL lan-guage reference manual. IEEE Standard P1076 2000/D3, New York, 2000.
[17] The Kate Editor. http://www.kate-editor.org.
[18] KIRNER, R., KADLEC, A., AND PUSCHNER, P. Precise worst-case execution time analysis for processors with timing anomalies. InProceedings of the 21st Euromicro Conference on Real-Time Systems (Dublin, Ireland, July 2009), IEEE, pp. 119–128.
[19] LaTeX - A Document Preparation System. http://www.latex-project.org.
[20] LEON2 processor user’s manual. http://www.arl.wustl.edu/.../leon2-1_0_23-xst.pdf.
[21] LIONS, J.-L., LÜBECK, L., FAUQUEMBERGUE, J.-L., KAHN, G., KUBBAT, W., LEVEDAG, S., MAZZINI, L., MERLE, D., AND O’HALLORAN, C. Ariane 5 flight 501 failure. Ariane 501 inquiry board report, ESA, Paris, Juli 1996.
[22] Longest path problem. http://en.wikipedia.org/wiki/Longest_path_problem.
[23] LUCAS, P., PARSHIN, O., AND WILHELM, R. Operating mode specific WCET analysis. InProceedings of JRWRTC (October 2009), C. Seidner, Ed.
Bibliography
[24] LUNDQVIST, T., AND STENSTRÖM, P. Timing anomalies in dynamically scheduled microprocessors. InReal-Time Systems Symposium (RTSS) (December 1999).
[25] MAHAPATRA, N. R., AND VENKATRAO, B. The processor-memory bottleneck:
Problems and solutions.Crossroads - Computer architecture Crossroads Homepage archive 5, 3es (Spring 1999).
[26] MARTIN, F., ALT, M., WILHELM, R., AND FERDINAND, C. Analysis of loops. In Compiler Construction, K. Koskimies, Ed., vol. 1383 of Lecture Notes in Computer Science. Springer Berlin / Heidelberg, 1998, pp. 80–94.
10.1007/BFb0026424.
[27] MOORE, G. Cramming more components onto integrated circuits. Eletronics 19, 3 (April 1965), 114–117.
[28] MPC5553 and MPC5554 microcontroller reference manual.
http://freescale.com/files/.../MPC5553_MPC5554_RM.pdf.
[29] The Nexus 5001 Forum Standard for a Global Embedded Processor Debug Interface, 2003.
[30] NIELSON, F., NIELSON, H. R., AND HANKIN, C.Principles of Program Analysis, 2nd ed. Springer-Verlag New York, Inc., Secaucus, NJ, USA, 2005.
[31] PETTERS, S. M. Comparison of trace generation methods for measurement based WCET analysis. In3rd International Workshop on Worst Case Execution Time Analysis (Porto, Portugal, July 2003), pp. 75–78.
[32] REINEKE, J. Caches in WCET Analysis. PhD thesis, Universität des Saarlandes, November 2008.
[33] REINEKE, J., AND SEN, R. Sound and efficient wcet analysis in the presence of timing anomalies. In9th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis (Dagstuhl, Germany, 2009), N. Holsti, Ed., Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany.
[34] REINEKE, J., WACHTER, B., THESING, S., WILHELM, R., POLIAN, I., EISINGER, J., AND BECKER, B. A definition and classification of timing anomalies. InWorkshop on Worst-Case Execution-Time Analysis (WCET) (July 2006).
[35] ROJAS, R. Konrad Zuse’s legacy: The architecture of the Z1 and Z3. IEEE Annals of the History of Computing 19, 2 (April 1997), 5–16.
[36] Rubber - A Wrapper for LaTeX and Friends. http://launchpad.net/rubber.
[37] SCHLICKLING, M., AND PISTER, M. Semi-automatic derivation of tim-ing models for WCET analysis. In LCTES ’10: Proceedings of the ACM SIG-PLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems (April 2010), ACM, pp. 67–76.
[38] SCHNEIDER, J. Combined Schedulability and WCET Analysis for Real-Time Operating Systems. PhD thesis, Saarland University, 2003.
[39] SHARIR, M., AND PNUELI, A. Two Approaches to Interprocedural Data Flow Analysis. InProgram Flow Analysis: Theory and Applications, S. S. Muchnick and N. D. Jones, Eds. Prentice-Hall, 1981, ch. 7.
[40] TC1797 microcontroller reference manual. http://www.infineon.com.
[41] THEILING, H. Ilp-based interprocedural path analysis. InEMSOFT (2002), A. L. Sangiovanni-Vincentelli and J. Sifakis, Eds., vol. 2491 ofLecture Notes in Computer Science, Springer, pp. 349–363.
[42] THESING, S. Safe and Precise WCET Determinations by Abstract Interpretation of Pipeline Models. PhD thesis, Saarland University, 2004.
[43] THOMAS, D., AND MOORBY, P. The Verilog Hardware Description Language.
Kluwer Academic Publishers, Boston, Massechusetts, 1991.
[44] Topological sorting. http://en.wikipedia.org/wiki/Topological_sorting.
[45] WENZEL, I., KIRNER, R., PUSCHNER, P., AND RIEDER, B. Principles of tim-ing anomalies in superscalar processors. InProceedings of the Fifth International Conference on Quality Software (Washington, DC, USA, 2005), QSIC ’05, IEEE Computer Society, pp. 295–306.
[46] WERNER, T., AND AKELLA, V. Asynchronous processor survey. IEEE Com-puter 30, 11 (1997), 67–76.
[47] WILHELM, R., GRUND, D., REINEKE, J., SCHLICKLING, M., PISTER, M., AND FERDINAND, C. Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems. IEEE Transactions on CAD of Integrated Circuits and Systems 28, 7 (July 2009), 966–978.
Index
abstract collecting path semantics .19 abstract interpretation . . . .15abstract state transformer step . . . . .37
abstract sticky collecting semantics21
local worst-case2,12,33,43–46,53,56 LWC transition . . . .46
O
out-of-order execution . . . .11
overestimation . . . .69
P
P-LRU . . . .13,55 path semantics . . . .18pipeline stages . . . .6
prediction graph . . . .29,39,40 prefetch mechanism . . . .8
processor complexity . . . .24
S
scheduling timing anomaly . . . .54speculation timing anomaly . .55,109, 116,119,128 speculative execution . . . .12
split . . . .37
state abstraction function . . . .36
state collecting path semantics .34,35 state collecting transformer . . . 34
state concretization function . . . .35
state transformer . . . .34
state transformer step . . . .34
state transition difference . . . .48
static branch prediction . . . .9
sticky collecting semantics . . . .18
superscalar processor . . . .10
synchronous processor . . . .31