Analog Test Bus Standard

17.1 Inductance measurement

φ = LI, V = LdI dt

One test method would be to apply a current ramp to the inductor while mea-suring the voltage across it, which should be constant. We will ignore the startup and shutdown transients and just look at the steady-state response.

Since all of the switches induce a voltage drop (due to their 100Ω resistance), we can first disable the inductor by applying a known DC current and measuring the voltage drop in the system. Then, we can calculate the efective series resitance:

V = IR_{ef f}, so, R_{ef f} = I V For the current ramp test,

V = R_{ef f}I(t) + LdI dt Let I(t) = 0 + 50 mA/s× t, so ^dI_dt = 50 mA/s. Then,

V (t) = R_{ef f} ×50 mA

s t + L×50 mA s So,

L = V (t)− Ref f50^mA_s t 50 mA/s or

L = V (t)

50 mA/s − Ref ft Test method (see Figure 17.8, page 586 of the book):

I. Measure R_{ef f}

A. Turn on S5, S6, SB1(pin1), SB2(pin1), SG(pin1), and force 100µA of current into AT 1 with ATE current source.

B. Measure voltage V₁ between AT 2 and ground.

C. Turn off SB2 at pin1 and turn on SB2 at pin2.

D. Measure voltage V₂ between AT 2 and ground.

E. V = V₁ − V2. If this is not 0, then there is significant current leakage through AT 2 or there is series resistance in the inductor.

R_{ef f} = V1− V2

100µA We assume the latter.

II. Measure L

A. Turn off SB2 at pin2 and turn on SB2 at pin1.

B. Apply this current ramp through AT 1:

t slope=50mA/s

Current, I

0

C. Measure V at two different time instants t1 and t2 (chosen so that the startup transient at t = 0 has died down.) Use steps I, B through D, to do this.

D. Compute L twice:

L = V (t)− Ref f50mA s t 50mA/s

The measurements L₁and L₂should agree within 60×10⁻¹⁰H. If they do not agree within that tolerance, reject the inductor. Otherwise, average the measurements:

L_ave = L₁+ L₂ 2

Verify that 59.994µH ≤ Lave ≤ 60.006µH. If Lave is not in this range, reject the inductor.

An error V_err(t) in the V (t) measurement changes the calculated L by

∆L =± V_err(t) 50mA/s

Measurement error exceeds inductor tolerance. This is an unreliable test! We need to change the current slope.

To have |∆L| ≤ ¹₂60µH× 10⁻⁴, we need dI

dt = 20µV

|∆L| = 20µV

1

260µH× 10⁻⁴ = 6666.67 A/s

Redesign the test with this ^dI_dt, and with sampling times t₁ and t₂ so that we only get 100mA maximum current.

t₁, t₂< 100mA

6666.67 A/s = 0.150µs

This may or may not cause a problem with the startup transient being sampled.

Alternative solution:

Apply a sinusoidal current waveform to the inductor and measure the voltage across it, which should have some phase shift. Ignore startup and shutdown tran-sients and just look at the steady-state response.

We assume that the system voltmeter has extremely high impedance, so that we can ignore the current through it and, therefore, we do not model AB2 R⁰s. Then:

V₁ = I(100Ω + jωL) V2 = I(100Ω) V₁− V2 = jωLI

Z = jωL =√

ω²L²= ωL L = V1− V2

ωI

Test method (see Figure 17.8, page 586 of the book):

I. Repeat prior part I to calculate R_{ef f} (series resistance of inductor.) II. Measure L

A. Turn off SB2 at pin2 and turn on SB2 at pin1.

B. Apply I = sin(2π× 60t) through AT 1.

C. Measure V₁ and V₂.

D. V1− V2 = I(R_{ef f} + jωL), ω = 2π60 rad/s

Z = R_{ef f} + jωL =^qR_{ef f}² + ω²L² So,

(V1− V2)²

I² = R²_{ef f} + ω²L² L = 1

ω

s(V₁− V2)²

I² − R_{ef f}²

Both Ref f and V1−V2 have an error term proportional to voltmeter error.

17.2 Capacitance measurement

Q = CV, I = CdV dt

One test method would be to apply a voltage ramp to the capacitor while mea-suring the current across it, which should be constant. We will ignore the startup and shutdown transients and just look at the steady-state response.

Since all of the switches induce voltage drop (due to their 100Ω impedance), we can first disable the capacitor by applying a known DC voltage and measuring the current in the system. Then, we can calculate the effective series resistance.

I = V

R_{ef f} so R_{ef f} = I V For the voltage ramp test,

V = IR_{ef f} + Z _t

0

Idt

C or

dV

dt = I

C (since I will be constant) So,

C = I

dV /dt, choose dV

dt = 50mV /s Test method (see Figure 17.8 on page 586 of the book):

I. Optionally measure R_{ef f} (not needed for accurate C measurement.) Method is the same as for Part I of solution to Problem 17.1.

II. Measure C

A. Turn on S5, S6, SB1 (pin 1), SG (pin 1), and SB2 ant pin 1.

B. Turn off SB2 at pin 2.

C. Apply the voltage ramp, shown below, at AT 1.

0 t

slope=50mV/s

Voltage, V

E. Compute C twice:

C = I

dV /dt

The measurements should agree within 0.02nF . If they do not, reject the capacitor. Otherwise, average the measurements.

C_ave = C₁+ C₂

199.98nF ≤ Cave≤ 200.02nF If not, reject the capacitor.

Alternative solution:

Apply a sinusoidal current waveform to the capacitor and measure the voltage in the circuit, which should have some phase shift. Ignore startup and shutdown transients, and just look at the steady state response. Ignore impedances of S6 and SB2 in AT 2, since the voltmeter has very high impedance.

V₁ = I(100Ω + 1 jωC) V₂ = I(100Ω)

V₁− V2 = I jωC

Z = 1

jωC = jωC

−ω²C² =

sω²C² ω⁴C⁴ = 1

ωC

C = I

ωC(V1− V2)

Test method to measure C (see Figure 17.8 on page 586 of the book):

A. Turn off SB2 at pin 2 and turn on SB2 at pin 1.

B. Turn on S5, SB1 at pin 1, and SG at pin 2.

C. Apply I = sin(2π× 60t) through AT 1.

D. Measure V1 and V2,

Z = 1

ωC, so (V₁− V2)²

I₂ = ω²C² C =

s(V₁− V2)² ωI

17.3 Resistance measurement

To measure a resistance R of value 40Ω±10%, we proceed as follows (see Figure 17.8 on page 586 of the book):

A. Turn on S5, S6, SB1 (pin 1), SB2 (pin 2), SG (pin 1) and force 100µA of current into AT 1 with ATE current source (AT 1 connects to AB1, AT 2 connects to AB2.)

B. Measure voltage V₁ between AT 2 and Ground.

C. Turn off SB2 at pin 1 and turn on SB2 at pin 2.

D. Measure voltage V₂ between AT 2 and Ground.

E. V = V₁− V2 and R_{ef f} = V₁− V2. This will be correct only if the ATE system voltmeter has extremely high impedance (so that current flow in AT 2 can be ignored.) If that holds, there is no voltage drop in SB2 at pins 1 and 2 and at S6 in AT 2. However, notice that the external R that we are measuring (40Ω) is smaller than 100Ω, the switch resistance.

First, we calculate the effect of voltmeter measurement error of 20µV : V_{1ef f} = V₁+ 20µV

V_{2ef f} = V₂− 20µV

R_{ef f} = V1± 20µV − (V2∓ 20µV ) 100µA

= V₁− V2

100µA ± 0.4Ω

The error of 0.4Ω equals the tolerance on the resistor value of 40Ω. Although this test can be used, it will most likely reject the vast bulk of resistors tested. A better test would be to reduce the ATE system voltmeter measurement error to 2µV . Alternatively, the circuit under test can be redesigned not to use such low-valued R’s.

We should now calculate a bound on the leakage current I_leak in the voltmeter on AT 2.

V1AT 2 = V1− (RSB2p1+ RS6)I_leak V_{2AT 2} = V₂− (RSB2p2+ R_S6)I_leak

V_{1AT 2}− V2AT 2 = V₁− V2− Ileak(R_SB2p1+ R_S6− RSB2p2− RS6) V₁− V2 = V_{1AT 2}− V2AT 2− Ileak(R_SB2p1− RSB2p2)

Error = ±Ileak(R_SB2 mismatch between pins 1 and 2)

R_SB2 mismatch Upper bound on Ileak

10Ω 0.2µA

5Ω 0.4µA

2Ω 1.0µA

1Ω 2.0µA

0.1Ω 20.0µA

17.4 Analog core test

The difference between INTEST and PROBE instructions for testing an analog core is as follows. PROBE does not require boundary scan hardware on lines from digital circuits to analog circuits, whereas INTEST does. As a result, the PROBE instruction lets internal digital circuits interact with the analog core, while INTEST disconnects the digital core and replaces it with set up patterns from the boundary register.

17.5 Bus impedance calibration

Measurement of resistive impedance in AT 1 and AT 2 buses:

1. In the test bus interface circuit (TBIC), close switch S1 connecting AT 1 to V_H. Ground the other end of AT 1 at the automatic test equipment (ATE).

Measure the current in AT 1, I = (VH− 0)/RAT 1. So, RAT 1 = VH/I.

2. Repeat step 1, but using AT 2 and closing switch S2. Thus, R_{AT 2}= V_H/I.

3. In the TBIC, close switch S3 to connect AT 1 to V_L. Set the other end of AT 1 to V_DD at the ATE. Measure the current in AT 1, I = (V_DD− VL)/R_{AT 1}. So, R_{AT 1} = (V_DD− VL)/I. Compare this value to the result of step 1.

4. Repeat step 3, but using AT 2 and closing switch S4 in the TBIC. Thus, R_{AT 2} = (V_DD− VL)/I. Compare this value to the result of step 2.

An alternative procedure:

1. Disconnect all pins from AB1.

2. In the TBIC. close switches S5 and S8 to connect both AT 1 and AT 2 together through AB1.

3. Drive AT 1 with a voltage V1 and drive AT 2 with V2. Measure the current I flowing into AT 2 at the ATE:

I = V₁− V2

R_total So,

R_total= V1− V2

I

17.6 Bus impedance calibration

1. First, measure resistance in AT 1 and AT 2 switches S5 through S8.

2. At a given pin, connect AB1 by closing SB1 and close SG for that pin. All other pin switches should be open. Connect AT 1 to AB1. Force V_DD into AT 1 at the automatic test equipment (ATE). Measure I at AT 1:

ATE AT1 S5 AB1 SB1

SG VDD

V_G TBIC

Analog pin

I = V_DD− VG

R_S5+ R_SB1+ R_SG So,

R_SB1+ R_SG= V_DD− VG

I − RS5

Assume:

RS5= R_S5+ R_S8

2 , from Problem 17.5 3. Repeat step 2 closing SL at the pin rather than SG. Then,

R_SB1+ R_SL= V_DD− VL

I − RS5

4. Repeat steps 1 through 3, but using AB2 instead of AB1 and R_S7rather than R_S5.

Alternative method:

1. Probe the analog pin with the ATE.

2. Measure resistance in AT 1 and AT 2 switches S5 through S8.

3. At the pin, connect AB1 by closing SB1 for that pin. All other pin switches should be open. Connect AT 1 to AB1. Force V_DD into AT 1 at the ATE.

Make the ATE force the analog pin to ground. Measure I at AT 1.

AB1 S5

AT1 SB1

VDD Analog pin

I = V_DD R_S5+ R_SB1 R_SB1 = V_DD

I − RS5

R_S5 = R_S5+ R_S8

2 , from Problem 17.5

4. Repeat step 3, but using AB2 instead of AB1 and R_S7 rather than R_S5.

In document Solutions to Problems from Essentials of Electronic Testing (Page 168-177)