The last analog element in a typical measurement system is the analog-to-digital converter (ADC), Figure 1.1. As the name implies, this electronic component converts an analog voltage to an equivalent digital number. In the process of analog-to-digital conversion an analog or continuous waveform, x(t), is con-verted into a discrete waveform, x(n), a function of real numbers that are defined only at discrete integers, n. To convert a continuous waveform to digital format requires slicing the signal in two ways: slicing in time and slicing in amplitude (Figure 1.10).
Slicing the signal into discrete points in time is termed time sampling or simply sampling. Time slicing samples the continuous waveform, x(t), at dis-crete prints in time, nTs, where Ts is the sample interval. The consequences of time slicing are discussed in the next chapter. The same concept can be applied to images wherein a continuous image such as a photograph that has intensities that vary continuously across spatial distance is sampled at distances of S mm.
In this case, the digital representation of the image is a two-dimensional array.
The consequences of spatial sampling are discussed in Chapter 11.
Since the binary output of the ADC is a discrete integer while the analog signal has a continuous range of values, analog-to-digital conversion also re-quires the analog signal to be sliced into discrete levels, a process termed quanti-zation, Figure 1.10. The equivalent number can only approximate the level of
FIGURE1.10 Converting a continuous signal (solid line) to discrete format re-quires slicing the signal in time and amplitude. The result is a series of discrete points (X’s) that approximate the original signal.
Introduction 19
the analog signal, and the degree of approximation will depend on the range of binary numbers and the amplitude of the analog signal. For example, if the output of the ADC is an 8-bit binary number capable of 28or 256 discrete states, and the input amplitude range is 0.0–5.0 volts, then the quantization interval will be 5/256 or 0.0195 volts. If, as is usually the case, the analog signal is time varying in a continuous manner, it must be approximated by a series of binary numbers representing the approximate analog signal level at discrete points in time (Figure 1.10). The errors associated with amplitude slicing, or quantization, are described in the next section, and the potential error due to sampling is covered in Chapter 2. The remainder of this section briefly describes the hard-ware used to achieve this approximate conversion.
Analog-to-Digital Conversion Techniques
Various conversion rules have been used, but the most common is to convert the voltage into a proportional binary number. Different approaches can be used to implement the conversion electronically; the most common is the successive approximation technique described at the end of this section. ADC’s differ in conversion range, speed of conversion, and resolution. The range of analog volt-ages that can be converted is frequently software selectable, and may, or may not, include negative voltages. Typical ranges are from 0.0–10.0 volts or less, or if negative values are possible ± 5.0 volts or less. The speed of conversion is specified in terms of samples per second, or conversion time. For example, an ADC with a conversion time of 10µsec should, logically, be able to operate at up to 100,000 samples per second (or simply 100 kHz). Typical conversion rates run up to 500 kHz for moderate cost converters, but off-the-shelf converters can be obtained with rates up to 10–20 MHz. Except for image processing systems, lower conversion rates are usually acceptable for biological signals.
Even image processing systems may use downsampling techniques to reduce the required ADC conversion rate and, hence, the cost.
A typical ADC system involves several components in addition to the actual ADC element, as shown in Figure 1.11. The first element is an N-to-1 analog switch that allows multiple input channels to be converted. Typical ADC systems provide up to 8 to 16 channels, and the switching is usually software-selectable. Since a single ADC is doing the conversion for all channels, the conversion rate for any given channel is reduced in proportion to the number of channels being converted. Hence, an ADC system with converter element that had a conversion rate of 50 kHz would be able to sample each of eight channels at a theoretical maximum rate of 50/8= 6.25 kHz.
The Sample and Hold is a high-speed switch that momentarily records the input signal, and retains that signal value at its output. The time the switch is closed is termed the aperture time. Typical values range around 150 ns, and, except for very fast signals, can be considered basically instantaneous. This
FIGURE1.11 Block diagram of a typical analog-to-digital conversion system.
instantaneously sampled voltage value is held (as a charge on a capacitor) while the ADC element determines the equivalent binary number. Again, it is the ADC element that determines the overall speed of the conversion process.
Quantization Error
Resolution is given in terms of the number of bits in the binary output with the assumption that the least significant bit (LSB) in the output is accurate (which may not always be true). Typical converters feature 8-, 12-, and 16-bit output with 12 bits presenting a good compromise between conversion resolution and cost. In fact, most signals do not have a sufficient signal-to-noise ratio to justify a higher resolution; you are simply obtaining a more accurate conversion of the noise. For example, assuming that converter resolution is equivalent to the LSB, then the minimum voltage that can be resolved is the same as the quantization voltage described above: the voltage range divided by 2N, where N is the number of bits in the binary output. The resolution of a 5-volt, 12-bit ADC is 5.0/212= 5/4096= 0.0012 volts. The dynamic range of a 12-bit ADC, the range from the smallest to the largest voltage it can convert, is from 0.0012 to 5 volts: in db this is 20 * log*1012* = 167 db. Since typical signals, especially those of biologi-cal origin, have dynamic ranges rarely exceeding 60 to 80 db, a 12-bit converter with the dynamic range of 167 db may appear to be overkill. However, having this extra resolution means that not all of the range need be used, and since 12-bit ADC’s are only marginally more expensive than 8-12-bit ADC’s they are often used even when an 8-bit ADC (with dynamic range of over 100 DB, would be adequate). A 12-bit output does require two bytes to store and will double the memory requirements over an 8-bit ADC.
Introduction 21
The number of bits used for conversion sets a lower limit on the resolu-tion, and also determines the quantization error (Figure 1.12). This error can be thought of as a noise process added to the signal. If a sufficient number of quantization levels exist (say N> 64), the distortion produced by quantization error may be modeled as additive independent white noise with zero mean with the variance determined by the quantization step size, δ = VMAX/2N. Assuming that the error is uniformly distributed between −δ/2 +δ/2, the variance, σ, is:
σ =
∫
−δ/2δ/2 η2/δ dη = V2Max(2−2N)/12 (8) Assuming a uniform distribution, the RMS value of the noise would be just twice the standard deviation,σ.Further Study: Successive Approximation
The most popular analog-to-digital converters use a rather roundabout strategy to find the binary number most equivalent to the input analog voltage—a digi-tal-to-analog converter (DAC) is placed in a feedback loop. As shown Figure 1.13, an initial binary number stored in the buffer is fed to a DAC to produce a
FIGURE 1.12 Quantization (amplitude slicing) of a continuous waveform. The lower trace shows the error between the quantized signal and the input.
FIGURE1.13 Block diagram of an analog-to-digital converter. The input analog voltage is compared with the output of a digital-to-analog converter. When the two voltages match, the number held in the binary buffer is equivalent to the input voltage with the resolution of the converter. Different strategies can be used to adjust the contents of the binary buffer to attain a match.
proportional voltage, VDAC. This DAC voltage, VDAC, is then compared to the input voltage, and the binary number in the buffer is adjusted until the desired level of match between VDACand Vinis obtained. This approach begs the question
“How are DAC’s constructed?” In fact, DAC’s are relatively easy to construct using a simple ladder network and the principal of current superposition.
The controller adjusts the binary number based on whether or not the comparator finds the voltage out of the DAC, VDAC, to be greater or less than the input voltage, Vin. One simple adjustment strategy is to increase the binary number by one each cycle if VDAC< Vin, or decrease it otherwise. This so-called tracking ADC is very fast when Vin changes slowly, but can take many cycles when Vin changes abruptly (Figure 1.14). Not only can the conversion time be quite long, but it is variable since it depends on the dynamics of the input signal.
This strategy would not easily allow for sampling an analog signal at a fixed rate due to the variability in conversion time.
An alternative strategy termed successive approximation allows the con-version to be done at a fixed rate and is well-suited to digital technology. The successive approximation strategy always takes the same number of cycles irre-spective of the input voltage. In the first cycle, the controller sets the most significant bit (MSB) of the buffer to 1; all others are cleared. This binary number is half the maximum possible value (which occurs when all the bits are
Introduction 23
FIGURE1.14 Voltage waveform of an ADC that uses a tracking strategy. The ADC voltage (solid line) follows the input voltage (dashed line) fairly closely when the input voltage varies slowly, but takes many cycles to “catch up” to an abrupt change in input voltage.
1), so the DAC should output a voltage that is half its maximum voltage—that is, a voltage in the middle of its range. If the comparator tells the controller that Vin> VDAC, then the input voltage, Vin, must be greater than half the maximum range, and the MSB is left set. If Vin< VDAC, then that the input voltage is in the lower half of the range and the MSB is cleared (Figure 1.15). In the next cycle, the next most significant bit is set, and the same comparison is made and the same bit adjustment takes place based on the results of the comparison (Figure 1.15).
After N cycles, where N is the number of bits in the digital output, the voltage from the DAC, VDAC, converges to the best possible fit to the input voltage, Vin. Since Vin⬇ VDAC, the number in the buffer, which is proportional to VDAC, is the best representation of the analog input voltage within the resolu-tion of the converter. To signal the end of the conversion process, the ADC puts
FIGURE 1.15 Vin and VDAC in a 6-bit ADC using the successive approximation strategy. In the first cycle, the MSB is set (solid line) since Vin> VDAC. In the next two cycles, the bit being tested is cleared because Vin< VDACwhen this bit was set. For the fourth and fifth cycles the bit being tested remained set and for the last cycle it was cleared. At the end of the sixth cycle a conversion complete flag is set to signify the end of the conversion process.
out a digital signal or flag indicating that the conversion is complete (Figure 1.15).